Timing Messages

Report Title Timing Analysis Report
Design File C:\Gowin\SV_240812_mhut_2001\add4bit\impl\gwsynthesis\add4bit.vg
Physical Constraints File C:\Gowin\SV_240812_mhut_2001\add4bit\src\add4bit.cst
Timing Constraint File C:\Gowin\SV_240812_mhut_2001\add4bit\src\add4bit.sdc
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Aug 12 11:36:51 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C6/I5
Hold Delay Model Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed 171
Numbers of Endpoints Analyzed 85
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk27mhz Base 37.037 27.000 0.000 18.518 clk
2 clk160hz Generated 6249993.500 0.000 0.000 3124996.750 clk clk27mhz clk_160hz

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk27mhz 27.000(MHz) 146.578(MHz) 5 TOP
2 clk160hz 0.000(MHz) 111.111(MHz) 4 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk27mhz Setup 0.000 0
clk27mhz Hold 0.000 0
clk160hz Setup 0.000 0
clk160hz Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 30.215 clkdiv_1/count_7_s0/Q clkdiv_1/count_1_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.779
2 30.215 clkdiv_1/count_7_s0/Q clkdiv_1/count_2_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.779
3 30.215 clkdiv_1/count_7_s0/Q clkdiv_1/count_3_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.779
4 30.215 clkdiv_1/count_7_s0/Q clkdiv_1/count_4_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.779
5 30.215 clkdiv_1/count_7_s0/Q clkdiv_1/count_5_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.779
6 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_6_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
7 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_7_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
8 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_8_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
9 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_9_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
10 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_10_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
11 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_11_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
12 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_18_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
13 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_19_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
14 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_20_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
15 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_21_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
16 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_22_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
17 30.219 clkdiv_1/count_7_s0/Q clkdiv_1/count_23_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.775
18 30.224 clkdiv_1/count_7_s0/Q clkdiv_1/count_25_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.770
19 30.224 clkdiv_1/count_7_s0/Q clkdiv_1/count_24_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.770
20 30.599 clkdiv_1/count_22_s0/Q clkdiv_1/clk_out_s1/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.395
21 30.636 clkdiv_1/count_7_s0/Q clkdiv_1/count_12_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.358
22 30.636 clkdiv_1/count_7_s0/Q clkdiv_1/count_13_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.358
23 30.636 clkdiv_1/count_7_s0/Q clkdiv_1/count_14_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.358
24 30.636 clkdiv_1/count_7_s0/Q clkdiv_1/count_15_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.358
25 30.636 clkdiv_1/count_7_s0/Q clkdiv_1/count_16_s0/RESET clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.358

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.709 clkdiv_1/count_0_s0/Q clkdiv_1/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
2 0.718 mux7seg_1/col_1_s0/Q mux7seg_1/col_1_s0/D clk160hz:[R] clk160hz:[R] 0.000 0.000 0.718
3 0.730 clkdiv_1/count_2_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.730
4 0.730 clkdiv_1/count_6_s0/Q clkdiv_1/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.730
5 0.730 clkdiv_1/count_8_s0/Q clkdiv_1/count_8_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.730
6 0.730 clkdiv_1/count_12_s0/Q clkdiv_1/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.730
7 0.730 clkdiv_1/count_14_s0/Q clkdiv_1/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.730
8 0.730 clkdiv_1/count_18_s0/Q clkdiv_1/count_18_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.730
9 0.730 clkdiv_1/count_20_s0/Q clkdiv_1/count_20_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.730
10 0.730 clkdiv_1/count_24_s0/Q clkdiv_1/count_24_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.730
11 0.853 clkdiv_1/count_1_s0/Q clkdiv_1/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.853
12 0.962 clkdiv_1/count_5_s0/Q clkdiv_1/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.962
13 0.962 clkdiv_1/count_7_s0/Q clkdiv_1/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.962
14 0.962 clkdiv_1/count_13_s0/Q clkdiv_1/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.962
15 0.965 clkdiv_1/count_25_s0/Q clkdiv_1/count_25_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.965
16 0.965 clkdiv_1/count_3_s0/Q clkdiv_1/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.965
17 0.966 clkdiv_1/count_4_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.966
18 0.970 clkdiv_1/count_21_s0/Q clkdiv_1/count_21_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.970
19 0.970 clkdiv_1/count_22_s0/Q clkdiv_1/count_22_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.970
20 0.970 clkdiv_1/count_23_s0/Q clkdiv_1/count_23_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.970
21 0.971 clkdiv_1/count_9_s0/Q clkdiv_1/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.971
22 0.971 clkdiv_1/count_11_s0/Q clkdiv_1/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.971
23 0.971 clkdiv_1/count_16_s0/Q clkdiv_1/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.971
24 0.976 clkdiv_1/count_10_s0/Q clkdiv_1/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.976
25 0.976 clkdiv_1/count_15_s0/Q clkdiv_1/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.976

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_24_s0
2 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_22_s0
3 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_18_s0
4 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_10_s0
5 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_11_s0
6 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_19_s0
7 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_12_s0
8 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/clk_out_s1
9 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_25_s0
10 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_13_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 30.215
Data Arrival Time 9.111
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.111 0.807 tNET RR 1 R15C23[0][B] clkdiv_1/count_1_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C23[0][B] clkdiv_1/count_1_s0/CLK
39.326 -0.043 tSu 1 R15C23[0][B] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.136%; route: 2.380, 35.103%; tC2Q: 0.458, 6.761%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path2

Path Summary:

Slack 30.215
Data Arrival Time 9.111
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.111 0.807 tNET RR 1 R15C23[1][A] clkdiv_1/count_2_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C23[1][A] clkdiv_1/count_2_s0/CLK
39.326 -0.043 tSu 1 R15C23[1][A] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.136%; route: 2.380, 35.103%; tC2Q: 0.458, 6.761%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path3

Path Summary:

Slack 30.215
Data Arrival Time 9.111
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.111 0.807 tNET RR 1 R15C23[1][B] clkdiv_1/count_3_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C23[1][B] clkdiv_1/count_3_s0/CLK
39.326 -0.043 tSu 1 R15C23[1][B] clkdiv_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.136%; route: 2.380, 35.103%; tC2Q: 0.458, 6.761%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path4

Path Summary:

Slack 30.215
Data Arrival Time 9.111
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.111 0.807 tNET RR 1 R15C23[2][A] clkdiv_1/count_4_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C23[2][A] clkdiv_1/count_4_s0/CLK
39.326 -0.043 tSu 1 R15C23[2][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.136%; route: 2.380, 35.103%; tC2Q: 0.458, 6.761%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path5

Path Summary:

Slack 30.215
Data Arrival Time 9.111
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.111 0.807 tNET RR 1 R15C23[2][B] clkdiv_1/count_5_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C23[2][B] clkdiv_1/count_5_s0/CLK
39.326 -0.043 tSu 1 R15C23[2][B] clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.136%; route: 2.380, 35.103%; tC2Q: 0.458, 6.761%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path6

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C24[0][A] clkdiv_1/count_6_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C24[0][A] clkdiv_1/count_6_s0/CLK
39.326 -0.043 tSu 1 R15C24[0][A] clkdiv_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path7

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
39.326 -0.043 tSu 1 R15C24[0][B] clkdiv_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path8

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_8_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C24[1][A] clkdiv_1/count_8_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C24[1][A] clkdiv_1/count_8_s0/CLK
39.326 -0.043 tSu 1 R15C24[1][A] clkdiv_1/count_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path9

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C24[1][B] clkdiv_1/count_9_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C24[1][B] clkdiv_1/count_9_s0/CLK
39.326 -0.043 tSu 1 R15C24[1][B] clkdiv_1/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path10

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C24[2][A] clkdiv_1/count_10_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C24[2][A] clkdiv_1/count_10_s0/CLK
39.326 -0.043 tSu 1 R15C24[2][A] clkdiv_1/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path11

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C24[2][B] clkdiv_1/count_11_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C24[2][B] clkdiv_1/count_11_s0/CLK
39.326 -0.043 tSu 1 R15C24[2][B] clkdiv_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path12

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_18_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C26[0][A] clkdiv_1/count_18_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C26[0][A] clkdiv_1/count_18_s0/CLK
39.326 -0.043 tSu 1 R15C26[0][A] clkdiv_1/count_18_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path13

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_19_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C26[0][B] clkdiv_1/count_19_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C26[0][B] clkdiv_1/count_19_s0/CLK
39.326 -0.043 tSu 1 R15C26[0][B] clkdiv_1/count_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path14

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_20_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C26[1][A] clkdiv_1/count_20_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C26[1][A] clkdiv_1/count_20_s0/CLK
39.326 -0.043 tSu 1 R15C26[1][A] clkdiv_1/count_20_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path15

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_21_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C26[1][B] clkdiv_1/count_21_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C26[1][B] clkdiv_1/count_21_s0/CLK
39.326 -0.043 tSu 1 R15C26[1][B] clkdiv_1/count_21_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path16

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_22_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C26[2][A] clkdiv_1/count_22_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C26[2][A] clkdiv_1/count_22_s0/CLK
39.326 -0.043 tSu 1 R15C26[2][A] clkdiv_1/count_22_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path17

Path Summary:

Slack 30.219
Data Arrival Time 9.107
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_23_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.107 0.803 tNET RR 1 R15C26[2][B] clkdiv_1/count_23_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C26[2][B] clkdiv_1/count_23_s0/CLK
39.326 -0.043 tSu 1 R15C26[2][B] clkdiv_1/count_23_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.170%; route: 2.376, 35.065%; tC2Q: 0.458, 6.765%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path18

Path Summary:

Slack 30.224
Data Arrival Time 9.102
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_25_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.102 0.798 tNET RR 1 R15C27[0][B] clkdiv_1/count_25_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C27[0][B] clkdiv_1/count_25_s0/CLK
39.326 -0.043 tSu 1 R15C27[0][B] clkdiv_1/count_25_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.214%; route: 2.370, 35.015%; tC2Q: 0.458, 6.770%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path19

Path Summary:

Slack 30.224
Data Arrival Time 9.102
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_24_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
9.102 0.798 tNET RR 1 R15C27[0][A] clkdiv_1/count_24_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C27[0][A] clkdiv_1/count_24_s0/CLK
39.326 -0.043 tSu 1 R15C27[0][A] clkdiv_1/count_24_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 58.214%; route: 2.370, 35.015%; tC2Q: 0.458, 6.770%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path20

Path Summary:

Slack 30.599
Data Arrival Time 8.726
Data Required Time 39.326
From clkdiv_1/count_22_s0
To clkdiv_1/clk_out_s1
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C26[2][A] clkdiv_1/count_22_s0/CLK
2.790 0.458 tC2Q RF 2 R15C26[2][A] clkdiv_1/count_22_s0/Q
3.135 0.345 tNET FF 1 R15C26[3][B] clkdiv_1/n7_s89/I1
4.234 1.099 tINS FF 1 R15C26[3][B] clkdiv_1/n7_s89/F
4.239 0.005 tNET FF 1 R15C26[3][A] clkdiv_1/n7_s86/I3
5.265 1.026 tINS FR 2 R15C26[3][A] clkdiv_1/n7_s86/F
5.686 0.421 tNET RR 1 R15C25[3][B] clkdiv_1/clk_out_s7/I3
6.508 0.822 tINS RF 1 R15C25[3][B] clkdiv_1/clk_out_s7/F
7.329 0.821 tNET FF 1 R14C25[0][B] clkdiv_1/clk_out_s3/I3
8.390 1.061 tINS FR 1 R14C25[0][B] clkdiv_1/clk_out_s3/F
8.726 0.336 tNET RR 1 R14C25[1][B] clkdiv_1/clk_out_s1/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R14C25[1][B] clkdiv_1/clk_out_s1/CLK
39.326 -0.043 tSu 1 R14C25[1][B] clkdiv_1/clk_out_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.008, 62.679%; route: 1.928, 30.154%; tC2Q: 0.458, 7.168%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path21

Path Summary:

Slack 30.636
Data Arrival Time 8.690
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
8.690 0.386 tNET RR 1 R15C25[0][A] clkdiv_1/count_12_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C25[0][A] clkdiv_1/count_12_s0/CLK
39.326 -0.043 tSu 1 R15C25[0][A] clkdiv_1/count_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 61.984%; route: 1.959, 30.807%; tC2Q: 0.458, 7.209%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path22

Path Summary:

Slack 30.636
Data Arrival Time 8.690
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
8.690 0.386 tNET RR 1 R15C25[0][B] clkdiv_1/count_13_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C25[0][B] clkdiv_1/count_13_s0/CLK
39.326 -0.043 tSu 1 R15C25[0][B] clkdiv_1/count_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 61.984%; route: 1.959, 30.807%; tC2Q: 0.458, 7.209%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path23

Path Summary:

Slack 30.636
Data Arrival Time 8.690
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
8.690 0.386 tNET RR 1 R15C25[1][A] clkdiv_1/count_14_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C25[1][A] clkdiv_1/count_14_s0/CLK
39.326 -0.043 tSu 1 R15C25[1][A] clkdiv_1/count_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 61.984%; route: 1.959, 30.807%; tC2Q: 0.458, 7.209%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path24

Path Summary:

Slack 30.636
Data Arrival Time 8.690
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
8.690 0.386 tNET RR 1 R15C25[1][B] clkdiv_1/count_15_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C25[1][B] clkdiv_1/count_15_s0/CLK
39.326 -0.043 tSu 1 R15C25[1][B] clkdiv_1/count_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 61.984%; route: 1.959, 30.807%; tC2Q: 0.458, 7.209%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path25

Path Summary:

Slack 30.636
Data Arrival Time 8.690
Data Required Time 39.326
From clkdiv_1/count_7_s0
To clkdiv_1/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
3.602 0.812 tNET FF 1 R14C24[1][A] clkdiv_1/n7_s88/I1
4.634 1.032 tINS FF 1 R14C24[1][A] clkdiv_1/n7_s88/F
4.970 0.336 tNET FF 1 R14C24[0][B] clkdiv_1/n7_s83/I3
6.031 1.061 tINS FR 1 R14C24[0][B] clkdiv_1/n7_s83/F
6.450 0.419 tNET RR 1 R14C25[2][B] clkdiv_1/n7_s79/I0
7.272 0.822 tINS RF 1 R14C25[2][B] clkdiv_1/n7_s79/F
7.278 0.005 tNET FF 1 R14C25[3][B] clkdiv_1/n7_s78/I0
8.304 1.026 tINS FR 26 R14C25[3][B] clkdiv_1/n7_s78/F
8.690 0.386 tNET RR 1 R15C25[2][A] clkdiv_1/count_16_s0/RESET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C25[2][A] clkdiv_1/count_16_s0/CLK
39.326 -0.043 tSu 1 R15C25[2][A] clkdiv_1/count_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.941, 61.984%; route: 1.959, 30.807%; tC2Q: 0.458, 7.209%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_1/count_0_s0
To clkdiv_1/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C26[0][A] clkdiv_1/count_0_s0/CLK
1.910 0.333 tC2Q RR 4 R14C26[0][A] clkdiv_1/count_0_s0/Q
1.913 0.004 tNET RR 1 R14C26[0][A] clkdiv_1/n34_s2/I0
2.285 0.372 tINS RF 1 R14C26[0][A] clkdiv_1/n34_s2/F
2.285 0.000 tNET FF 1 R14C26[0][A] clkdiv_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C26[0][A] clkdiv_1/count_0_s0/CLK
1.577 0.000 tHld 1 R14C26[0][A] clkdiv_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path2

Path Summary:

Slack 0.718
Data Arrival Time 1.755
Data Required Time 1.036
From mux7seg_1/col_1_s0
To mux7seg_1/col_1_s0
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R14C25[1][B] clkdiv_1/clk_out_s1/Q
1.036 1.036 tNET RR 1 R15C29[0][A] mux7seg_1/col_1_s0/CLK
1.370 0.333 tC2Q RR 20 R15C29[0][A] mux7seg_1/col_1_s0/Q
1.383 0.013 tNET RR 1 R15C29[0][A] mux7seg_1/n9_s3/I1
1.755 0.372 tINS RF 1 R15C29[0][A] mux7seg_1/n9_s3/F
1.755 0.000 tNET FF 1 R15C29[0][A] mux7seg_1/col_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R14C25[1][B] clkdiv_1/clk_out_s1/Q
1.036 1.036 tNET RR 1 R15C29[0][A] mux7seg_1/col_1_s0/CLK
1.036 0.000 tHld 1 R15C29[0][A] mux7seg_1/col_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.036, 100.000%
Arrival Data Path Delay cell: 0.372, 51.788%; route: 0.013, 1.808%; tC2Q: 0.333, 46.405%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.036, 100.000%

Path3

Path Summary:

Slack 0.730
Data Arrival Time 2.306
Data Required Time 1.577
From clkdiv_1/count_2_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C23[1][A] clkdiv_1/count_2_s0/CLK
1.910 0.333 tC2Q RR 3 R15C23[1][A] clkdiv_1/count_2_s0/Q
1.912 0.002 tNET RR 2 R15C23[1][A] clkdiv_1/n32_s/I1
2.306 0.394 tINS RF 1 R15C23[1][A] clkdiv_1/n32_s/SUM
2.306 0.000 tNET FF 1 R15C23[1][A] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C23[1][A] clkdiv_1/count_2_s0/CLK
1.577 0.000 tHld 1 R15C23[1][A] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path4

Path Summary:

Slack 0.730
Data Arrival Time 2.306
Data Required Time 1.577
From clkdiv_1/count_6_s0
To clkdiv_1/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[0][A] clkdiv_1/count_6_s0/CLK
1.910 0.333 tC2Q RR 3 R15C24[0][A] clkdiv_1/count_6_s0/Q
1.912 0.002 tNET RR 2 R15C24[0][A] clkdiv_1/n28_s/I1
2.306 0.394 tINS RF 1 R15C24[0][A] clkdiv_1/n28_s/SUM
2.306 0.000 tNET FF 1 R15C24[0][A] clkdiv_1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[0][A] clkdiv_1/count_6_s0/CLK
1.577 0.000 tHld 1 R15C24[0][A] clkdiv_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path5

Path Summary:

Slack 0.730
Data Arrival Time 2.306
Data Required Time 1.577
From clkdiv_1/count_8_s0
To clkdiv_1/count_8_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[1][A] clkdiv_1/count_8_s0/CLK
1.910 0.333 tC2Q RR 3 R15C24[1][A] clkdiv_1/count_8_s0/Q
1.912 0.002 tNET RR 2 R15C24[1][A] clkdiv_1/n26_s/I1
2.306 0.394 tINS RF 1 R15C24[1][A] clkdiv_1/n26_s/SUM
2.306 0.000 tNET FF 1 R15C24[1][A] clkdiv_1/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[1][A] clkdiv_1/count_8_s0/CLK
1.577 0.000 tHld 1 R15C24[1][A] clkdiv_1/count_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path6

Path Summary:

Slack 0.730
Data Arrival Time 2.306
Data Required Time 1.577
From clkdiv_1/count_12_s0
To clkdiv_1/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[0][A] clkdiv_1/count_12_s0/CLK
1.910 0.333 tC2Q RR 3 R15C25[0][A] clkdiv_1/count_12_s0/Q
1.912 0.002 tNET RR 2 R15C25[0][A] clkdiv_1/n22_s/I1
2.306 0.394 tINS RF 1 R15C25[0][A] clkdiv_1/n22_s/SUM
2.306 0.000 tNET FF 1 R15C25[0][A] clkdiv_1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[0][A] clkdiv_1/count_12_s0/CLK
1.577 0.000 tHld 1 R15C25[0][A] clkdiv_1/count_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path7

Path Summary:

Slack 0.730
Data Arrival Time 2.306
Data Required Time 1.577
From clkdiv_1/count_14_s0
To clkdiv_1/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[1][A] clkdiv_1/count_14_s0/CLK
1.910 0.333 tC2Q RR 3 R15C25[1][A] clkdiv_1/count_14_s0/Q
1.912 0.002 tNET RR 2 R15C25[1][A] clkdiv_1/n20_s/I1
2.306 0.394 tINS RF 1 R15C25[1][A] clkdiv_1/n20_s/SUM
2.306 0.000 tNET FF 1 R15C25[1][A] clkdiv_1/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[1][A] clkdiv_1/count_14_s0/CLK
1.577 0.000 tHld 1 R15C25[1][A] clkdiv_1/count_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path8

Path Summary:

Slack 0.730
Data Arrival Time 2.306
Data Required Time 1.577
From clkdiv_1/count_18_s0
To clkdiv_1/count_18_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C26[0][A] clkdiv_1/count_18_s0/CLK
1.910 0.333 tC2Q RR 2 R15C26[0][A] clkdiv_1/count_18_s0/Q
1.912 0.002 tNET RR 2 R15C26[0][A] clkdiv_1/n16_s/I1
2.306 0.394 tINS RF 1 R15C26[0][A] clkdiv_1/n16_s/SUM
2.306 0.000 tNET FF 1 R15C26[0][A] clkdiv_1/count_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C26[0][A] clkdiv_1/count_18_s0/CLK
1.577 0.000 tHld 1 R15C26[0][A] clkdiv_1/count_18_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path9

Path Summary:

Slack 0.730
Data Arrival Time 2.306
Data Required Time 1.577
From clkdiv_1/count_20_s0
To clkdiv_1/count_20_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C26[1][A] clkdiv_1/count_20_s0/CLK
1.910 0.333 tC2Q RR 2 R15C26[1][A] clkdiv_1/count_20_s0/Q
1.912 0.002 tNET RR 2 R15C26[1][A] clkdiv_1/n14_s/I1
2.306 0.394 tINS RF 1 R15C26[1][A] clkdiv_1/n14_s/SUM
2.306 0.000 tNET FF 1 R15C26[1][A] clkdiv_1/count_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C26[1][A] clkdiv_1/count_20_s0/CLK
1.577 0.000 tHld 1 R15C26[1][A] clkdiv_1/count_20_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path10

Path Summary:

Slack 0.730
Data Arrival Time 2.306
Data Required Time 1.577
From clkdiv_1/count_24_s0
To clkdiv_1/count_24_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C27[0][A] clkdiv_1/count_24_s0/CLK
1.910 0.333 tC2Q RR 2 R15C27[0][A] clkdiv_1/count_24_s0/Q
1.912 0.002 tNET RR 2 R15C27[0][A] clkdiv_1/n10_s/I1
2.306 0.394 tINS RF 1 R15C27[0][A] clkdiv_1/n10_s/SUM
2.306 0.000 tNET FF 1 R15C27[0][A] clkdiv_1/count_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C27[0][A] clkdiv_1/count_24_s0/CLK
1.577 0.000 tHld 1 R15C27[0][A] clkdiv_1/count_24_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 53.995%; route: 0.002, 0.324%; tC2Q: 0.333, 45.681%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path11

Path Summary:

Slack 0.853
Data Arrival Time 2.429
Data Required Time 1.577
From clkdiv_1/count_1_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C23[0][B] clkdiv_1/count_1_s0/CLK
1.910 0.333 tC2Q RR 3 R15C23[0][B] clkdiv_1/count_1_s0/Q
1.912 0.002 tNET RR 2 R15C23[0][B] clkdiv_1/n33_s/I0
2.429 0.517 tINS RF 1 R15C23[0][B] clkdiv_1/n33_s/SUM
2.429 0.000 tNET FF 1 R15C23[0][B] clkdiv_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C23[0][B] clkdiv_1/count_1_s0/CLK
1.577 0.000 tHld 1 R15C23[0][B] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.517, 60.631%; route: 0.002, 0.277%; tC2Q: 0.333, 39.092%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path12

Path Summary:

Slack 0.962
Data Arrival Time 2.538
Data Required Time 1.577
From clkdiv_1/count_5_s0
To clkdiv_1/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C23[2][B] clkdiv_1/count_5_s0/CLK
1.910 0.333 tC2Q RF 3 R15C23[2][B] clkdiv_1/count_5_s0/Q
2.144 0.234 tNET FF 2 R15C23[2][B] clkdiv_1/n29_s/I1
2.538 0.394 tINS FF 1 R15C23[2][B] clkdiv_1/n29_s/SUM
2.538 0.000 tNET FF 1 R15C23[2][B] clkdiv_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C23[2][B] clkdiv_1/count_5_s0/CLK
1.577 0.000 tHld 1 R15C23[2][B] clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path13

Path Summary:

Slack 0.962
Data Arrival Time 2.538
Data Required Time 1.577
From clkdiv_1/count_7_s0
To clkdiv_1/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
1.910 0.333 tC2Q RF 3 R15C24[0][B] clkdiv_1/count_7_s0/Q
2.144 0.234 tNET FF 2 R15C24[0][B] clkdiv_1/n27_s/I1
2.538 0.394 tINS FF 1 R15C24[0][B] clkdiv_1/n27_s/SUM
2.538 0.000 tNET FF 1 R15C24[0][B] clkdiv_1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[0][B] clkdiv_1/count_7_s0/CLK
1.577 0.000 tHld 1 R15C24[0][B] clkdiv_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path14

Path Summary:

Slack 0.962
Data Arrival Time 2.538
Data Required Time 1.577
From clkdiv_1/count_13_s0
To clkdiv_1/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[0][B] clkdiv_1/count_13_s0/CLK
1.910 0.333 tC2Q RF 3 R15C25[0][B] clkdiv_1/count_13_s0/Q
2.144 0.234 tNET FF 2 R15C25[0][B] clkdiv_1/n21_s/I1
2.538 0.394 tINS FF 1 R15C25[0][B] clkdiv_1/n21_s/SUM
2.538 0.000 tNET FF 1 R15C25[0][B] clkdiv_1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[0][B] clkdiv_1/count_13_s0/CLK
1.577 0.000 tHld 1 R15C25[0][B] clkdiv_1/count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.964%; route: 0.234, 24.379%; tC2Q: 0.333, 34.657%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path15

Path Summary:

Slack 0.965
Data Arrival Time 2.541
Data Required Time 1.577
From clkdiv_1/count_25_s0
To clkdiv_1/count_25_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C27[0][B] clkdiv_1/count_25_s0/CLK
1.910 0.333 tC2Q RR 3 R15C27[0][B] clkdiv_1/count_25_s0/Q
2.147 0.238 tNET RR 2 R15C27[0][B] clkdiv_1/n9_s/I1
2.541 0.394 tINS RF 1 R15C27[0][B] clkdiv_1/n9_s/SUM
2.541 0.000 tNET FF 1 R15C27[0][B] clkdiv_1/count_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C27[0][B] clkdiv_1/count_25_s0/CLK
1.577 0.000 tHld 1 R15C27[0][B] clkdiv_1/count_25_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path16

Path Summary:

Slack 0.965
Data Arrival Time 2.541
Data Required Time 1.577
From clkdiv_1/count_3_s0
To clkdiv_1/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C23[1][B] clkdiv_1/count_3_s0/CLK
1.910 0.333 tC2Q RR 3 R15C23[1][B] clkdiv_1/count_3_s0/Q
2.147 0.238 tNET RR 2 R15C23[1][B] clkdiv_1/n31_s/I1
2.541 0.394 tINS RF 1 R15C23[1][B] clkdiv_1/n31_s/SUM
2.541 0.000 tNET FF 1 R15C23[1][B] clkdiv_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C23[1][B] clkdiv_1/count_3_s0/CLK
1.577 0.000 tHld 1 R15C23[1][B] clkdiv_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.833%; route: 0.238, 24.621%; tC2Q: 0.333, 34.546%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path17

Path Summary:

Slack 0.966
Data Arrival Time 2.543
Data Required Time 1.577
From clkdiv_1/count_4_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C23[2][A] clkdiv_1/count_4_s0/CLK
1.910 0.333 tC2Q RR 3 R15C23[2][A] clkdiv_1/count_4_s0/Q
2.149 0.239 tNET RR 2 R15C23[2][A] clkdiv_1/n30_s/I1
2.543 0.394 tINS RF 1 R15C23[2][A] clkdiv_1/n30_s/SUM
2.543 0.000 tNET FF 1 R15C23[2][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C23[2][A] clkdiv_1/count_4_s0/CLK
1.577 0.000 tHld 1 R15C23[2][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.783%; route: 0.239, 24.713%; tC2Q: 0.333, 34.503%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path18

Path Summary:

Slack 0.970
Data Arrival Time 2.547
Data Required Time 1.577
From clkdiv_1/count_21_s0
To clkdiv_1/count_21_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C26[1][B] clkdiv_1/count_21_s0/CLK
1.910 0.333 tC2Q RR 2 R15C26[1][B] clkdiv_1/count_21_s0/Q
2.153 0.243 tNET RR 2 R15C26[1][B] clkdiv_1/n13_s/I1
2.547 0.394 tINS RF 1 R15C26[1][B] clkdiv_1/n13_s/SUM
2.547 0.000 tNET FF 1 R15C26[1][B] clkdiv_1/count_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C26[1][B] clkdiv_1/count_21_s0/CLK
1.577 0.000 tHld 1 R15C26[1][B] clkdiv_1/count_21_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.621%; route: 0.243, 25.012%; tC2Q: 0.333, 34.366%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path19

Path Summary:

Slack 0.970
Data Arrival Time 2.547
Data Required Time 1.577
From clkdiv_1/count_22_s0
To clkdiv_1/count_22_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C26[2][A] clkdiv_1/count_22_s0/CLK
1.910 0.333 tC2Q RR 2 R15C26[2][A] clkdiv_1/count_22_s0/Q
2.153 0.243 tNET RR 2 R15C26[2][A] clkdiv_1/n12_s/I1
2.547 0.394 tINS RF 1 R15C26[2][A] clkdiv_1/n12_s/SUM
2.547 0.000 tNET FF 1 R15C26[2][A] clkdiv_1/count_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C26[2][A] clkdiv_1/count_22_s0/CLK
1.577 0.000 tHld 1 R15C26[2][A] clkdiv_1/count_22_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.621%; route: 0.243, 25.012%; tC2Q: 0.333, 34.366%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path20

Path Summary:

Slack 0.970
Data Arrival Time 2.547
Data Required Time 1.577
From clkdiv_1/count_23_s0
To clkdiv_1/count_23_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C26[2][B] clkdiv_1/count_23_s0/CLK
1.910 0.333 tC2Q RR 2 R15C26[2][B] clkdiv_1/count_23_s0/Q
2.153 0.243 tNET RR 2 R15C26[2][B] clkdiv_1/n11_s/I1
2.547 0.394 tINS RF 1 R15C26[2][B] clkdiv_1/n11_s/SUM
2.547 0.000 tNET FF 1 R15C26[2][B] clkdiv_1/count_23_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C26[2][B] clkdiv_1/count_23_s0/CLK
1.577 0.000 tHld 1 R15C26[2][B] clkdiv_1/count_23_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.621%; route: 0.243, 25.012%; tC2Q: 0.333, 34.366%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path21

Path Summary:

Slack 0.971
Data Arrival Time 2.548
Data Required Time 1.577
From clkdiv_1/count_9_s0
To clkdiv_1/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[1][B] clkdiv_1/count_9_s0/CLK
1.910 0.333 tC2Q RR 3 R15C24[1][B] clkdiv_1/count_9_s0/Q
2.154 0.244 tNET RR 2 R15C24[1][B] clkdiv_1/n25_s/I1
2.548 0.394 tINS RF 1 R15C24[1][B] clkdiv_1/n25_s/SUM
2.548 0.000 tNET FF 1 R15C24[1][B] clkdiv_1/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[1][B] clkdiv_1/count_9_s0/CLK
1.577 0.000 tHld 1 R15C24[1][B] clkdiv_1/count_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.572%; route: 0.244, 25.104%; tC2Q: 0.333, 34.325%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path22

Path Summary:

Slack 0.971
Data Arrival Time 2.548
Data Required Time 1.577
From clkdiv_1/count_11_s0
To clkdiv_1/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[2][B] clkdiv_1/count_11_s0/CLK
1.910 0.333 tC2Q RR 3 R15C24[2][B] clkdiv_1/count_11_s0/Q
2.154 0.244 tNET RR 2 R15C24[2][B] clkdiv_1/n23_s/I1
2.548 0.394 tINS RF 1 R15C24[2][B] clkdiv_1/n23_s/SUM
2.548 0.000 tNET FF 1 R15C24[2][B] clkdiv_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[2][B] clkdiv_1/count_11_s0/CLK
1.577 0.000 tHld 1 R15C24[2][B] clkdiv_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.572%; route: 0.244, 25.104%; tC2Q: 0.333, 34.325%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path23

Path Summary:

Slack 0.971
Data Arrival Time 2.548
Data Required Time 1.577
From clkdiv_1/count_16_s0
To clkdiv_1/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[2][A] clkdiv_1/count_16_s0/CLK
1.910 0.333 tC2Q RR 4 R15C25[2][A] clkdiv_1/count_16_s0/Q
2.154 0.244 tNET RR 2 R15C25[2][A] clkdiv_1/n18_s/I1
2.548 0.394 tINS RF 1 R15C25[2][A] clkdiv_1/n18_s/SUM
2.548 0.000 tNET FF 1 R15C25[2][A] clkdiv_1/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[2][A] clkdiv_1/count_16_s0/CLK
1.577 0.000 tHld 1 R15C25[2][A] clkdiv_1/count_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.572%; route: 0.244, 25.104%; tC2Q: 0.333, 34.325%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path24

Path Summary:

Slack 0.976
Data Arrival Time 2.553
Data Required Time 1.577
From clkdiv_1/count_10_s0
To clkdiv_1/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[2][A] clkdiv_1/count_10_s0/CLK
1.910 0.333 tC2Q RR 3 R15C24[2][A] clkdiv_1/count_10_s0/Q
2.159 0.249 tNET RR 2 R15C24[2][A] clkdiv_1/n24_s/I1
2.553 0.394 tINS RF 1 R15C24[2][A] clkdiv_1/n24_s/SUM
2.553 0.000 tNET FF 1 R15C24[2][A] clkdiv_1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C24[2][A] clkdiv_1/count_10_s0/CLK
1.577 0.000 tHld 1 R15C24[2][A] clkdiv_1/count_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.363%; route: 0.249, 25.490%; tC2Q: 0.333, 34.148%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path25

Path Summary:

Slack 0.976
Data Arrival Time 2.553
Data Required Time 1.577
From clkdiv_1/count_15_s0
To clkdiv_1/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[1][B] clkdiv_1/count_15_s0/CLK
1.910 0.333 tC2Q RR 3 R15C25[1][B] clkdiv_1/count_15_s0/Q
2.159 0.249 tNET RR 2 R15C25[1][B] clkdiv_1/n19_s/I1
2.553 0.394 tINS RF 1 R15C25[1][B] clkdiv_1/n19_s/SUM
2.553 0.000 tNET FF 1 R15C25[1][B] clkdiv_1/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[1][B] clkdiv_1/count_15_s0/CLK
1.577 0.000 tHld 1 R15C25[1][B] clkdiv_1/count_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.394, 40.363%; route: 0.249, 25.490%; tC2Q: 0.333, 34.148%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_24_s0/CLK

MPW2

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_22_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_22_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_22_s0/CLK

MPW3

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_18_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_18_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_18_s0/CLK

MPW4

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_10_s0/CLK

MPW5

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_11_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_11_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_11_s0/CLK

MPW6

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_19_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_19_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_19_s0/CLK

MPW7

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_12_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_12_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_12_s0/CLK

MPW8

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/clk_out_s1

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/clk_out_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/clk_out_s1/CLK

MPW9

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_25_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_25_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_25_s0/CLK

MPW10

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_13_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_13_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_13_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
27 clk_d 30.215 0.262
26 n7_108 30.215 0.847
20 col[1] 6249984.500 2.814
13 col[0] 6249985.000 2.777
13 clk_160hz 6249984.500 1.709
4 count[0] 31.698 1.296
4 count[16] 32.869 0.424
4 n13_12 6249984.500 1.141
4 count[17] 32.862 0.420
3 count[8] 32.167 0.424

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R15C24 80.56%
R15C25 80.56%
R15C26 76.39%
R15C23 62.50%
R15C27 48.61%
R15C29 47.22%
R14C25 31.94%
R14C26 31.94%
R14C28 26.39%
R14C27 23.61%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk160hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 168750 [get_nets {clk_160hz}]