PnR Messages

Report Title PnR Report
Design File C:\Gowin\SV_240812_mhut_2001\uart\impl\gwsynthesis\uart.vg
Physical Constraints File C:\Gowin\SV_240812_mhut_2001\uart\src\uart.cst
Timing Constraints File C:\Gowin\SV_240812_mhut_2001\uart\src\uart.sdc
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Aug 12 12:10:31 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.016s, Elapsed time = 0h 0m 0.016s Placement Phase 1: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.061s Placement Phase 2: CPU time = 0h 0m 0.007s, Elapsed time = 0h 0m 0.007s Placement Phase 3: CPU time = 0h 0m 0.744s, Elapsed time = 0h 0m 0.744s Total Placement: CPU time = 0h 0m 0.829s, Elapsed time = 0h 0m 0.828s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.116s, Elapsed time = 0h 0m 0.116s Routing Phase 2: CPU time = 0h 0m 0.143s, Elapsed time = 0h 0m 0.142s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.259s, Elapsed time = 0h 0m 0.258s Generate output files: CPU time = 0h 0m 0.655s, Elapsed time = 0h 0m 0.655s
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 262MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 246/8640 3%
    --LUT,ALU,ROM16 246(246 LUT, 0 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 126/6693 2%
    --Logic Register as Latch 0/6480 0%
    --Logic Register as FF 103/6480 2%
    --I/O Register as Latch 0/213 0%
    --I/O Register as FF 23/213 11%
CLS 146/4320 4%
I/O Port 33 -
I/O Buf 33 -
    --Input Buf 12 -
    --Output Buf 21 -
    --Inout Buf 0 -
IOLOGIC 0 0%
BSRAM 0 0%
DSP 00%
PLL 0/2 0%
DCS 0/8 0%
DQCE 0/24 0%
OSC 0/1 0%
User Flash 0/1 0%
CLKDIV 0/8 0%
DLLDLY 0/8 0%
DHCEN 0/8 0%
DHCENC 0/4 0%

I/O Bank Usage Summary:

I/O Bank Usage
bank 1 15/25(60%)
bank 2 18/23(78%)
bank 3 0/23(0%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 5/8(63%)
LW 1/8(13%)
GCLK_PIN 2/3(67%)
PLL 0/2(0%)
CLKDIV 0/8(0%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
clk_d PRIMARY BL
clkbaudhz PRIMARY BR BL
clkbaudx2hz PRIMARY BR BL
clk400hz PRIMARY TR BR
clk160hz PRIMARY TR BR BL
nrst_d LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk 52/1 Y in IOR17[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
nrst 73/1 Y in IOT39[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
tx_data[0] 28/2 Y in IOB11[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tx_data[1] 27/2 Y in IOB11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tx_data[2] 26/2 Y in IOB8[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tx_data[3] 25/2 Y in IOB8[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tx_data[4] 39/2 Y in IOB33[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tx_data[5] 36/2 Y in IOB29[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tx_data[6] 37/2 Y in IOB31[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tx_data[7] 38/2 Y in IOB31[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
send 70/1 Y in IOT41[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
rxd 18/2 Y in IOB2[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
txd 17/2 Y out IOB2[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
led[0] 69/1 Y out IOT42[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
led[1] 68/1 Y out IOT42[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
led[2] 57/1 Y out IOR13[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
led[3] 56/1 Y out IOR14[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
led[4] 55/1 Y out IOR14[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
led[5] 54/1 Y out IOR15[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
led[6] 53/1 Y out IOR15[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
led[7] 51/1 Y out IOR17[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
seg[0] 42/2 Y out IOB41[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[1] 41/2 Y out IOB41[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[2] 35/2 Y out IOB29[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[3] 40/2 Y out IOB33[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[4] 34/2 Y out IOB23[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[5] 33/2 Y out IOB23[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[6] 30/2 Y out IOB13[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[7] 29/2 Y out IOB13[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
dig[0] 74/1 Y out IOT38[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
dig[1] 75/1 Y out IOT38[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
dig[2] 76/1 Y out IOT37[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
dig[3] 77/1 Y out IOT37[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/3 - in IOT2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
88/3 - in IOT5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
87/3 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
86/3 - in IOT8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
85/3 - in IOT8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
84/3 - in IOT10[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
83/3 - in IOT10[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
82/3 - in IOT11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
81/3 - in IOT11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
80/3 - in IOT12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
79/3 - in IOT12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
77/1 dig[3] out IOT37[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
76/1 dig[2] out IOT37[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
75/1 dig[1] out IOT38[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
74/1 dig[0] out IOT38[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
73/1 nrst in IOT39[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
72/1 - in IOT39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
71/1 - in IOT41[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
70/1 send in IOT41[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
69/1 led[0] out IOT42[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
68/1 led[1] out IOT42[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
17/2 txd out IOB2[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
18/2 rxd in IOB2[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
19/2 - in IOB4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
20/2 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
25/2 tx_data[3] in IOB8[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
26/2 tx_data[2] in IOB8[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
27/2 tx_data[1] in IOB11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
28/2 tx_data[0] in IOB11[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
29/2 seg[7] out IOB13[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
30/2 seg[6] out IOB13[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
31/2 - in IOB15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
32/2 - in IOB15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
33/2 seg[5] out IOB23[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
34/2 seg[4] out IOB23[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
35/2 seg[2] out IOB29[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
36/2 tx_data[5] in IOB29[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
37/2 tx_data[6] in IOB31[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
38/2 tx_data[7] in IOB31[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
39/2 tx_data[4] in IOB33[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
40/2 seg[3] out IOB33[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
41/2 seg[1] out IOB41[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
42/2 seg[0] out IOB41[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
47/2 - in IOB43[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
4/3 - in IOL5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
5/3 - in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
6/3 - in IOL11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/3 - in IOL12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/3 - out IOL13[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
9/3 - in IOL13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/3 - in IOL15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
11/3 - in IOL16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/3 - in IOL21[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/3 - in IOL22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 - in IOL25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
16/3 - in IOL26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
63/1 - in IOR5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
62/1 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
61/1 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
60/1 - in IOR12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
59/1 - in IOR12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
57/1 led[2] out IOR13[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
56/1 led[3] out IOR14[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
55/1 led[4] out IOR14[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
54/1 led[5] out IOR15[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
53/1 led[6] out IOR15[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
52/1 clk in IOR17[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
51/1 led[7] out IOR17[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
50/1 - in IOR22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
49/1 - in IOR24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
48/1 - in IOR24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3