Power Messages

Report Title Power Analysis Report
Design File C:\Gowin\SV_240812_mhut_2001\leg4\impl\gwsynthesis\leg4.vg
Physical Constraints File C:\Gowin\SV_240812_mhut_2001\leg4\src\leg4.cst
Timing Constraints File C:\Gowin\SV_240812_mhut_2001\leg4\src\leg4.sdc
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Aug 12 11:38:28 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Configure Information:

Grade Commercial
Process Typical
Ambient Temperature 25.000
Use Custom Theta JA false
Heat Sink None
Air Flow LFM_0
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Related Vcd File
Related Saif File
Filter Glitches false
Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125

Power Summary

Power Information:

Total Power (mW) 27.672
Quiescent Power (mW) 27.484
Dynamic Power (mW) 0.188
Psram Power (mW) 86.000

Thermal Information:

Junction Temperature 25.560
Theta JA 21.450
Max Allowed Ambient Temperature 84.440

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.200 0.040 3.512 4.261
VCCX 3.300 0.021 5.000 16.570
VCCIO33 3.300 0.021 2.052 6.840

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 0.021 NA 2.281
IO 8.066 7.900 1.013

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
leg4sys 0.021 0.021(0.021)
leg4sys/clkdiv_1/ 0.003 0.003(0.000)
leg4sys/clkdiv_2/ 0.006 0.006(0.000)
leg4sys/clkdiv_3/ 0.005 0.005(0.000)
leg4sys/clkdiv_4/ 0.003 0.003(0.000)
leg4sys/clkdiv_5/ 0.004 0.004(0.000)
leg4sys/debounce_1/ 0.000 0.000(0.000)
leg4sys/drv7seg_1/ 0.000 0.000(0.000)
leg4sys/drv7seg_2/ 0.000 0.000(0.000)
leg4sys/drv7seg_3/ 0.000 0.000(0.000)
leg4sys/drv7seg_4/ 0.000 0.000(0.000)
leg4sys/leg4_1/ 0.000 0.000(0.000)
leg4sys/leg4_1/inst1/ 0.000 0.000(0.000)
leg4sys/leg4_1/inst2/ 0.000 0.000(0.000)
leg4sys/leg4_rom_1/ 0.000 0.000(0.000)
leg4sys/mux7seg_1/ 0.000 0.000(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
leg4_clk 0.001 0.000
clk27mhz 27.000 0.022
clk400hz 0.000 0.000
clk160hz 0.000 0.000
clk1khz 0.001 0.000
clk10hz 0.000 0.000
clk1hz 0.000 0.000