Timing Messages

Report Title Timing Analysis Report
Design File C:\Gowin\SV_240812_mhut_2001\organ\impl\gwsynthesis\organ.vg
Physical Constraints File C:\Gowin\SV_240812_mhut_2001\organ\src\organ.cst
Timing Constraint File C:\Gowin\SV_240812_mhut_2001\organ\src\organ.sdc
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Aug 12 11:43:08 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C6/I5
Hold Delay Model Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed 401
Numbers of Endpoints Analyzed 210
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk27mhz Base 37.037 27.000 0.000 18.518 clk
2 clk50hz Generated 19999980.000 0.000 0.000 9999990.000 clk clk27mhz clk50hz

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk27mhz 27.000(MHz) 110.658(MHz) 5 TOP
2 clk50hz 0.000(MHz) 166.666(MHz) 2 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk27mhz Setup 0.000 0
clk27mhz Hold 0.000 0
clk50hz Setup 0.000 0
clk50hz Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 28.000 inst5/count_2_s0/Q inst5/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 8.637
2 28.524 inst5/count_2_s0/Q inst5/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 8.113
3 28.539 inst5/count_1_s0/Q inst5/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 8.098
4 28.539 inst5/count_1_s0/Q inst5/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 8.098
5 28.561 inst5/count_1_s0/Q inst5/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 8.076
6 28.561 inst5/count_1_s0/Q inst5/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 8.076
7 28.603 clkdiv_1/count_2_s0/Q clkdiv_1/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 8.034
8 28.670 clkdiv_1/count_2_s0/Q clkdiv_1/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.967
9 28.670 clkdiv_1/count_2_s0/Q clkdiv_1/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.967
10 28.670 clkdiv_1/count_2_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.967
11 28.723 inst5/count_1_s0/Q inst5/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.914
12 28.872 clkdiv_1/count_2_s0/Q clkdiv_1/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.765
13 28.872 clkdiv_1/count_2_s0/Q clkdiv_1/count_19_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.765
14 29.000 inst5/count_1_s0/Q inst5/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.637
15 29.047 clkdiv_1/count_2_s0/Q clkdiv_1/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.590
16 29.082 clkdiv_1/count_2_s0/Q clkdiv_1/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.555
17 29.082 clkdiv_1/count_2_s0/Q clkdiv_1/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.555
18 29.150 inst5/count_1_s0/Q inst5/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.487
19 29.168 clkdiv_1/count_2_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.469
20 29.168 clkdiv_1/count_2_s0/Q clkdiv_1/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.469
21 29.168 clkdiv_1/count_2_s0/Q clkdiv_1/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.469
22 29.168 clkdiv_1/count_2_s0/Q clkdiv_1/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.469
23 29.196 inst5/count_1_s0/Q inst5/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.441
24 29.196 inst5/count_1_s0/Q inst5/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.441
25 29.253 inst5/count_1_s0/Q inst5/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.384

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.708 clkdiv_1/count_16_s0/Q clkdiv_1/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.708
2 0.708 clkdiv_1/count_17_s0/Q clkdiv_1/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.708
3 0.709 clkdiv_1/count_0_s0/Q clkdiv_1/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
4 0.709 clkdiv_1/count_4_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
5 0.709 clkdiv_1/count_18_s0/Q clkdiv_1/count_18_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
6 0.710 inst5/count_3_s0/Q inst5/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.710
7 0.710 inst5/count_12_s0/Q inst5/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.710
8 0.710 inst5/count_13_s0/Q inst5/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.710
9 0.711 inst2/index_0_s0/Q inst2/index_0_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.711
10 0.711 inst2/index_2_s0/Q inst2/index_2_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.711
11 0.711 inst5/count_7_s0/Q inst5/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.711
12 0.711 inst5/count_11_s0/Q inst5/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.711
13 0.892 clkdiv_1/count_2_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.892
14 0.892 clkdiv_1/count_14_s0/Q clkdiv_1/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.892
15 0.892 clkdiv_1/count_15_s0/Q clkdiv_1/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.892
16 0.893 clkdiv_1/count_11_s0/Q clkdiv_1/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.893
17 0.894 inst5/count_5_s0/Q inst5/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.894
18 0.894 inst5/count_9_s0/Q inst5/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.894
19 0.896 inst5/count_1_s0/Q inst5/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.896
20 0.942 inst2/tmp_1_s1/Q inst2/key_1_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.942
21 0.954 inst5/count_16_s0/Q inst5/clk_out_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.954
22 0.954 inst5/count_16_s0/Q inst5/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.954
23 0.958 inst5/count_0_s0/Q inst5/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.958
24 0.966 clkdiv_1/count_19_s0/Q clkdiv_1/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.966
25 0.973 clkdiv_1/count_19_s0/Q clkdiv_1/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.973

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 15.130 16.380 1.250 High Pulse Width clk27mhz clkdiv_1/count_19_s0
2 15.130 16.380 1.250 High Pulse Width clk27mhz clkdiv_1/count_18_s0
3 15.130 16.380 1.250 High Pulse Width clk27mhz clkdiv_1/count_16_s0
4 15.130 16.380 1.250 High Pulse Width clk27mhz clkdiv_1/count_12_s0
5 15.130 16.380 1.250 High Pulse Width clk27mhz clkdiv_1/count_4_s0
6 15.130 16.380 1.250 High Pulse Width clk27mhz inst5/count_7_s0
7 15.130 16.380 1.250 High Pulse Width clk27mhz inst5/count_8_s0
8 15.130 16.380 1.250 High Pulse Width clk27mhz clkdiv_1/count_5_s0
9 15.130 16.380 1.250 High Pulse Width clk27mhz inst5/count_9_s0
10 15.130 16.380 1.250 High Pulse Width clk27mhz inst5/count_10_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 28.000
Data Arrival Time 13.111
Data Required Time 41.111
From inst5/count_2_s0
To inst5/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[1][B] inst5/count_2_s0/CLK
4.932 0.458 tC2Q RF 5 R14C22[1][B] inst5/count_2_s0/Q
5.434 0.501 tNET FF 1 R14C20[1][B] inst5/n57_s3/I2
6.533 1.099 tINS FF 5 R14C20[1][B] inst5/n57_s3/F
7.838 1.305 tNET FF 1 R15C21[3][A] inst5/n51_s3/I2
8.937 1.099 tINS FF 7 R15C21[3][A] inst5/n51_s3/F
9.752 0.815 tNET FF 1 R16C22[3][A] inst5/n45_s4/I1
10.784 1.032 tINS FF 2 R16C22[3][A] inst5/n45_s4/F
12.079 1.294 tNET FF 1 R14C19[1][B] inst5/n45_s2/I1
13.111 1.032 tINS FF 1 R14C19[1][B] inst5/n45_s2/F
13.111 0.000 tNET FF 1 R14C19[1][B] inst5/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C19[1][B] inst5/count_16_s0/CLK
41.111 -0.400 tSu 1 R14C19[1][B] inst5/count_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 4.262, 49.347%; route: 3.916, 45.346%; tC2Q: 0.458, 5.307%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path2

Path Summary:

Slack 28.524
Data Arrival Time 12.586
Data Required Time 41.111
From inst5/count_2_s0
To inst5/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[1][B] inst5/count_2_s0/CLK
4.932 0.458 tC2Q RF 5 R14C22[1][B] inst5/count_2_s0/Q
5.434 0.501 tNET FF 1 R14C20[1][B] inst5/n57_s3/I2
6.533 1.099 tINS FF 5 R14C20[1][B] inst5/n57_s3/F
7.838 1.305 tNET FF 1 R15C21[3][A] inst5/n51_s3/I2
8.937 1.099 tINS FF 7 R15C21[3][A] inst5/n51_s3/F
9.752 0.815 tNET FF 1 R16C22[3][A] inst5/n45_s4/I1
10.784 1.032 tINS FF 2 R16C22[3][A] inst5/n45_s4/F
11.764 0.980 tNET FF 1 R14C20[0][B] inst5/n44_s2/I2
12.586 0.822 tINS FF 1 R14C20[0][B] inst5/n44_s2/F
12.586 0.000 tNET FF 1 R14C20[0][B] inst5/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C20[0][B] inst5/count_17_s0/CLK
41.111 -0.400 tSu 1 R14C20[0][B] inst5/count_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 4.052, 49.948%; route: 3.602, 44.403%; tC2Q: 0.458, 5.650%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path3

Path Summary:

Slack 28.539
Data Arrival Time 12.572
Data Required Time 41.111
From inst5/count_1_s0
To inst5/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
4.932 0.458 tC2Q RF 6 R14C22[2][A] inst5/count_1_s0/Q
6.240 1.308 tNET FF 2 R15C20[1][A] inst5/n7_s62/I0
7.198 0.958 tINS FF 1 R15C20[1][A] inst5/n7_s62/COUT
7.198 0.000 tNET FF 2 R15C20[1][B] inst5/n7_s63/CIN
7.255 0.057 tINS FF 1 R15C20[1][B] inst5/n7_s63/COUT
7.255 0.000 tNET FF 2 R15C20[2][A] inst5/n7_s64/CIN
7.312 0.057 tINS FF 1 R15C20[2][A] inst5/n7_s64/COUT
7.312 0.000 tNET FF 2 R15C20[2][B] inst5/n7_s65/CIN
7.369 0.057 tINS FF 1 R15C20[2][B] inst5/n7_s65/COUT
7.369 0.000 tNET FF 2 R15C21[0][A] inst5/n7_s66/CIN
7.426 0.057 tINS FF 1 R15C21[0][A] inst5/n7_s66/COUT
7.426 0.000 tNET FF 2 R15C21[0][B] inst5/n7_s67/CIN
7.483 0.057 tINS FF 1 R15C21[0][B] inst5/n7_s67/COUT
7.483 0.000 tNET FF 2 R15C21[1][A] inst5/n7_s68/CIN
7.540 0.057 tINS FF 1 R15C21[1][A] inst5/n7_s68/COUT
7.540 0.000 tNET FF 2 R15C21[1][B] inst5/n7_s69/CIN
7.597 0.057 tINS FF 1 R15C21[1][B] inst5/n7_s69/COUT
7.597 0.000 tNET FF 2 R15C21[2][A] inst5/n7_s70/CIN
7.654 0.057 tINS FF 1 R15C21[2][A] inst5/n7_s70/COUT
7.654 0.000 tNET FF 2 R15C21[2][B] inst5/n7_s71/CIN
7.711 0.057 tINS FF 1 R15C21[2][B] inst5/n7_s71/COUT
7.711 0.000 tNET FF 2 R15C22[0][A] inst5/n7_s72/CIN
7.768 0.057 tINS FF 1 R15C22[0][A] inst5/n7_s72/COUT
7.768 0.000 tNET FF 2 R15C22[0][B] inst5/n7_s73/CIN
7.825 0.057 tINS FF 1 R15C22[0][B] inst5/n7_s73/COUT
7.825 0.000 tNET FF 2 R15C22[1][A] inst5/n7_s74/CIN
7.882 0.057 tINS FF 1 R15C22[1][A] inst5/n7_s74/COUT
7.882 0.000 tNET FF 2 R15C22[1][B] inst5/n7_s75/CIN
7.939 0.057 tINS FF 1 R15C22[1][B] inst5/n7_s75/COUT
7.939 0.000 tNET FF 2 R15C22[2][A] inst5/n7_s76/CIN
7.996 0.057 tINS FF 1 R15C22[2][A] inst5/n7_s76/COUT
9.363 1.367 tNET FF 1 R14C20[2][B] inst5/n61_s6/I2
10.395 1.032 tINS FF 18 R14C20[2][B] inst5/n61_s6/F
11.750 1.354 tNET FF 1 R16C23[0][B] inst5/n47_s2/I3
12.572 0.822 tINS FF 1 R16C23[0][B] inst5/n47_s2/F
12.572 0.000 tNET FF 1 R16C23[0][B] inst5/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R16C23[0][B] inst5/count_14_s0/CLK
41.111 -0.400 tSu 1 R16C23[0][B] inst5/count_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.610, 44.578%; route: 4.030, 49.762%; tC2Q: 0.458, 5.660%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path4

Path Summary:

Slack 28.539
Data Arrival Time 12.572
Data Required Time 41.111
From inst5/count_1_s0
To inst5/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
4.932 0.458 tC2Q RF 6 R14C22[2][A] inst5/count_1_s0/Q
6.240 1.308 tNET FF 2 R15C20[1][A] inst5/n7_s62/I0
7.198 0.958 tINS FF 1 R15C20[1][A] inst5/n7_s62/COUT
7.198 0.000 tNET FF 2 R15C20[1][B] inst5/n7_s63/CIN
7.255 0.057 tINS FF 1 R15C20[1][B] inst5/n7_s63/COUT
7.255 0.000 tNET FF 2 R15C20[2][A] inst5/n7_s64/CIN
7.312 0.057 tINS FF 1 R15C20[2][A] inst5/n7_s64/COUT
7.312 0.000 tNET FF 2 R15C20[2][B] inst5/n7_s65/CIN
7.369 0.057 tINS FF 1 R15C20[2][B] inst5/n7_s65/COUT
7.369 0.000 tNET FF 2 R15C21[0][A] inst5/n7_s66/CIN
7.426 0.057 tINS FF 1 R15C21[0][A] inst5/n7_s66/COUT
7.426 0.000 tNET FF 2 R15C21[0][B] inst5/n7_s67/CIN
7.483 0.057 tINS FF 1 R15C21[0][B] inst5/n7_s67/COUT
7.483 0.000 tNET FF 2 R15C21[1][A] inst5/n7_s68/CIN
7.540 0.057 tINS FF 1 R15C21[1][A] inst5/n7_s68/COUT
7.540 0.000 tNET FF 2 R15C21[1][B] inst5/n7_s69/CIN
7.597 0.057 tINS FF 1 R15C21[1][B] inst5/n7_s69/COUT
7.597 0.000 tNET FF 2 R15C21[2][A] inst5/n7_s70/CIN
7.654 0.057 tINS FF 1 R15C21[2][A] inst5/n7_s70/COUT
7.654 0.000 tNET FF 2 R15C21[2][B] inst5/n7_s71/CIN
7.711 0.057 tINS FF 1 R15C21[2][B] inst5/n7_s71/COUT
7.711 0.000 tNET FF 2 R15C22[0][A] inst5/n7_s72/CIN
7.768 0.057 tINS FF 1 R15C22[0][A] inst5/n7_s72/COUT
7.768 0.000 tNET FF 2 R15C22[0][B] inst5/n7_s73/CIN
7.825 0.057 tINS FF 1 R15C22[0][B] inst5/n7_s73/COUT
7.825 0.000 tNET FF 2 R15C22[1][A] inst5/n7_s74/CIN
7.882 0.057 tINS FF 1 R15C22[1][A] inst5/n7_s74/COUT
7.882 0.000 tNET FF 2 R15C22[1][B] inst5/n7_s75/CIN
7.939 0.057 tINS FF 1 R15C22[1][B] inst5/n7_s75/COUT
7.939 0.000 tNET FF 2 R15C22[2][A] inst5/n7_s76/CIN
7.996 0.057 tINS FF 1 R15C22[2][A] inst5/n7_s76/COUT
9.363 1.367 tNET FF 1 R14C20[2][B] inst5/n61_s6/I2
10.395 1.032 tINS FF 18 R14C20[2][B] inst5/n61_s6/F
11.750 1.354 tNET FF 1 R16C23[0][A] inst5/n46_s2/I3
12.572 0.822 tINS FF 1 R16C23[0][A] inst5/n46_s2/F
12.572 0.000 tNET FF 1 R16C23[0][A] inst5/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R16C23[0][A] inst5/count_15_s0/CLK
41.111 -0.400 tSu 1 R16C23[0][A] inst5/count_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.610, 44.578%; route: 4.030, 49.762%; tC2Q: 0.458, 5.660%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path5

Path Summary:

Slack 28.561
Data Arrival Time 12.549
Data Required Time 41.111
From inst5/count_1_s0
To inst5/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
4.932 0.458 tC2Q RF 6 R14C22[2][A] inst5/count_1_s0/Q
6.240 1.308 tNET FF 2 R15C20[1][A] inst5/n7_s62/I0
7.198 0.958 tINS FF 1 R15C20[1][A] inst5/n7_s62/COUT
7.198 0.000 tNET FF 2 R15C20[1][B] inst5/n7_s63/CIN
7.255 0.057 tINS FF 1 R15C20[1][B] inst5/n7_s63/COUT
7.255 0.000 tNET FF 2 R15C20[2][A] inst5/n7_s64/CIN
7.312 0.057 tINS FF 1 R15C20[2][A] inst5/n7_s64/COUT
7.312 0.000 tNET FF 2 R15C20[2][B] inst5/n7_s65/CIN
7.369 0.057 tINS FF 1 R15C20[2][B] inst5/n7_s65/COUT
7.369 0.000 tNET FF 2 R15C21[0][A] inst5/n7_s66/CIN
7.426 0.057 tINS FF 1 R15C21[0][A] inst5/n7_s66/COUT
7.426 0.000 tNET FF 2 R15C21[0][B] inst5/n7_s67/CIN
7.483 0.057 tINS FF 1 R15C21[0][B] inst5/n7_s67/COUT
7.483 0.000 tNET FF 2 R15C21[1][A] inst5/n7_s68/CIN
7.540 0.057 tINS FF 1 R15C21[1][A] inst5/n7_s68/COUT
7.540 0.000 tNET FF 2 R15C21[1][B] inst5/n7_s69/CIN
7.597 0.057 tINS FF 1 R15C21[1][B] inst5/n7_s69/COUT
7.597 0.000 tNET FF 2 R15C21[2][A] inst5/n7_s70/CIN
7.654 0.057 tINS FF 1 R15C21[2][A] inst5/n7_s70/COUT
7.654 0.000 tNET FF 2 R15C21[2][B] inst5/n7_s71/CIN
7.711 0.057 tINS FF 1 R15C21[2][B] inst5/n7_s71/COUT
7.711 0.000 tNET FF 2 R15C22[0][A] inst5/n7_s72/CIN
7.768 0.057 tINS FF 1 R15C22[0][A] inst5/n7_s72/COUT
7.768 0.000 tNET FF 2 R15C22[0][B] inst5/n7_s73/CIN
7.825 0.057 tINS FF 1 R15C22[0][B] inst5/n7_s73/COUT
7.825 0.000 tNET FF 2 R15C22[1][A] inst5/n7_s74/CIN
7.882 0.057 tINS FF 1 R15C22[1][A] inst5/n7_s74/COUT
7.882 0.000 tNET FF 2 R15C22[1][B] inst5/n7_s75/CIN
7.939 0.057 tINS FF 1 R15C22[1][B] inst5/n7_s75/COUT
7.939 0.000 tNET FF 2 R15C22[2][A] inst5/n7_s76/CIN
7.996 0.057 tINS FF 1 R15C22[2][A] inst5/n7_s76/COUT
9.363 1.367 tNET FF 1 R14C20[2][B] inst5/n61_s6/I2
10.395 1.032 tINS FF 18 R14C20[2][B] inst5/n61_s6/F
11.727 1.332 tNET FF 1 R15C23[0][B] inst5/n55_s2/I2
12.549 0.822 tINS FF 1 R15C23[0][B] inst5/n55_s2/F
12.549 0.000 tNET FF 1 R15C23[0][B] inst5/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R15C23[0][B] inst5/count_6_s0/CLK
41.111 -0.400 tSu 1 R15C23[0][B] inst5/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.610, 44.703%; route: 4.007, 49.622%; tC2Q: 0.458, 5.676%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path6

Path Summary:

Slack 28.561
Data Arrival Time 12.549
Data Required Time 41.111
From inst5/count_1_s0
To inst5/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
4.932 0.458 tC2Q RF 6 R14C22[2][A] inst5/count_1_s0/Q
6.240 1.308 tNET FF 2 R15C20[1][A] inst5/n7_s62/I0
7.198 0.958 tINS FF 1 R15C20[1][A] inst5/n7_s62/COUT
7.198 0.000 tNET FF 2 R15C20[1][B] inst5/n7_s63/CIN
7.255 0.057 tINS FF 1 R15C20[1][B] inst5/n7_s63/COUT
7.255 0.000 tNET FF 2 R15C20[2][A] inst5/n7_s64/CIN
7.312 0.057 tINS FF 1 R15C20[2][A] inst5/n7_s64/COUT
7.312 0.000 tNET FF 2 R15C20[2][B] inst5/n7_s65/CIN
7.369 0.057 tINS FF 1 R15C20[2][B] inst5/n7_s65/COUT
7.369 0.000 tNET FF 2 R15C21[0][A] inst5/n7_s66/CIN
7.426 0.057 tINS FF 1 R15C21[0][A] inst5/n7_s66/COUT
7.426 0.000 tNET FF 2 R15C21[0][B] inst5/n7_s67/CIN
7.483 0.057 tINS FF 1 R15C21[0][B] inst5/n7_s67/COUT
7.483 0.000 tNET FF 2 R15C21[1][A] inst5/n7_s68/CIN
7.540 0.057 tINS FF 1 R15C21[1][A] inst5/n7_s68/COUT
7.540 0.000 tNET FF 2 R15C21[1][B] inst5/n7_s69/CIN
7.597 0.057 tINS FF 1 R15C21[1][B] inst5/n7_s69/COUT
7.597 0.000 tNET FF 2 R15C21[2][A] inst5/n7_s70/CIN
7.654 0.057 tINS FF 1 R15C21[2][A] inst5/n7_s70/COUT
7.654 0.000 tNET FF 2 R15C21[2][B] inst5/n7_s71/CIN
7.711 0.057 tINS FF 1 R15C21[2][B] inst5/n7_s71/COUT
7.711 0.000 tNET FF 2 R15C22[0][A] inst5/n7_s72/CIN
7.768 0.057 tINS FF 1 R15C22[0][A] inst5/n7_s72/COUT
7.768 0.000 tNET FF 2 R15C22[0][B] inst5/n7_s73/CIN
7.825 0.057 tINS FF 1 R15C22[0][B] inst5/n7_s73/COUT
7.825 0.000 tNET FF 2 R15C22[1][A] inst5/n7_s74/CIN
7.882 0.057 tINS FF 1 R15C22[1][A] inst5/n7_s74/COUT
7.882 0.000 tNET FF 2 R15C22[1][B] inst5/n7_s75/CIN
7.939 0.057 tINS FF 1 R15C22[1][B] inst5/n7_s75/COUT
7.939 0.000 tNET FF 2 R15C22[2][A] inst5/n7_s76/CIN
7.996 0.057 tINS FF 1 R15C22[2][A] inst5/n7_s76/COUT
9.363 1.367 tNET FF 1 R14C20[2][B] inst5/n61_s6/I2
10.395 1.032 tINS FF 18 R14C20[2][B] inst5/n61_s6/F
11.727 1.332 tNET FF 1 R15C23[0][A] inst5/n54_s2/I2
12.549 0.822 tINS FF 1 R15C23[0][A] inst5/n54_s2/F
12.549 0.000 tNET FF 1 R15C23[0][A] inst5/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R15C23[0][A] inst5/count_7_s0/CLK
41.111 -0.400 tSu 1 R15C23[0][A] inst5/count_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.610, 44.703%; route: 4.007, 49.622%; tC2Q: 0.458, 5.676%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path7

Path Summary:

Slack 28.603
Data Arrival Time 12.508
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
11.409 1.033 tNET FF 1 R16C34[2][A] clkdiv_1/n50_s5/I1
12.508 1.099 tINS FF 1 R16C34[2][A] clkdiv_1/n50_s5/F
12.508 0.000 tNET FF 1 R16C34[2][A] clkdiv_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R16C34[2][A] clkdiv_1/count_11_s0/CLK
41.111 -0.400 tSu 1 R16C34[2][A] clkdiv_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.579, 44.546%; route: 3.997, 49.750%; tC2Q: 0.458, 5.705%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path8

Path Summary:

Slack 28.670
Data Arrival Time 12.441
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
11.409 1.033 tNET FF 1 R16C34[0][A] clkdiv_1/n61_s10/I0
12.441 1.032 tINS FF 1 R16C34[0][A] clkdiv_1/n61_s10/F
12.441 0.000 tNET FF 1 R16C34[0][A] clkdiv_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R16C34[0][A] clkdiv_1/count_0_s0/CLK
41.111 -0.400 tSu 1 R16C34[0][A] clkdiv_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.512, 44.079%; route: 3.997, 50.168%; tC2Q: 0.458, 5.753%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path9

Path Summary:

Slack 28.670
Data Arrival Time 12.441
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
11.409 1.033 tNET FF 1 R16C34[0][B] clkdiv_1/n60_s3/I1
12.441 1.032 tINS FF 1 R16C34[0][B] clkdiv_1/n60_s3/F
12.441 0.000 tNET FF 1 R16C34[0][B] clkdiv_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R16C34[0][B] clkdiv_1/count_1_s0/CLK
41.111 -0.400 tSu 1 R16C34[0][B] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.512, 44.079%; route: 3.997, 50.168%; tC2Q: 0.458, 5.753%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path10

Path Summary:

Slack 28.670
Data Arrival Time 12.441
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
11.409 1.033 tNET FF 1 R16C34[1][A] clkdiv_1/n57_s4/I1
12.441 1.032 tINS FF 1 R16C34[1][A] clkdiv_1/n57_s4/F
12.441 0.000 tNET FF 1 R16C34[1][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R16C34[1][A] clkdiv_1/count_4_s0/CLK
41.111 -0.400 tSu 1 R16C34[1][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.512, 44.079%; route: 3.997, 50.168%; tC2Q: 0.458, 5.753%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path11

Path Summary:

Slack 28.723
Data Arrival Time 12.388
Data Required Time 41.111
From inst5/count_1_s0
To inst5/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
4.932 0.458 tC2Q RF 6 R14C22[2][A] inst5/count_1_s0/Q
6.240 1.308 tNET FF 2 R15C20[1][A] inst5/n7_s62/I0
7.198 0.958 tINS FF 1 R15C20[1][A] inst5/n7_s62/COUT
7.198 0.000 tNET FF 2 R15C20[1][B] inst5/n7_s63/CIN
7.255 0.057 tINS FF 1 R15C20[1][B] inst5/n7_s63/COUT
7.255 0.000 tNET FF 2 R15C20[2][A] inst5/n7_s64/CIN
7.312 0.057 tINS FF 1 R15C20[2][A] inst5/n7_s64/COUT
7.312 0.000 tNET FF 2 R15C20[2][B] inst5/n7_s65/CIN
7.369 0.057 tINS FF 1 R15C20[2][B] inst5/n7_s65/COUT
7.369 0.000 tNET FF 2 R15C21[0][A] inst5/n7_s66/CIN
7.426 0.057 tINS FF 1 R15C21[0][A] inst5/n7_s66/COUT
7.426 0.000 tNET FF 2 R15C21[0][B] inst5/n7_s67/CIN
7.483 0.057 tINS FF 1 R15C21[0][B] inst5/n7_s67/COUT
7.483 0.000 tNET FF 2 R15C21[1][A] inst5/n7_s68/CIN
7.540 0.057 tINS FF 1 R15C21[1][A] inst5/n7_s68/COUT
7.540 0.000 tNET FF 2 R15C21[1][B] inst5/n7_s69/CIN
7.597 0.057 tINS FF 1 R15C21[1][B] inst5/n7_s69/COUT
7.597 0.000 tNET FF 2 R15C21[2][A] inst5/n7_s70/CIN
7.654 0.057 tINS FF 1 R15C21[2][A] inst5/n7_s70/COUT
7.654 0.000 tNET FF 2 R15C21[2][B] inst5/n7_s71/CIN
7.711 0.057 tINS FF 1 R15C21[2][B] inst5/n7_s71/COUT
7.711 0.000 tNET FF 2 R15C22[0][A] inst5/n7_s72/CIN
7.768 0.057 tINS FF 1 R15C22[0][A] inst5/n7_s72/COUT
7.768 0.000 tNET FF 2 R15C22[0][B] inst5/n7_s73/CIN
7.825 0.057 tINS FF 1 R15C22[0][B] inst5/n7_s73/COUT
7.825 0.000 tNET FF 2 R15C22[1][A] inst5/n7_s74/CIN
7.882 0.057 tINS FF 1 R15C22[1][A] inst5/n7_s74/COUT
7.882 0.000 tNET FF 2 R15C22[1][B] inst5/n7_s75/CIN
7.939 0.057 tINS FF 1 R15C22[1][B] inst5/n7_s75/COUT
7.939 0.000 tNET FF 2 R15C22[2][A] inst5/n7_s76/CIN
7.996 0.057 tINS FF 1 R15C22[2][A] inst5/n7_s76/COUT
9.363 1.367 tNET FF 1 R14C20[2][B] inst5/n61_s6/I2
10.395 1.032 tINS FF 18 R14C20[2][B] inst5/n61_s6/F
11.289 0.893 tNET FF 1 R14C22[1][A] inst5/n58_s2/I2
12.388 1.099 tINS FF 1 R14C22[1][A] inst5/n58_s2/F
12.388 0.000 tNET FF 1 R14C22[1][A] inst5/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C22[1][A] inst5/count_3_s0/CLK
41.111 -0.400 tSu 1 R14C22[1][A] inst5/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.887, 49.116%; route: 3.569, 45.093%; tC2Q: 0.458, 5.791%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path12

Path Summary:

Slack 28.872
Data Arrival Time 12.239
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
11.207 0.831 tNET FF 1 R15C34[2][B] clkdiv_1/n49_s4/I0
12.239 1.032 tINS FF 1 R15C34[2][B] clkdiv_1/n49_s4/F
12.239 0.000 tNET FF 1 R15C34[2][B] clkdiv_1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R15C34[2][B] clkdiv_1/count_12_s0/CLK
41.111 -0.400 tSu 1 R15C34[2][B] clkdiv_1/count_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.512, 45.227%; route: 3.795, 48.871%; tC2Q: 0.458, 5.902%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path13

Path Summary:

Slack 28.872
Data Arrival Time 12.239
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_19_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
11.207 0.831 tNET FF 1 R15C34[0][B] clkdiv_1/n42_s3/I2
12.239 1.032 tINS FF 1 R15C34[0][B] clkdiv_1/n42_s3/F
12.239 0.000 tNET FF 1 R15C34[0][B] clkdiv_1/count_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R15C34[0][B] clkdiv_1/count_19_s0/CLK
41.111 -0.400 tSu 1 R15C34[0][B] clkdiv_1/count_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.512, 45.227%; route: 3.795, 48.871%; tC2Q: 0.458, 5.902%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path14

Path Summary:

Slack 29.000
Data Arrival Time 12.111
Data Required Time 41.111
From inst5/count_1_s0
To inst5/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
4.932 0.458 tC2Q RF 6 R14C22[2][A] inst5/count_1_s0/Q
6.240 1.308 tNET FF 2 R15C20[1][A] inst5/n7_s62/I0
7.198 0.958 tINS FF 1 R15C20[1][A] inst5/n7_s62/COUT
7.198 0.000 tNET FF 2 R15C20[1][B] inst5/n7_s63/CIN
7.255 0.057 tINS FF 1 R15C20[1][B] inst5/n7_s63/COUT
7.255 0.000 tNET FF 2 R15C20[2][A] inst5/n7_s64/CIN
7.312 0.057 tINS FF 1 R15C20[2][A] inst5/n7_s64/COUT
7.312 0.000 tNET FF 2 R15C20[2][B] inst5/n7_s65/CIN
7.369 0.057 tINS FF 1 R15C20[2][B] inst5/n7_s65/COUT
7.369 0.000 tNET FF 2 R15C21[0][A] inst5/n7_s66/CIN
7.426 0.057 tINS FF 1 R15C21[0][A] inst5/n7_s66/COUT
7.426 0.000 tNET FF 2 R15C21[0][B] inst5/n7_s67/CIN
7.483 0.057 tINS FF 1 R15C21[0][B] inst5/n7_s67/COUT
7.483 0.000 tNET FF 2 R15C21[1][A] inst5/n7_s68/CIN
7.540 0.057 tINS FF 1 R15C21[1][A] inst5/n7_s68/COUT
7.540 0.000 tNET FF 2 R15C21[1][B] inst5/n7_s69/CIN
7.597 0.057 tINS FF 1 R15C21[1][B] inst5/n7_s69/COUT
7.597 0.000 tNET FF 2 R15C21[2][A] inst5/n7_s70/CIN
7.654 0.057 tINS FF 1 R15C21[2][A] inst5/n7_s70/COUT
7.654 0.000 tNET FF 2 R15C21[2][B] inst5/n7_s71/CIN
7.711 0.057 tINS FF 1 R15C21[2][B] inst5/n7_s71/COUT
7.711 0.000 tNET FF 2 R15C22[0][A] inst5/n7_s72/CIN
7.768 0.057 tINS FF 1 R15C22[0][A] inst5/n7_s72/COUT
7.768 0.000 tNET FF 2 R15C22[0][B] inst5/n7_s73/CIN
7.825 0.057 tINS FF 1 R15C22[0][B] inst5/n7_s73/COUT
7.825 0.000 tNET FF 2 R15C22[1][A] inst5/n7_s74/CIN
7.882 0.057 tINS FF 1 R15C22[1][A] inst5/n7_s74/COUT
7.882 0.000 tNET FF 2 R15C22[1][B] inst5/n7_s75/CIN
7.939 0.057 tINS FF 1 R15C22[1][B] inst5/n7_s75/COUT
7.939 0.000 tNET FF 2 R15C22[2][A] inst5/n7_s76/CIN
7.996 0.057 tINS FF 1 R15C22[2][A] inst5/n7_s76/COUT
9.363 1.367 tNET FF 1 R14C20[2][B] inst5/n61_s6/I2
10.395 1.032 tINS FF 18 R14C20[2][B] inst5/n61_s6/F
11.289 0.893 tNET FF 1 R14C22[0][B] inst5/n57_s2/I2
12.111 0.822 tINS FF 1 R14C22[0][B] inst5/n57_s2/F
12.111 0.000 tNET FF 1 R14C22[0][B] inst5/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C22[0][B] inst5/count_4_s0/CLK
41.111 -0.400 tSu 1 R14C22[0][B] inst5/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.610, 47.270%; route: 3.569, 46.728%; tC2Q: 0.458, 6.002%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path15

Path Summary:

Slack 29.047
Data Arrival Time 12.064
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
11.242 0.866 tNET FF 1 R14C34[1][B] clkdiv_1/n56_s4/I1
12.064 0.822 tINS FF 1 R14C34[1][B] clkdiv_1/n56_s4/F
12.064 0.000 tNET FF 1 R14C34[1][B] clkdiv_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C34[1][B] clkdiv_1/count_5_s0/CLK
41.111 -0.400 tSu 1 R14C34[1][B] clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.302, 43.504%; route: 3.830, 50.457%; tC2Q: 0.458, 6.039%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path16

Path Summary:

Slack 29.082
Data Arrival Time 12.029
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
11.207 0.831 tNET FF 1 R16C33[1][A] clkdiv_1/n58_s5/I0
12.029 0.822 tINS FF 1 R16C33[1][A] clkdiv_1/n58_s5/F
12.029 0.000 tNET FF 1 R16C33[1][A] clkdiv_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R16C33[1][A] clkdiv_1/count_3_s0/CLK
41.111 -0.400 tSu 1 R16C33[1][A] clkdiv_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.302, 43.704%; route: 3.795, 50.229%; tC2Q: 0.458, 6.066%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path17

Path Summary:

Slack 29.082
Data Arrival Time 12.029
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
11.207 0.831 tNET FF 1 R16C33[1][B] clkdiv_1/n55_s6/I1
12.029 0.822 tINS FF 1 R16C33[1][B] clkdiv_1/n55_s6/F
12.029 0.000 tNET FF 1 R16C33[1][B] clkdiv_1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R16C33[1][B] clkdiv_1/count_6_s0/CLK
41.111 -0.400 tSu 1 R16C33[1][B] clkdiv_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.302, 43.704%; route: 3.795, 50.229%; tC2Q: 0.458, 6.066%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path18

Path Summary:

Slack 29.150
Data Arrival Time 11.960
Data Required Time 41.111
From inst5/count_1_s0
To inst5/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
4.932 0.458 tC2Q RF 6 R14C22[2][A] inst5/count_1_s0/Q
6.240 1.308 tNET FF 2 R15C20[1][A] inst5/n7_s62/I0
7.198 0.958 tINS FF 1 R15C20[1][A] inst5/n7_s62/COUT
7.198 0.000 tNET FF 2 R15C20[1][B] inst5/n7_s63/CIN
7.255 0.057 tINS FF 1 R15C20[1][B] inst5/n7_s63/COUT
7.255 0.000 tNET FF 2 R15C20[2][A] inst5/n7_s64/CIN
7.312 0.057 tINS FF 1 R15C20[2][A] inst5/n7_s64/COUT
7.312 0.000 tNET FF 2 R15C20[2][B] inst5/n7_s65/CIN
7.369 0.057 tINS FF 1 R15C20[2][B] inst5/n7_s65/COUT
7.369 0.000 tNET FF 2 R15C21[0][A] inst5/n7_s66/CIN
7.426 0.057 tINS FF 1 R15C21[0][A] inst5/n7_s66/COUT
7.426 0.000 tNET FF 2 R15C21[0][B] inst5/n7_s67/CIN
7.483 0.057 tINS FF 1 R15C21[0][B] inst5/n7_s67/COUT
7.483 0.000 tNET FF 2 R15C21[1][A] inst5/n7_s68/CIN
7.540 0.057 tINS FF 1 R15C21[1][A] inst5/n7_s68/COUT
7.540 0.000 tNET FF 2 R15C21[1][B] inst5/n7_s69/CIN
7.597 0.057 tINS FF 1 R15C21[1][B] inst5/n7_s69/COUT
7.597 0.000 tNET FF 2 R15C21[2][A] inst5/n7_s70/CIN
7.654 0.057 tINS FF 1 R15C21[2][A] inst5/n7_s70/COUT
7.654 0.000 tNET FF 2 R15C21[2][B] inst5/n7_s71/CIN
7.711 0.057 tINS FF 1 R15C21[2][B] inst5/n7_s71/COUT
7.711 0.000 tNET FF 2 R15C22[0][A] inst5/n7_s72/CIN
7.768 0.057 tINS FF 1 R15C22[0][A] inst5/n7_s72/COUT
7.768 0.000 tNET FF 2 R15C22[0][B] inst5/n7_s73/CIN
7.825 0.057 tINS FF 1 R15C22[0][B] inst5/n7_s73/COUT
7.825 0.000 tNET FF 2 R15C22[1][A] inst5/n7_s74/CIN
7.882 0.057 tINS FF 1 R15C22[1][A] inst5/n7_s74/COUT
7.882 0.000 tNET FF 2 R15C22[1][B] inst5/n7_s75/CIN
7.939 0.057 tINS FF 1 R15C22[1][B] inst5/n7_s75/COUT
7.939 0.000 tNET FF 2 R15C22[2][A] inst5/n7_s76/CIN
7.996 0.057 tINS FF 1 R15C22[2][A] inst5/n7_s76/COUT
9.363 1.367 tNET FF 1 R14C20[2][B] inst5/n61_s6/I2
10.395 1.032 tINS FF 18 R14C20[2][B] inst5/n61_s6/F
10.928 0.533 tNET FF 1 R14C22[1][B] inst5/n59_s2/I3
11.960 1.032 tINS FF 1 R14C22[1][B] inst5/n59_s2/F
11.960 0.000 tNET FF 1 R14C22[1][B] inst5/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C22[1][B] inst5/count_2_s0/CLK
41.111 -0.400 tSu 1 R14C22[1][B] inst5/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.820, 51.024%; route: 3.208, 42.854%; tC2Q: 0.458, 6.122%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path19

Path Summary:

Slack 29.168
Data Arrival Time 11.943
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
10.911 0.535 tNET FF 1 R14C34[2][A] clkdiv_1/n59_s4/I1
11.943 1.032 tINS FF 1 R14C34[2][A] clkdiv_1/n59_s4/F
11.943 0.000 tNET FF 1 R14C34[2][A] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
41.111 -0.400 tSu 1 R14C34[2][A] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.512, 47.020%; route: 3.499, 46.844%; tC2Q: 0.458, 6.136%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path20

Path Summary:

Slack 29.168
Data Arrival Time 11.943
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
10.911 0.535 tNET FF 1 R14C34[1][A] clkdiv_1/n54_s4/I0
11.943 1.032 tINS FF 1 R14C34[1][A] clkdiv_1/n54_s4/F
11.943 0.000 tNET FF 1 R14C34[1][A] clkdiv_1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C34[1][A] clkdiv_1/count_7_s0/CLK
41.111 -0.400 tSu 1 R14C34[1][A] clkdiv_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.512, 47.020%; route: 3.499, 46.844%; tC2Q: 0.458, 6.136%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path21

Path Summary:

Slack 29.168
Data Arrival Time 11.943
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
10.911 0.535 tNET FF 1 R14C34[0][B] clkdiv_1/n52_s4/I1
11.943 1.032 tINS FF 1 R14C34[0][B] clkdiv_1/n52_s4/F
11.943 0.000 tNET FF 1 R14C34[0][B] clkdiv_1/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C34[0][B] clkdiv_1/count_9_s0/CLK
41.111 -0.400 tSu 1 R14C34[0][B] clkdiv_1/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.512, 47.020%; route: 3.499, 46.844%; tC2Q: 0.458, 6.136%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path22

Path Summary:

Slack 29.168
Data Arrival Time 11.943
Data Required Time 41.111
From clkdiv_1/count_2_s0
To clkdiv_1/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
4.932 0.458 tC2Q RF 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
6.250 1.318 tNET FF 1 R16C33[0][B] clkdiv_1/n57_s3/I2
6.876 0.626 tINS FF 6 R16C33[0][B] clkdiv_1/n57_s3/F
7.701 0.825 tNET FF 1 R14C34[3][A] clkdiv_1/n61_s5/I0
8.523 0.822 tINS FF 1 R14C34[3][A] clkdiv_1/n61_s5/F
9.344 0.821 tNET FF 1 R14C32[3][B] clkdiv_1/n61_s3/I1
10.376 1.032 tINS FF 15 R14C32[3][B] clkdiv_1/n61_s3/F
10.911 0.535 tNET FF 1 R14C34[0][A] clkdiv_1/n51_s4/I0
11.943 1.032 tINS FF 1 R14C34[0][A] clkdiv_1/n51_s4/F
11.943 0.000 tNET FF 1 R14C34[0][A] clkdiv_1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C34[0][A] clkdiv_1/count_10_s0/CLK
41.111 -0.400 tSu 1 R14C34[0][A] clkdiv_1/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.512, 47.020%; route: 3.499, 46.844%; tC2Q: 0.458, 6.136%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path23

Path Summary:

Slack 29.196
Data Arrival Time 11.915
Data Required Time 41.111
From inst5/count_1_s0
To inst5/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
4.932 0.458 tC2Q RF 6 R14C22[2][A] inst5/count_1_s0/Q
6.240 1.308 tNET FF 2 R15C20[1][A] inst5/n7_s62/I0
7.198 0.958 tINS FF 1 R15C20[1][A] inst5/n7_s62/COUT
7.198 0.000 tNET FF 2 R15C20[1][B] inst5/n7_s63/CIN
7.255 0.057 tINS FF 1 R15C20[1][B] inst5/n7_s63/COUT
7.255 0.000 tNET FF 2 R15C20[2][A] inst5/n7_s64/CIN
7.312 0.057 tINS FF 1 R15C20[2][A] inst5/n7_s64/COUT
7.312 0.000 tNET FF 2 R15C20[2][B] inst5/n7_s65/CIN
7.369 0.057 tINS FF 1 R15C20[2][B] inst5/n7_s65/COUT
7.369 0.000 tNET FF 2 R15C21[0][A] inst5/n7_s66/CIN
7.426 0.057 tINS FF 1 R15C21[0][A] inst5/n7_s66/COUT
7.426 0.000 tNET FF 2 R15C21[0][B] inst5/n7_s67/CIN
7.483 0.057 tINS FF 1 R15C21[0][B] inst5/n7_s67/COUT
7.483 0.000 tNET FF 2 R15C21[1][A] inst5/n7_s68/CIN
7.540 0.057 tINS FF 1 R15C21[1][A] inst5/n7_s68/COUT
7.540 0.000 tNET FF 2 R15C21[1][B] inst5/n7_s69/CIN
7.597 0.057 tINS FF 1 R15C21[1][B] inst5/n7_s69/COUT
7.597 0.000 tNET FF 2 R15C21[2][A] inst5/n7_s70/CIN
7.654 0.057 tINS FF 1 R15C21[2][A] inst5/n7_s70/COUT
7.654 0.000 tNET FF 2 R15C21[2][B] inst5/n7_s71/CIN
7.711 0.057 tINS FF 1 R15C21[2][B] inst5/n7_s71/COUT
7.711 0.000 tNET FF 2 R15C22[0][A] inst5/n7_s72/CIN
7.768 0.057 tINS FF 1 R15C22[0][A] inst5/n7_s72/COUT
7.768 0.000 tNET FF 2 R15C22[0][B] inst5/n7_s73/CIN
7.825 0.057 tINS FF 1 R15C22[0][B] inst5/n7_s73/COUT
7.825 0.000 tNET FF 2 R15C22[1][A] inst5/n7_s74/CIN
7.882 0.057 tINS FF 1 R15C22[1][A] inst5/n7_s74/COUT
7.882 0.000 tNET FF 2 R15C22[1][B] inst5/n7_s75/CIN
7.939 0.057 tINS FF 1 R15C22[1][B] inst5/n7_s75/COUT
7.939 0.000 tNET FF 2 R15C22[2][A] inst5/n7_s76/CIN
7.996 0.057 tINS FF 1 R15C22[2][A] inst5/n7_s76/COUT
9.363 1.367 tNET FF 1 R14C20[2][B] inst5/n61_s6/I2
10.395 1.032 tINS FF 18 R14C20[2][B] inst5/n61_s6/F
11.289 0.893 tNET FF 1 R14C22[2][B] inst5/n61_s2/I1
11.915 0.626 tINS FF 1 R14C22[2][B] inst5/n61_s2/F
11.915 0.000 tNET FF 1 R14C22[2][B] inst5/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C22[2][B] inst5/count_0_s0/CLK
41.111 -0.400 tSu 1 R14C22[2][B] inst5/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.414, 45.881%; route: 3.569, 47.959%; tC2Q: 0.458, 6.160%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path24

Path Summary:

Slack 29.196
Data Arrival Time 11.915
Data Required Time 41.111
From inst5/count_1_s0
To inst5/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
4.932 0.458 tC2Q RF 6 R14C22[2][A] inst5/count_1_s0/Q
6.240 1.308 tNET FF 2 R15C20[1][A] inst5/n7_s62/I0
7.198 0.958 tINS FF 1 R15C20[1][A] inst5/n7_s62/COUT
7.198 0.000 tNET FF 2 R15C20[1][B] inst5/n7_s63/CIN
7.255 0.057 tINS FF 1 R15C20[1][B] inst5/n7_s63/COUT
7.255 0.000 tNET FF 2 R15C20[2][A] inst5/n7_s64/CIN
7.312 0.057 tINS FF 1 R15C20[2][A] inst5/n7_s64/COUT
7.312 0.000 tNET FF 2 R15C20[2][B] inst5/n7_s65/CIN
7.369 0.057 tINS FF 1 R15C20[2][B] inst5/n7_s65/COUT
7.369 0.000 tNET FF 2 R15C21[0][A] inst5/n7_s66/CIN
7.426 0.057 tINS FF 1 R15C21[0][A] inst5/n7_s66/COUT
7.426 0.000 tNET FF 2 R15C21[0][B] inst5/n7_s67/CIN
7.483 0.057 tINS FF 1 R15C21[0][B] inst5/n7_s67/COUT
7.483 0.000 tNET FF 2 R15C21[1][A] inst5/n7_s68/CIN
7.540 0.057 tINS FF 1 R15C21[1][A] inst5/n7_s68/COUT
7.540 0.000 tNET FF 2 R15C21[1][B] inst5/n7_s69/CIN
7.597 0.057 tINS FF 1 R15C21[1][B] inst5/n7_s69/COUT
7.597 0.000 tNET FF 2 R15C21[2][A] inst5/n7_s70/CIN
7.654 0.057 tINS FF 1 R15C21[2][A] inst5/n7_s70/COUT
7.654 0.000 tNET FF 2 R15C21[2][B] inst5/n7_s71/CIN
7.711 0.057 tINS FF 1 R15C21[2][B] inst5/n7_s71/COUT
7.711 0.000 tNET FF 2 R15C22[0][A] inst5/n7_s72/CIN
7.768 0.057 tINS FF 1 R15C22[0][A] inst5/n7_s72/COUT
7.768 0.000 tNET FF 2 R15C22[0][B] inst5/n7_s73/CIN
7.825 0.057 tINS FF 1 R15C22[0][B] inst5/n7_s73/COUT
7.825 0.000 tNET FF 2 R15C22[1][A] inst5/n7_s74/CIN
7.882 0.057 tINS FF 1 R15C22[1][A] inst5/n7_s74/COUT
7.882 0.000 tNET FF 2 R15C22[1][B] inst5/n7_s75/CIN
7.939 0.057 tINS FF 1 R15C22[1][B] inst5/n7_s75/COUT
7.939 0.000 tNET FF 2 R15C22[2][A] inst5/n7_s76/CIN
7.996 0.057 tINS FF 1 R15C22[2][A] inst5/n7_s76/COUT
9.363 1.367 tNET FF 1 R14C20[2][B] inst5/n61_s6/I2
10.395 1.032 tINS FF 18 R14C20[2][B] inst5/n61_s6/F
11.289 0.893 tNET FF 1 R14C22[2][A] inst5/n60_s2/I2
11.915 0.626 tINS FF 1 R14C22[2][A] inst5/n60_s2/F
11.915 0.000 tNET FF 1 R14C22[2][A] inst5/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
41.111 -0.400 tSu 1 R14C22[2][A] inst5/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.414, 45.881%; route: 3.569, 47.959%; tC2Q: 0.458, 6.160%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Path25

Path Summary:

Slack 29.253
Data Arrival Time 11.858
Data Required Time 41.111
From inst5/count_1_s0
To inst5/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
4.230 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
4.474 0.244 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
4.932 0.458 tC2Q RF 6 R14C22[2][A] inst5/count_1_s0/Q
6.240 1.308 tNET FF 2 R15C20[1][A] inst5/n7_s62/I0
7.198 0.958 tINS FF 1 R15C20[1][A] inst5/n7_s62/COUT
7.198 0.000 tNET FF 2 R15C20[1][B] inst5/n7_s63/CIN
7.255 0.057 tINS FF 1 R15C20[1][B] inst5/n7_s63/COUT
7.255 0.000 tNET FF 2 R15C20[2][A] inst5/n7_s64/CIN
7.312 0.057 tINS FF 1 R15C20[2][A] inst5/n7_s64/COUT
7.312 0.000 tNET FF 2 R15C20[2][B] inst5/n7_s65/CIN
7.369 0.057 tINS FF 1 R15C20[2][B] inst5/n7_s65/COUT
7.369 0.000 tNET FF 2 R15C21[0][A] inst5/n7_s66/CIN
7.426 0.057 tINS FF 1 R15C21[0][A] inst5/n7_s66/COUT
7.426 0.000 tNET FF 2 R15C21[0][B] inst5/n7_s67/CIN
7.483 0.057 tINS FF 1 R15C21[0][B] inst5/n7_s67/COUT
7.483 0.000 tNET FF 2 R15C21[1][A] inst5/n7_s68/CIN
7.540 0.057 tINS FF 1 R15C21[1][A] inst5/n7_s68/COUT
7.540 0.000 tNET FF 2 R15C21[1][B] inst5/n7_s69/CIN
7.597 0.057 tINS FF 1 R15C21[1][B] inst5/n7_s69/COUT
7.597 0.000 tNET FF 2 R15C21[2][A] inst5/n7_s70/CIN
7.654 0.057 tINS FF 1 R15C21[2][A] inst5/n7_s70/COUT
7.654 0.000 tNET FF 2 R15C21[2][B] inst5/n7_s71/CIN
7.711 0.057 tINS FF 1 R15C21[2][B] inst5/n7_s71/COUT
7.711 0.000 tNET FF 2 R15C22[0][A] inst5/n7_s72/CIN
7.768 0.057 tINS FF 1 R15C22[0][A] inst5/n7_s72/COUT
7.768 0.000 tNET FF 2 R15C22[0][B] inst5/n7_s73/CIN
7.825 0.057 tINS FF 1 R15C22[0][B] inst5/n7_s73/COUT
7.825 0.000 tNET FF 2 R15C22[1][A] inst5/n7_s74/CIN
7.882 0.057 tINS FF 1 R15C22[1][A] inst5/n7_s74/COUT
7.882 0.000 tNET FF 2 R15C22[1][B] inst5/n7_s75/CIN
7.939 0.057 tINS FF 1 R15C22[1][B] inst5/n7_s75/COUT
7.939 0.000 tNET FF 2 R15C22[2][A] inst5/n7_s76/CIN
7.996 0.057 tINS FF 1 R15C22[2][A] inst5/n7_s76/COUT
9.363 1.367 tNET FF 1 R14C20[2][B] inst5/n61_s6/I2
10.389 1.026 tINS FR 18 R14C20[2][B] inst5/n61_s6/F
10.826 0.436 tNET RR 1 R14C21[1][B] inst5/n51_s2/I2
11.858 1.032 tINS RF 1 R14C21[1][B] inst5/n51_s2/F
11.858 0.000 tNET FF 1 R14C21[1][B] inst5/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
41.267 4.230 tINS RR 40 IOR17[A] clk_ibuf/O
41.511 0.244 tNET RR 1 R14C21[1][B] inst5/count_10_s0/CLK
41.111 -0.400 tSu 1 R14C21[1][B] inst5/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%
Arrival Data Path Delay cell: 3.814, 51.652%; route: 3.112, 42.141%; tC2Q: 0.458, 6.207%
Required Clock Path Delay cell: 4.230, 94.547%; route: 0.244, 5.453%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.708
Data Arrival Time 4.019
Data Required Time 3.311
From clkdiv_1/count_16_s0
To clkdiv_1/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C32[0][A] clkdiv_1/count_16_s0/CLK
3.644 0.333 tC2Q RR 4 R15C32[0][A] clkdiv_1/count_16_s0/Q
3.647 0.002 tNET RR 1 R15C32[0][A] clkdiv_1/n45_s4/I2
4.019 0.372 tINS RF 1 R15C32[0][A] clkdiv_1/n45_s4/F
4.019 0.000 tNET FF 1 R15C32[0][A] clkdiv_1/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C32[0][A] clkdiv_1/count_16_s0/CLK
3.311 0.000 tHld 1 R15C32[0][A] clkdiv_1/count_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path2

Path Summary:

Slack 0.708
Data Arrival Time 4.019
Data Required Time 3.311
From clkdiv_1/count_17_s0
To clkdiv_1/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C34[1][A] clkdiv_1/count_17_s0/CLK
3.644 0.333 tC2Q RR 3 R15C34[1][A] clkdiv_1/count_17_s0/Q
3.647 0.002 tNET RR 1 R15C34[1][A] clkdiv_1/n44_s5/I2
4.019 0.372 tINS RF 1 R15C34[1][A] clkdiv_1/n44_s5/F
4.019 0.000 tNET FF 1 R15C34[1][A] clkdiv_1/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C34[1][A] clkdiv_1/count_17_s0/CLK
3.311 0.000 tHld 1 R15C34[1][A] clkdiv_1/count_17_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path3

Path Summary:

Slack 0.709
Data Arrival Time 4.020
Data Required Time 3.311
From clkdiv_1/count_0_s0
To clkdiv_1/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R16C34[0][A] clkdiv_1/count_0_s0/CLK
3.644 0.333 tC2Q RR 5 R16C34[0][A] clkdiv_1/count_0_s0/Q
3.648 0.004 tNET RR 1 R16C34[0][A] clkdiv_1/n61_s10/I2
4.020 0.372 tINS RF 1 R16C34[0][A] clkdiv_1/n61_s10/F
4.020 0.000 tNET FF 1 R16C34[0][A] clkdiv_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R16C34[0][A] clkdiv_1/count_0_s0/CLK
3.311 0.000 tHld 1 R16C34[0][A] clkdiv_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path4

Path Summary:

Slack 0.709
Data Arrival Time 4.020
Data Required Time 3.311
From clkdiv_1/count_4_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R16C34[1][A] clkdiv_1/count_4_s0/CLK
3.644 0.333 tC2Q RR 5 R16C34[1][A] clkdiv_1/count_4_s0/Q
3.648 0.004 tNET RR 1 R16C34[1][A] clkdiv_1/n57_s4/I3
4.020 0.372 tINS RF 1 R16C34[1][A] clkdiv_1/n57_s4/F
4.020 0.000 tNET FF 1 R16C34[1][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R16C34[1][A] clkdiv_1/count_4_s0/CLK
3.311 0.000 tHld 1 R16C34[1][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path5

Path Summary:

Slack 0.709
Data Arrival Time 4.020
Data Required Time 3.311
From clkdiv_1/count_18_s0
To clkdiv_1/count_18_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C34[0][A] clkdiv_1/count_18_s0/CLK
3.644 0.333 tC2Q RR 4 R15C34[0][A] clkdiv_1/count_18_s0/Q
3.648 0.004 tNET RR 1 R15C34[0][A] clkdiv_1/n43_s5/I0
4.020 0.372 tINS RF 1 R15C34[0][A] clkdiv_1/n43_s5/F
4.020 0.000 tNET FF 1 R15C34[0][A] clkdiv_1/count_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C34[0][A] clkdiv_1/count_18_s0/CLK
3.311 0.000 tHld 1 R15C34[0][A] clkdiv_1/count_18_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path6

Path Summary:

Slack 0.710
Data Arrival Time 4.021
Data Required Time 3.311
From inst5/count_3_s0
To inst5/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C22[1][A] inst5/count_3_s0/CLK
3.644 0.333 tC2Q RR 4 R14C22[1][A] inst5/count_3_s0/Q
3.649 0.005 tNET RR 1 R14C22[1][A] inst5/n58_s2/I0
4.021 0.372 tINS RF 1 R14C22[1][A] inst5/n58_s2/F
4.021 0.000 tNET FF 1 R14C22[1][A] inst5/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C22[1][A] inst5/count_3_s0/CLK
3.311 0.000 tHld 1 R14C22[1][A] inst5/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path7

Path Summary:

Slack 0.710
Data Arrival Time 4.021
Data Required Time 3.311
From inst5/count_12_s0
To inst5/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C19[0][A] inst5/count_12_s0/CLK
3.644 0.333 tC2Q RR 5 R14C19[0][A] inst5/count_12_s0/Q
3.649 0.005 tNET RR 1 R14C19[0][A] inst5/n49_s2/I2
4.021 0.372 tINS RF 1 R14C19[0][A] inst5/n49_s2/F
4.021 0.000 tNET FF 1 R14C19[0][A] inst5/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C19[0][A] inst5/count_12_s0/CLK
3.311 0.000 tHld 1 R14C19[0][A] inst5/count_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path8

Path Summary:

Slack 0.710
Data Arrival Time 4.021
Data Required Time 3.311
From inst5/count_13_s0
To inst5/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C19[1][A] inst5/count_13_s0/CLK
3.644 0.333 tC2Q RR 4 R14C19[1][A] inst5/count_13_s0/Q
3.649 0.005 tNET RR 1 R14C19[1][A] inst5/n48_s2/I2
4.021 0.372 tINS RF 1 R14C19[1][A] inst5/n48_s2/F
4.021 0.000 tNET FF 1 R14C19[1][A] inst5/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C19[1][A] inst5/count_13_s0/CLK
3.311 0.000 tHld 1 R14C19[1][A] inst5/count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path9

Path Summary:

Slack 0.711
Data Arrival Time 1.747
Data Required Time 1.036
From inst2/index_0_s0
To inst2/index_0_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R14C32[1][A] clkdiv_1/clk_out_s0/Q
1.036 1.036 tNET RR 1 R14C31[1][A] inst2/index_0_s0/CLK
1.370 0.333 tC2Q RR 12 R14C31[1][A] inst2/index_0_s0/Q
1.375 0.006 tNET RR 1 R14C31[1][A] inst2/n137_s2/I0
1.747 0.372 tINS RF 1 R14C31[1][A] inst2/n137_s2/F
1.747 0.000 tNET FF 1 R14C31[1][A] inst2/index_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R14C32[1][A] clkdiv_1/clk_out_s0/Q
1.036 1.036 tNET RR 1 R14C31[1][A] inst2/index_0_s0/CLK
1.036 0.000 tHld 1 R14C31[1][A] inst2/index_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.036, 100.000%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.036, 100.000%

Path10

Path Summary:

Slack 0.711
Data Arrival Time 1.747
Data Required Time 1.036
From inst2/index_2_s0
To inst2/index_2_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R14C32[1][A] clkdiv_1/clk_out_s0/Q
1.036 1.036 tNET RR 1 R14C30[1][A] inst2/index_2_s0/CLK
1.370 0.333 tC2Q RR 10 R14C30[1][A] inst2/index_2_s0/Q
1.375 0.006 tNET RR 1 R14C30[1][A] inst2/n135_s0/I2
1.747 0.372 tINS RF 1 R14C30[1][A] inst2/n135_s0/F
1.747 0.000 tNET FF 1 R14C30[1][A] inst2/index_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R14C32[1][A] clkdiv_1/clk_out_s0/Q
1.036 1.036 tNET RR 1 R14C30[1][A] inst2/index_2_s0/CLK
1.036 0.000 tHld 1 R14C30[1][A] inst2/index_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.036, 100.000%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.036, 100.000%

Path11

Path Summary:

Slack 0.711
Data Arrival Time 4.022
Data Required Time 3.311
From inst5/count_7_s0
To inst5/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C23[0][A] inst5/count_7_s0/CLK
3.644 0.333 tC2Q RR 6 R15C23[0][A] inst5/count_7_s0/Q
3.650 0.006 tNET RR 1 R15C23[0][A] inst5/n54_s2/I0
4.022 0.372 tINS RF 1 R15C23[0][A] inst5/n54_s2/F
4.022 0.000 tNET FF 1 R15C23[0][A] inst5/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C23[0][A] inst5/count_7_s0/CLK
3.311 0.000 tHld 1 R15C23[0][A] inst5/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path12

Path Summary:

Slack 0.711
Data Arrival Time 4.022
Data Required Time 3.311
From inst5/count_11_s0
To inst5/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C21[1][A] inst5/count_11_s0/CLK
3.644 0.333 tC2Q RR 6 R14C21[1][A] inst5/count_11_s0/Q
3.650 0.006 tNET RR 1 R14C21[1][A] inst5/n50_s2/I2
4.022 0.372 tINS RF 1 R14C21[1][A] inst5/n50_s2/F
4.022 0.000 tNET FF 1 R14C21[1][A] inst5/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C21[1][A] inst5/count_11_s0/CLK
3.311 0.000 tHld 1 R14C21[1][A] inst5/count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path13

Path Summary:

Slack 0.892
Data Arrival Time 4.203
Data Required Time 3.311
From clkdiv_1/count_2_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
3.644 0.333 tC2Q RR 3 R14C34[2][A] clkdiv_1/count_2_s0/Q
3.647 0.002 tNET RR 1 R14C34[2][A] clkdiv_1/n59_s4/I3
4.203 0.556 tINS RR 1 R14C34[2][A] clkdiv_1/n59_s4/F
4.203 0.000 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C34[2][A] clkdiv_1/count_2_s0/CLK
3.311 0.000 tHld 1 R14C34[2][A] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path14

Path Summary:

Slack 0.892
Data Arrival Time 4.203
Data Required Time 3.311
From clkdiv_1/count_14_s0
To clkdiv_1/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C32[2][A] clkdiv_1/count_14_s0/CLK
3.644 0.333 tC2Q RR 5 R14C32[2][A] clkdiv_1/count_14_s0/Q
3.647 0.002 tNET RR 1 R14C32[2][A] clkdiv_1/n47_s3/I2
4.203 0.556 tINS RR 1 R14C32[2][A] clkdiv_1/n47_s3/F
4.203 0.000 tNET RR 1 R14C32[2][A] clkdiv_1/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C32[2][A] clkdiv_1/count_14_s0/CLK
3.311 0.000 tHld 1 R14C32[2][A] clkdiv_1/count_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path15

Path Summary:

Slack 0.892
Data Arrival Time 4.203
Data Required Time 3.311
From clkdiv_1/count_15_s0
To clkdiv_1/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C34[2][A] clkdiv_1/count_15_s0/CLK
3.644 0.333 tC2Q RR 4 R15C34[2][A] clkdiv_1/count_15_s0/Q
3.647 0.002 tNET RR 1 R15C34[2][A] clkdiv_1/n46_s4/I2
4.203 0.556 tINS RR 1 R15C34[2][A] clkdiv_1/n46_s4/F
4.203 0.000 tNET RR 1 R15C34[2][A] clkdiv_1/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C34[2][A] clkdiv_1/count_15_s0/CLK
3.311 0.000 tHld 1 R15C34[2][A] clkdiv_1/count_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path16

Path Summary:

Slack 0.893
Data Arrival Time 4.204
Data Required Time 3.311
From clkdiv_1/count_11_s0
To clkdiv_1/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R16C34[2][A] clkdiv_1/count_11_s0/CLK
3.644 0.333 tC2Q RR 4 R16C34[2][A] clkdiv_1/count_11_s0/Q
3.648 0.004 tNET RR 1 R16C34[2][A] clkdiv_1/n50_s5/I2
4.204 0.556 tINS RR 1 R16C34[2][A] clkdiv_1/n50_s5/F
4.204 0.000 tNET RR 1 R16C34[2][A] clkdiv_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R16C34[2][A] clkdiv_1/count_11_s0/CLK
3.311 0.000 tHld 1 R16C34[2][A] clkdiv_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path17

Path Summary:

Slack 0.894
Data Arrival Time 4.205
Data Required Time 3.311
From inst5/count_5_s0
To inst5/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C20[2][A] inst5/count_5_s0/CLK
3.644 0.333 tC2Q RR 6 R14C20[2][A] inst5/count_5_s0/Q
3.649 0.005 tNET RR 1 R14C20[2][A] inst5/n56_s2/I2
4.205 0.556 tINS RR 1 R14C20[2][A] inst5/n56_s2/F
4.205 0.000 tNET RR 1 R14C20[2][A] inst5/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C20[2][A] inst5/count_5_s0/CLK
3.311 0.000 tHld 1 R14C20[2][A] inst5/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path18

Path Summary:

Slack 0.894
Data Arrival Time 4.205
Data Required Time 3.311
From inst5/count_9_s0
To inst5/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C21[2][A] inst5/count_9_s0/CLK
3.644 0.333 tC2Q RR 4 R14C21[2][A] inst5/count_9_s0/Q
3.649 0.005 tNET RR 1 R14C21[2][A] inst5/n52_s2/I2
4.205 0.556 tINS RR 1 R14C21[2][A] inst5/n52_s2/F
4.205 0.000 tNET RR 1 R14C21[2][A] inst5/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C21[2][A] inst5/count_9_s0/CLK
3.311 0.000 tHld 1 R14C21[2][A] inst5/count_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path19

Path Summary:

Slack 0.896
Data Arrival Time 4.207
Data Required Time 3.311
From inst5/count_1_s0
To inst5/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
3.644 0.333 tC2Q RR 6 R14C22[2][A] inst5/count_1_s0/Q
3.651 0.007 tNET RR 1 R14C22[2][A] inst5/n60_s2/I0
4.207 0.556 tINS RR 1 R14C22[2][A] inst5/n60_s2/F
4.207 0.000 tNET RR 1 R14C22[2][A] inst5/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C22[2][A] inst5/count_1_s0/CLK
3.311 0.000 tHld 1 R14C22[2][A] inst5/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.556, 62.025%; route: 0.007, 0.790%; tC2Q: 0.333, 37.185%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path20

Path Summary:

Slack 0.942
Data Arrival Time 1.978
Data Required Time 1.036
From inst2/tmp_1_s1
To inst2/key_1_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R14C32[1][A] clkdiv_1/clk_out_s0/Q
1.036 1.036 tNET RR 1 R15C29[0][B] inst2/tmp_1_s1/CLK
1.370 0.333 tC2Q RR 1 R15C29[0][B] inst2/tmp_1_s1/Q
1.606 0.236 tNET RR 1 R15C29[1][B] inst2/n116_s3/I0
1.978 0.372 tINS RF 1 R15C29[1][B] inst2/n116_s3/F
1.978 0.000 tNET FF 1 R15C29[1][B] inst2/key_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R14C32[1][A] clkdiv_1/clk_out_s0/Q
1.036 1.036 tNET RR 1 R15C29[1][B] inst2/key_1_s0/CLK
1.036 0.000 tHld 1 R15C29[1][B] inst2/key_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.036, 100.000%
Arrival Data Path Delay cell: 0.372, 39.502%; route: 0.236, 25.102%; tC2Q: 0.333, 35.396%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.036, 100.000%

Path21

Path Summary:

Slack 0.954
Data Arrival Time 4.265
Data Required Time 3.311
From inst5/count_16_s0
To inst5/clk_out_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C19[1][B] inst5/count_16_s0/CLK
3.644 0.333 tC2Q RF 4 R14C19[1][B] inst5/count_16_s0/Q
3.893 0.249 tNET FF 1 R14C20[0][A] inst5/n63_s83/I0
4.265 0.372 tINS FF 1 R14C20[0][A] inst5/n63_s83/F
4.265 0.000 tNET FF 1 R14C20[0][A] inst5/clk_out_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C20[0][A] inst5/clk_out_s0/CLK
3.311 0.000 tHld 1 R14C20[0][A] inst5/clk_out_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 38.999%; route: 0.249, 26.055%; tC2Q: 0.333, 34.946%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path22

Path Summary:

Slack 0.954
Data Arrival Time 4.265
Data Required Time 3.311
From inst5/count_16_s0
To inst5/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C19[1][B] inst5/count_16_s0/CLK
3.644 0.333 tC2Q RF 4 R14C19[1][B] inst5/count_16_s0/Q
3.893 0.249 tNET FF 1 R14C20[0][B] inst5/n44_s2/I0
4.265 0.372 tINS FF 1 R14C20[0][B] inst5/n44_s2/F
4.265 0.000 tNET FF 1 R14C20[0][B] inst5/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C20[0][B] inst5/count_17_s0/CLK
3.311 0.000 tHld 1 R14C20[0][B] inst5/count_17_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 38.999%; route: 0.249, 26.055%; tC2Q: 0.333, 34.946%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path23

Path Summary:

Slack 0.958
Data Arrival Time 4.269
Data Required Time 3.311
From inst5/count_0_s0
To inst5/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C22[2][B] inst5/count_0_s0/CLK
3.644 0.333 tC2Q RR 7 R14C22[2][B] inst5/count_0_s0/Q
3.897 0.252 tNET RR 1 R14C22[1][B] inst5/n59_s2/I1
4.269 0.372 tINS RF 1 R14C22[1][B] inst5/n59_s2/F
4.269 0.000 tNET FF 1 R14C22[1][B] inst5/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R14C22[1][B] inst5/count_2_s0/CLK
3.311 0.000 tHld 1 R14C22[1][B] inst5/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 38.843%; route: 0.252, 26.351%; tC2Q: 0.333, 34.806%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path24

Path Summary:

Slack 0.966
Data Arrival Time 4.277
Data Required Time 3.311
From clkdiv_1/count_19_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C34[0][B] clkdiv_1/count_19_s0/CLK
3.644 0.333 tC2Q RF 21 R15C34[0][B] clkdiv_1/count_19_s0/Q
3.905 0.260 tNET FF 1 R16C34[0][B] clkdiv_1/n60_s3/I0
4.277 0.372 tINS FF 1 R16C34[0][B] clkdiv_1/n60_s3/F
4.277 0.000 tNET FF 1 R16C34[0][B] clkdiv_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R16C34[0][B] clkdiv_1/count_1_s0/CLK
3.311 0.000 tHld 1 R16C34[0][B] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 38.523%; route: 0.260, 26.958%; tC2Q: 0.333, 34.519%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Path25

Path Summary:

Slack 0.973
Data Arrival Time 4.284
Data Required Time 3.311
From clkdiv_1/count_19_s0
To clkdiv_1/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C34[0][B] clkdiv_1/count_19_s0/CLK
3.644 0.333 tC2Q RF 21 R15C34[0][B] clkdiv_1/count_19_s0/Q
3.912 0.267 tNET FF 1 R15C34[2][B] clkdiv_1/n49_s4/I1
4.284 0.372 tINS FF 1 R15C34[2][B] clkdiv_1/n49_s4/F
4.284 0.000 tNET FF 1 R15C34[2][B] clkdiv_1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
3.126 3.126 tINS RR 40 IOR17[A] clk_ibuf/O
3.311 0.185 tNET RR 1 R15C34[2][B] clkdiv_1/count_12_s0/CLK
3.311 0.000 tHld 1 R15C34[2][B] clkdiv_1/count_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%
Arrival Data Path Delay cell: 0.372, 38.245%; route: 0.267, 27.485%; tC2Q: 0.333, 34.270%
Required Clock Path Delay cell: 3.126, 94.425%; route: 0.185, 5.575%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 15.130
Actual Width: 16.380
Required Width: 1.250
Type: High Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_19_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.474 0.244 tNET RR clkdiv_1/count_19_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.658 2.140 tINS FF clk_ibuf/O
20.853 0.195 tNET FF clkdiv_1/count_19_s0/CLK

MPW2

MPW Summary:

Slack: 15.130
Actual Width: 16.380
Required Width: 1.250
Type: High Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_18_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.474 0.244 tNET RR clkdiv_1/count_18_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.658 2.140 tINS FF clk_ibuf/O
20.853 0.195 tNET FF clkdiv_1/count_18_s0/CLK

MPW3

MPW Summary:

Slack: 15.130
Actual Width: 16.380
Required Width: 1.250
Type: High Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_16_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.474 0.244 tNET RR clkdiv_1/count_16_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.658 2.140 tINS FF clk_ibuf/O
20.853 0.195 tNET FF clkdiv_1/count_16_s0/CLK

MPW4

MPW Summary:

Slack: 15.130
Actual Width: 16.380
Required Width: 1.250
Type: High Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_12_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.474 0.244 tNET RR clkdiv_1/count_12_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.658 2.140 tINS FF clk_ibuf/O
20.853 0.195 tNET FF clkdiv_1/count_12_s0/CLK

MPW5

MPW Summary:

Slack: 15.130
Actual Width: 16.380
Required Width: 1.250
Type: High Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.474 0.244 tNET RR clkdiv_1/count_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.658 2.140 tINS FF clk_ibuf/O
20.853 0.195 tNET FF clkdiv_1/count_4_s0/CLK

MPW6

MPW Summary:

Slack: 15.130
Actual Width: 16.380
Required Width: 1.250
Type: High Pulse Width
Clock: clk27mhz
Objects: inst5/count_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.474 0.244 tNET RR inst5/count_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.658 2.140 tINS FF clk_ibuf/O
20.853 0.195 tNET FF inst5/count_7_s0/CLK

MPW7

MPW Summary:

Slack: 15.130
Actual Width: 16.380
Required Width: 1.250
Type: High Pulse Width
Clock: clk27mhz
Objects: inst5/count_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.474 0.244 tNET RR inst5/count_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.658 2.140 tINS FF clk_ibuf/O
20.853 0.195 tNET FF inst5/count_8_s0/CLK

MPW8

MPW Summary:

Slack: 15.130
Actual Width: 16.380
Required Width: 1.250
Type: High Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.474 0.244 tNET RR clkdiv_1/count_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.658 2.140 tINS FF clk_ibuf/O
20.853 0.195 tNET FF clkdiv_1/count_5_s0/CLK

MPW9

MPW Summary:

Slack: 15.130
Actual Width: 16.380
Required Width: 1.250
Type: High Pulse Width
Clock: clk27mhz
Objects: inst5/count_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.474 0.244 tNET RR inst5/count_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.658 2.140 tINS FF clk_ibuf/O
20.853 0.195 tNET FF inst5/count_9_s0/CLK

MPW10

MPW Summary:

Slack: 15.130
Actual Width: 16.380
Required Width: 1.250
Type: High Pulse Width
Clock: clk27mhz
Objects: inst5/count_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR clk_ibuf/I
4.230 4.230 tINS RR clk_ibuf/O
4.474 0.244 tNET RR inst5/count_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.658 2.140 tINS FF clk_ibuf/O
20.853 0.195 tNET FF inst5/count_10_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
40 clk_d 28.000 0.262
40 clk50hz 19999974.000 1.709
21 count[19] 34.219 0.885
18 n61_14 28.539 1.354
17 key_15_5 19999974.000 3.604
15 n61_7 28.603 1.033
12 index[0] 19999974.000 1.322
11 index[1] 19999974.000 0.840
10 index[2] 19999976.000 0.836
8 count[13] 30.610 1.185

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R15C29 80.56%
R14C28 79.17%
R15C34 77.78%
R14C30 69.44%
R14C22 68.06%
R14C20 68.06%
R14C34 68.06%
R15C28 65.28%
R14C29 62.50%
R16C34 62.50%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk50hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 540000 [get_nets {clk50hz}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {clk27mhz}] -group [get_clocks {clk50hz}]