Timing Messages
Report Title | Timing Analysis Report |
Design File | C:\Gowin\SV_240812_mhut_2001\stopwatch\impl\gwsynthesis\stopwatch.vg |
Physical Constraints File | C:\Gowin\SV_240812_mhut_2001\stopwatch\src\stopwatch.cst |
Timing Constraint File | C:\Gowin\SV_240812_mhut_2001\stopwatch\src\stopwatch.sdc |
Tool Version | V1.9.10.01 (64-bit) |
Part Number | GW1NR-LV9QN88PC6/I5 |
Device | GW1NR-9 |
Device Version | C |
Created Time | Mon Aug 12 11:51:32 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C C6/I5 |
Hold Delay Model | Fast 1.26V 0C C6/I5 |
Numbers of Paths Analyzed | 265 |
Numbers of Endpoints Analyzed | 233 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | clk27mhz | Base | 37.037 | 27.000 | 0.000 | 18.518 | clk | ||
2 | clk160hz | Generated | 6249993.500 | 0.000 | 0.000 | 3124996.750 | clk | clk27mhz | clk160hz |
3 | clk400hz | Generated | 2499997.500 | 0.000 | 0.000 | 1249998.750 | clk | clk27mhz | clk400hz |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk27mhz | 27.000(MHz) | 111.884(MHz) | 5 | TOP |
2 | clk160hz | 0.000(MHz) | 153.846(MHz) | 2 | TOP |
3 | clk400hz | 0.000(MHz) | 210.526(MHz) | 2 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk27mhz | Setup | 0.000 | 0 |
clk27mhz | Hold | 0.000 | 0 |
clk160hz | Setup | 0.000 | 0 |
clk160hz | Hold | 0.000 | 0 |
clk400hz | Setup | 0.000 | 0 |
clk400hz | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 28.099 | cntr4max_1/cnt_1_s0/Q | cntr4max_4/cnt_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.538 |
2 | 28.099 | cntr4max_1/cnt_1_s0/Q | cntr4max_4/cnt_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.538 |
3 | 28.099 | cntr4max_1/cnt_1_s0/Q | cntr4max_4/cnt_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.538 |
4 | 29.415 | clkdiv_2/count_0_s0/Q | clkdiv_2/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.222 |
5 | 29.415 | clkdiv_2/count_0_s0/Q | clkdiv_2/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.222 |
6 | 29.415 | clkdiv_2/count_0_s0/Q | clkdiv_2/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.222 |
7 | 29.495 | clkdiv_3/count_0_s0/Q | clkdiv_3/clk_out_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.142 |
8 | 29.580 | clkdiv_1/count_0_s0/Q | clkdiv_1/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.057 |
9 | 29.580 | clkdiv_1/count_0_s0/Q | clkdiv_1/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.057 |
10 | 29.594 | cntr4max_1/cnt_1_s0/Q | cntr4max_4/cnt_3_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.400 |
11 | 29.594 | cntr4max_1/cnt_1_s0/Q | cntr4max_4/cnt_1_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.400 |
12 | 29.594 | cntr4max_1/cnt_1_s0/Q | cntr4max_4/cnt_2_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.400 |
13 | 29.620 | clkdiv_1/count_0_s0/Q | clkdiv_1/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.017 |
14 | 29.659 | clkdiv_2/count_0_s0/Q | clkdiv_2/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.978 |
15 | 29.673 | cntr4max_1/cnt_1_s0/Q | cntr4max_4/cnt_0_s1/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.964 |
16 | 29.682 | clkdiv_1/count_0_s0/Q | clkdiv_1/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.955 |
17 | 29.682 | clkdiv_1/count_0_s0/Q | clkdiv_1/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.955 |
18 | 29.757 | clkdiv_3/count_8_s0/Q | clkdiv_3/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.880 |
19 | 29.759 | clkdiv_2/count_0_s0/Q | clkdiv_2/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.878 |
20 | 29.759 | clkdiv_2/count_0_s0/Q | clkdiv_2/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.878 |
21 | 29.770 | clkdiv_3/count_8_s0/Q | clkdiv_3/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.867 |
22 | 29.770 | clkdiv_3/count_8_s0/Q | clkdiv_3/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.867 |
23 | 29.772 | clkdiv_1/count_12_s0/Q | clkdiv_1/count_18_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.865 |
24 | 29.815 | clkdiv_2/count_0_s0/Q | clkdiv_2/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.822 |
25 | 29.815 | clkdiv_2/count_0_s0/Q | clkdiv_2/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.822 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.708 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
2 | 0.708 | clkdiv_2/count_1_s0/Q | clkdiv_2/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
3 | 0.708 | clkdiv_2/count_3_s0/Q | clkdiv_2/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
4 | 0.708 | clkdiv_2/count_16_s0/Q | clkdiv_2/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
5 | 0.708 | clkdiv_1/count_2_s0/Q | clkdiv_1/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
6 | 0.709 | toggle_2/out_s0/Q | toggle_2/out_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
7 | 0.709 | clkdiv_3/count_5_s0/Q | clkdiv_3/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
8 | 0.709 | clkdiv_3/count_8_s0/Q | clkdiv_3/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
9 | 0.709 | clkdiv_3/count_11_s0/Q | clkdiv_3/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
10 | 0.709 | clkdiv_2/count_6_s0/Q | clkdiv_2/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
11 | 0.709 | clkdiv_2/count_12_s0/Q | clkdiv_2/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
12 | 0.709 | clkdiv_2/count_15_s0/Q | clkdiv_2/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
13 | 0.709 | clkdiv_1/count_4_s0/Q | clkdiv_1/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
14 | 0.709 | clkdiv_1/count_5_s0/Q | clkdiv_1/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
15 | 0.709 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
16 | 0.709 | clkdiv_1/count_10_s0/Q | clkdiv_1/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
17 | 0.709 | clkdiv_1/count_17_s0/Q | clkdiv_1/count_17_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
18 | 0.710 | cntr4max_1/cnt_0_s0/Q | cntr4max_1/cnt_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
19 | 0.710 | clkdiv_3/count_14_s0/Q | clkdiv_3/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
20 | 0.710 | clkdiv_3/count_16_s0/Q | clkdiv_3/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
21 | 0.710 | clkdiv_1/count_13_s0/Q | clkdiv_1/count_13_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
22 | 0.711 | cntr4max_4/cnt_1_s0/Q | cntr4max_4/cnt_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.711 |
23 | 0.712 | cntr4max_4/cnt_3_s0/Q | cntr4max_4/cnt_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.712 |
24 | 0.712 | cntr4max_3/cnt_2_s0/Q | cntr4max_3/cnt_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.712 |
25 | 0.712 | cntr4max_2/cnt_3_s0/Q | cntr4max_2/cnt_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.712 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_18_s0 |
2 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_16_s0 |
3 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_12_s0 |
4 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_4_s0 |
5 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_2/count_6_s0 |
6 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_0_s1 |
7 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_3_s0 |
8 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_2/count_7_s0 |
9 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_1_s0 |
10 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_2_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 28.099 |
Data Arrival Time | 10.870 |
Data Required Time | 38.969 |
From | cntr4max_1/cnt_1_s0 |
To | cntr4max_4/cnt_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C30[2][B] | cntr4max_1/cnt_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 17 | R13C30[2][B] | cntr4max_1/cnt_1_s0/Q |
4.437 | 1.646 | tNET | FF | 1 | R14C30[2][B] | cntr4max_1/clk1s_s0/I0 |
5.259 | 0.822 | tINS | FF | 4 | R14C30[2][B] | cntr4max_1/clk1s_s0/F |
6.095 | 0.836 | tNET | FF | 1 | R14C29[3][B] | cntr4max_2/clk10s_s/I2 |
6.720 | 0.625 | tINS | FR | 12 | R14C29[3][B] | cntr4max_2/clk10s_s/F |
7.156 | 0.437 | tNET | RR | 1 | R14C30[3][A] | cntr4max_3/clk1m_s1/I0 |
8.188 | 1.032 | tINS | RF | 8 | R14C30[3][A] | cntr4max_3/clk1m_s1/F |
9.838 | 1.649 | tNET | FF | 1 | R14C34[0][A] | cntr4max_4/n16_s2/I0 |
10.870 | 1.032 | tINS | FF | 1 | R14C34[0][A] | cntr4max_4/n16_s2/F |
10.870 | 0.000 | tNET | FF | 1 | R14C34[0][A] | cntr4max_4/cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[0][A] | cntr4max_4/cnt_3_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C34[0][A] | cntr4max_4/cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.511, 41.123%; route: 4.568, 53.509%; tC2Q: 0.458, 5.368% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path2
Path Summary:
Slack | 28.099 |
Data Arrival Time | 10.870 |
Data Required Time | 38.969 |
From | cntr4max_1/cnt_1_s0 |
To | cntr4max_4/cnt_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C30[2][B] | cntr4max_1/cnt_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 17 | R13C30[2][B] | cntr4max_1/cnt_1_s0/Q |
4.437 | 1.646 | tNET | FF | 1 | R14C30[2][B] | cntr4max_1/clk1s_s0/I0 |
5.259 | 0.822 | tINS | FF | 4 | R14C30[2][B] | cntr4max_1/clk1s_s0/F |
6.095 | 0.836 | tNET | FF | 1 | R14C29[3][B] | cntr4max_2/clk10s_s/I2 |
6.720 | 0.625 | tINS | FR | 12 | R14C29[3][B] | cntr4max_2/clk10s_s/F |
7.156 | 0.437 | tNET | RR | 1 | R14C30[3][A] | cntr4max_3/clk1m_s1/I0 |
8.188 | 1.032 | tINS | RF | 8 | R14C30[3][A] | cntr4max_3/clk1m_s1/F |
9.838 | 1.649 | tNET | FF | 1 | R14C34[1][A] | cntr4max_4/n18_s2/I1 |
10.870 | 1.032 | tINS | FF | 1 | R14C34[1][A] | cntr4max_4/n18_s2/F |
10.870 | 0.000 | tNET | FF | 1 | R14C34[1][A] | cntr4max_4/cnt_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[1][A] | cntr4max_4/cnt_1_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C34[1][A] | cntr4max_4/cnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.511, 41.123%; route: 4.568, 53.509%; tC2Q: 0.458, 5.368% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path3
Path Summary:
Slack | 28.099 |
Data Arrival Time | 10.870 |
Data Required Time | 38.969 |
From | cntr4max_1/cnt_1_s0 |
To | cntr4max_4/cnt_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C30[2][B] | cntr4max_1/cnt_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 17 | R13C30[2][B] | cntr4max_1/cnt_1_s0/Q |
4.437 | 1.646 | tNET | FF | 1 | R14C30[2][B] | cntr4max_1/clk1s_s0/I0 |
5.259 | 0.822 | tINS | FF | 4 | R14C30[2][B] | cntr4max_1/clk1s_s0/F |
6.095 | 0.836 | tNET | FF | 1 | R14C29[3][B] | cntr4max_2/clk10s_s/I2 |
6.720 | 0.625 | tINS | FR | 12 | R14C29[3][B] | cntr4max_2/clk10s_s/F |
7.156 | 0.437 | tNET | RR | 1 | R14C30[3][A] | cntr4max_3/clk1m_s1/I0 |
8.188 | 1.032 | tINS | RF | 8 | R14C30[3][A] | cntr4max_3/clk1m_s1/F |
9.838 | 1.649 | tNET | FF | 1 | R14C34[0][B] | cntr4max_4/n17_s2/I1 |
10.870 | 1.032 | tINS | FF | 1 | R14C34[0][B] | cntr4max_4/n17_s2/F |
10.870 | 0.000 | tNET | FF | 1 | R14C34[0][B] | cntr4max_4/cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[0][B] | cntr4max_4/cnt_2_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C34[0][B] | cntr4max_4/cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.511, 41.123%; route: 4.568, 53.509%; tC2Q: 0.458, 5.368% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path4
Path Summary:
Slack | 29.415 |
Data Arrival Time | 9.554 |
Data Required Time | 38.969 |
From | clkdiv_2/count_0_s0 |
To | clkdiv_2/count_4_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C28[0][B] | clkdiv_2/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 6 | R13C28[0][B] | clkdiv_2/count_0_s0/Q |
3.611 | 0.820 | tNET | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/I0 |
4.710 | 1.099 | tINS | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/F |
4.715 | 0.005 | tNET | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/I1 |
5.747 | 1.032 | tINS | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/F |
6.551 | 0.804 | tNET | FF | 1 | R15C28[2][B] | clkdiv_2/n7_s88/I2 |
7.650 | 1.099 | tINS | FF | 18 | R15C28[2][B] | clkdiv_2/n7_s88/F |
8.522 | 0.871 | tNET | FF | 1 | R13C27[2][A] | clkdiv_2/n57_s2/I0 |
9.554 | 1.032 | tINS | FF | 1 | R13C27[2][A] | clkdiv_2/n57_s2/F |
9.554 | 0.000 | tNET | FF | 1 | R13C27[2][A] | clkdiv_2/count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C27[2][A] | clkdiv_2/count_4_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C27[2][A] | clkdiv_2/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.262, 59.017%; route: 2.501, 34.636%; tC2Q: 0.458, 6.347% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path5
Path Summary:
Slack | 29.415 |
Data Arrival Time | 9.554 |
Data Required Time | 38.969 |
From | clkdiv_2/count_0_s0 |
To | clkdiv_2/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C28[0][B] | clkdiv_2/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 6 | R13C28[0][B] | clkdiv_2/count_0_s0/Q |
3.611 | 0.820 | tNET | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/I0 |
4.710 | 1.099 | tINS | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/F |
4.715 | 0.005 | tNET | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/I1 |
5.747 | 1.032 | tINS | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/F |
6.551 | 0.804 | tNET | FF | 1 | R15C28[2][B] | clkdiv_2/n7_s88/I2 |
7.650 | 1.099 | tINS | FF | 18 | R15C28[2][B] | clkdiv_2/n7_s88/F |
8.522 | 0.871 | tNET | FF | 1 | R13C27[1][A] | clkdiv_2/n55_s2/I2 |
9.554 | 1.032 | tINS | FF | 1 | R13C27[1][A] | clkdiv_2/n55_s2/F |
9.554 | 0.000 | tNET | FF | 1 | R13C27[1][A] | clkdiv_2/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C27[1][A] | clkdiv_2/count_6_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C27[1][A] | clkdiv_2/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.262, 59.017%; route: 2.501, 34.636%; tC2Q: 0.458, 6.347% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path6
Path Summary:
Slack | 29.415 |
Data Arrival Time | 9.554 |
Data Required Time | 38.969 |
From | clkdiv_2/count_0_s0 |
To | clkdiv_2/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C28[0][B] | clkdiv_2/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 6 | R13C28[0][B] | clkdiv_2/count_0_s0/Q |
3.611 | 0.820 | tNET | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/I0 |
4.710 | 1.099 | tINS | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/F |
4.715 | 0.005 | tNET | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/I1 |
5.747 | 1.032 | tINS | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/F |
6.551 | 0.804 | tNET | FF | 1 | R15C28[2][B] | clkdiv_2/n7_s88/I2 |
7.650 | 1.099 | tINS | FF | 18 | R15C28[2][B] | clkdiv_2/n7_s88/F |
8.522 | 0.871 | tNET | FF | 1 | R14C27[1][A] | clkdiv_2/n46_s2/I0 |
9.554 | 1.032 | tINS | FF | 1 | R14C27[1][A] | clkdiv_2/n46_s2/F |
9.554 | 0.000 | tNET | FF | 1 | R14C27[1][A] | clkdiv_2/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C27[1][A] | clkdiv_2/count_15_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C27[1][A] | clkdiv_2/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.262, 59.017%; route: 2.501, 34.636%; tC2Q: 0.458, 6.347% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path7
Path Summary:
Slack | 29.495 |
Data Arrival Time | 9.474 |
Data Required Time | 38.969 |
From | clkdiv_3/count_0_s0 |
To | clkdiv_3/clk_out_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C24[2][A] | clkdiv_3/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 6 | R13C24[2][A] | clkdiv_3/count_0_s0/Q |
3.169 | 0.378 | tNET | FF | 1 | R13C24[2][B] | clkdiv_3/n58_s3/I2 |
4.268 | 1.099 | tINS | FF | 2 | R13C24[2][B] | clkdiv_3/n58_s3/F |
5.077 | 0.810 | tNET | FF | 1 | R14C23[1][A] | clkdiv_3/n63_s82/I0 |
6.109 | 1.032 | tINS | FF | 1 | R14C23[1][A] | clkdiv_3/n63_s82/F |
6.930 | 0.821 | tNET | FF | 1 | R15C23[0][A] | clkdiv_3/n63_s80/I0 |
7.956 | 1.026 | tINS | FR | 1 | R15C23[0][A] | clkdiv_3/n63_s80/F |
8.375 | 0.419 | tNET | RR | 1 | R15C24[0][A] | clkdiv_3/n63_s79/I0 |
9.474 | 1.099 | tINS | RF | 1 | R15C24[0][A] | clkdiv_3/n63_s79/F |
9.474 | 0.000 | tNET | FF | 1 | R15C24[0][A] | clkdiv_3/clk_out_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C24[0][A] | clkdiv_3/clk_out_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C24[0][A] | clkdiv_3/clk_out_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.256, 59.590%; route: 2.428, 33.993%; tC2Q: 0.458, 6.417% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path8
Path Summary:
Slack | 29.580 |
Data Arrival Time | 9.389 |
Data Required Time | 38.969 |
From | clkdiv_1/count_0_s0 |
To | clkdiv_1/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C26[2][B] | clkdiv_1/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 5 | R13C26[2][B] | clkdiv_1/count_0_s0/Q |
3.153 | 0.363 | tNET | FF | 1 | R13C26[3][A] | clkdiv_1/n57_s3/I1 |
4.252 | 1.099 | tINS | FF | 7 | R13C26[3][A] | clkdiv_1/n57_s3/F |
5.076 | 0.824 | tNET | FF | 1 | R15C25[1][A] | clkdiv_1/n7_s80/I0 |
5.878 | 0.802 | tINS | FR | 1 | R15C25[1][A] | clkdiv_1/n7_s80/F |
6.297 | 0.419 | tNET | RR | 1 | R15C26[2][A] | clkdiv_1/n7_s89/I2 |
7.396 | 1.099 | tINS | RF | 20 | R15C26[2][A] | clkdiv_1/n7_s89/F |
8.290 | 0.893 | tNET | FF | 1 | R13C26[2][B] | clkdiv_1/n61_s2/I1 |
9.389 | 1.099 | tINS | FF | 1 | R13C26[2][B] | clkdiv_1/n61_s2/F |
9.389 | 0.000 | tNET | FF | 1 | R13C26[2][B] | clkdiv_1/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C26[2][B] | clkdiv_1/count_0_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C26[2][B] | clkdiv_1/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.099, 58.087%; route: 2.499, 35.418%; tC2Q: 0.458, 6.495% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path9
Path Summary:
Slack | 29.580 |
Data Arrival Time | 9.389 |
Data Required Time | 38.969 |
From | clkdiv_1/count_0_s0 |
To | clkdiv_1/count_4_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C26[2][B] | clkdiv_1/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 5 | R13C26[2][B] | clkdiv_1/count_0_s0/Q |
3.153 | 0.363 | tNET | FF | 1 | R13C26[3][A] | clkdiv_1/n57_s3/I1 |
4.252 | 1.099 | tINS | FF | 7 | R13C26[3][A] | clkdiv_1/n57_s3/F |
5.076 | 0.824 | tNET | FF | 1 | R15C25[1][A] | clkdiv_1/n7_s80/I0 |
5.878 | 0.802 | tINS | FR | 1 | R15C25[1][A] | clkdiv_1/n7_s80/F |
6.297 | 0.419 | tNET | RR | 1 | R15C26[2][A] | clkdiv_1/n7_s89/I2 |
7.396 | 1.099 | tINS | RF | 20 | R15C26[2][A] | clkdiv_1/n7_s89/F |
8.290 | 0.893 | tNET | FF | 1 | R13C26[1][A] | clkdiv_1/n57_s2/I0 |
9.389 | 1.099 | tINS | FF | 1 | R13C26[1][A] | clkdiv_1/n57_s2/F |
9.389 | 0.000 | tNET | FF | 1 | R13C26[1][A] | clkdiv_1/count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C26[1][A] | clkdiv_1/count_4_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C26[1][A] | clkdiv_1/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.099, 58.087%; route: 2.499, 35.418%; tC2Q: 0.458, 6.495% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path10
Path Summary:
Slack | 29.594 |
Data Arrival Time | 9.732 |
Data Required Time | 39.326 |
From | cntr4max_1/cnt_1_s0 |
To | cntr4max_4/cnt_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C30[2][B] | cntr4max_1/cnt_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 17 | R13C30[2][B] | cntr4max_1/cnt_1_s0/Q |
4.437 | 1.646 | tNET | FF | 1 | R14C30[2][B] | cntr4max_1/clk1s_s0/I0 |
5.259 | 0.822 | tINS | FF | 4 | R14C30[2][B] | cntr4max_1/clk1s_s0/F |
6.095 | 0.836 | tNET | FF | 1 | R14C29[3][B] | cntr4max_2/clk10s_s/I2 |
6.720 | 0.625 | tINS | FR | 12 | R14C29[3][B] | cntr4max_2/clk10s_s/F |
7.156 | 0.437 | tNET | RR | 1 | R14C30[3][A] | cntr4max_3/clk1m_s1/I0 |
8.182 | 1.026 | tINS | RR | 8 | R14C30[3][A] | cntr4max_3/clk1m_s1/F |
9.732 | 1.549 | tNET | RR | 1 | R14C34[0][A] | cntr4max_4/cnt_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[0][A] | cntr4max_4/cnt_3_s0/CLK |
39.326 | -0.043 | tSu | 1 | R14C34[0][A] | cntr4max_4/cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 2.473, 33.419%; route: 4.469, 60.387%; tC2Q: 0.458, 6.194% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path11
Path Summary:
Slack | 29.594 |
Data Arrival Time | 9.732 |
Data Required Time | 39.326 |
From | cntr4max_1/cnt_1_s0 |
To | cntr4max_4/cnt_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C30[2][B] | cntr4max_1/cnt_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 17 | R13C30[2][B] | cntr4max_1/cnt_1_s0/Q |
4.437 | 1.646 | tNET | FF | 1 | R14C30[2][B] | cntr4max_1/clk1s_s0/I0 |
5.259 | 0.822 | tINS | FF | 4 | R14C30[2][B] | cntr4max_1/clk1s_s0/F |
6.095 | 0.836 | tNET | FF | 1 | R14C29[3][B] | cntr4max_2/clk10s_s/I2 |
6.720 | 0.625 | tINS | FR | 12 | R14C29[3][B] | cntr4max_2/clk10s_s/F |
7.156 | 0.437 | tNET | RR | 1 | R14C30[3][A] | cntr4max_3/clk1m_s1/I0 |
8.182 | 1.026 | tINS | RR | 8 | R14C30[3][A] | cntr4max_3/clk1m_s1/F |
9.732 | 1.549 | tNET | RR | 1 | R14C34[1][A] | cntr4max_4/cnt_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[1][A] | cntr4max_4/cnt_1_s0/CLK |
39.326 | -0.043 | tSu | 1 | R14C34[1][A] | cntr4max_4/cnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 2.473, 33.419%; route: 4.469, 60.387%; tC2Q: 0.458, 6.194% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path12
Path Summary:
Slack | 29.594 |
Data Arrival Time | 9.732 |
Data Required Time | 39.326 |
From | cntr4max_1/cnt_1_s0 |
To | cntr4max_4/cnt_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C30[2][B] | cntr4max_1/cnt_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 17 | R13C30[2][B] | cntr4max_1/cnt_1_s0/Q |
4.437 | 1.646 | tNET | FF | 1 | R14C30[2][B] | cntr4max_1/clk1s_s0/I0 |
5.259 | 0.822 | tINS | FF | 4 | R14C30[2][B] | cntr4max_1/clk1s_s0/F |
6.095 | 0.836 | tNET | FF | 1 | R14C29[3][B] | cntr4max_2/clk10s_s/I2 |
6.720 | 0.625 | tINS | FR | 12 | R14C29[3][B] | cntr4max_2/clk10s_s/F |
7.156 | 0.437 | tNET | RR | 1 | R14C30[3][A] | cntr4max_3/clk1m_s1/I0 |
8.182 | 1.026 | tINS | RR | 8 | R14C30[3][A] | cntr4max_3/clk1m_s1/F |
9.732 | 1.549 | tNET | RR | 1 | R14C34[0][B] | cntr4max_4/cnt_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[0][B] | cntr4max_4/cnt_2_s0/CLK |
39.326 | -0.043 | tSu | 1 | R14C34[0][B] | cntr4max_4/cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 2.473, 33.419%; route: 4.469, 60.387%; tC2Q: 0.458, 6.194% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path13
Path Summary:
Slack | 29.620 |
Data Arrival Time | 9.349 |
Data Required Time | 38.969 |
From | clkdiv_1/count_0_s0 |
To | clkdiv_1/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C26[2][B] | clkdiv_1/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 5 | R13C26[2][B] | clkdiv_1/count_0_s0/Q |
3.153 | 0.363 | tNET | FF | 1 | R13C26[3][A] | clkdiv_1/n57_s3/I1 |
4.252 | 1.099 | tINS | FF | 7 | R13C26[3][A] | clkdiv_1/n57_s3/F |
5.076 | 0.824 | tNET | FF | 1 | R15C25[1][A] | clkdiv_1/n7_s80/I0 |
5.878 | 0.802 | tINS | FR | 1 | R15C25[1][A] | clkdiv_1/n7_s80/F |
6.297 | 0.419 | tNET | RR | 1 | R15C26[2][A] | clkdiv_1/n7_s89/I2 |
7.396 | 1.099 | tINS | RF | 20 | R15C26[2][A] | clkdiv_1/n7_s89/F |
8.250 | 0.854 | tNET | FF | 1 | R14C25[0][A] | clkdiv_1/n51_s4/I0 |
9.349 | 1.099 | tINS | FF | 1 | R14C25[0][A] | clkdiv_1/n51_s4/F |
9.349 | 0.000 | tNET | FF | 1 | R14C25[0][A] | clkdiv_1/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C25[0][A] | clkdiv_1/count_10_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C25[0][A] | clkdiv_1/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.099, 58.412%; route: 2.460, 35.057%; tC2Q: 0.458, 6.531% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path14
Path Summary:
Slack | 29.659 |
Data Arrival Time | 9.310 |
Data Required Time | 38.969 |
From | clkdiv_2/count_0_s0 |
To | clkdiv_2/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C28[0][B] | clkdiv_2/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 6 | R13C28[0][B] | clkdiv_2/count_0_s0/Q |
3.611 | 0.820 | tNET | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/I0 |
4.710 | 1.099 | tINS | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/F |
4.715 | 0.005 | tNET | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/I1 |
5.747 | 1.032 | tINS | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/F |
6.551 | 0.804 | tNET | FF | 1 | R15C28[2][B] | clkdiv_2/n7_s88/I2 |
7.650 | 1.099 | tINS | FF | 18 | R15C28[2][B] | clkdiv_2/n7_s88/F |
8.488 | 0.837 | tNET | FF | 1 | R15C27[0][B] | clkdiv_2/n59_s4/I0 |
9.310 | 0.822 | tINS | FF | 1 | R15C27[0][B] | clkdiv_2/n59_s4/F |
9.310 | 0.000 | tNET | FF | 1 | R15C27[0][B] | clkdiv_2/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C27[0][B] | clkdiv_2/count_2_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C27[0][B] | clkdiv_2/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.052, 58.071%; route: 2.467, 35.361%; tC2Q: 0.458, 6.569% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path15
Path Summary:
Slack | 29.673 |
Data Arrival Time | 9.296 |
Data Required Time | 38.969 |
From | cntr4max_1/cnt_1_s0 |
To | cntr4max_4/cnt_0_s1 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C30[2][B] | cntr4max_1/cnt_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 17 | R13C30[2][B] | cntr4max_1/cnt_1_s0/Q |
4.437 | 1.646 | tNET | FF | 1 | R14C30[2][B] | cntr4max_1/clk1s_s0/I0 |
5.259 | 0.822 | tINS | FF | 4 | R14C30[2][B] | cntr4max_1/clk1s_s0/F |
6.095 | 0.836 | tNET | FF | 1 | R14C29[3][B] | cntr4max_2/clk10s_s/I2 |
6.721 | 0.626 | tINS | FF | 12 | R14C29[3][B] | cntr4max_2/clk10s_s/F |
8.197 | 1.476 | tNET | FF | 1 | R14C34[2][A] | cntr4max_4/n19_s6/I0 |
9.296 | 1.099 | tINS | FF | 1 | R14C34[2][A] | cntr4max_4/n19_s6/F |
9.296 | 0.000 | tNET | FF | 1 | R14C34[2][A] | cntr4max_4/cnt_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[2][A] | cntr4max_4/cnt_0_s1/CLK |
38.969 | -0.400 | tSu | 1 | R14C34[2][A] | cntr4max_4/cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 2.547, 36.576%; route: 3.958, 56.842%; tC2Q: 0.458, 6.582% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path16
Path Summary:
Slack | 29.682 |
Data Arrival Time | 9.287 |
Data Required Time | 38.969 |
From | clkdiv_1/count_0_s0 |
To | clkdiv_1/count_5_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C26[2][B] | clkdiv_1/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 5 | R13C26[2][B] | clkdiv_1/count_0_s0/Q |
3.153 | 0.363 | tNET | FF | 1 | R13C26[3][A] | clkdiv_1/n57_s3/I1 |
4.252 | 1.099 | tINS | FF | 7 | R13C26[3][A] | clkdiv_1/n57_s3/F |
5.076 | 0.824 | tNET | FF | 1 | R15C25[1][A] | clkdiv_1/n7_s80/I0 |
5.878 | 0.802 | tINS | FR | 1 | R15C25[1][A] | clkdiv_1/n7_s80/F |
6.297 | 0.419 | tNET | RR | 1 | R15C26[2][A] | clkdiv_1/n7_s89/I2 |
7.396 | 1.099 | tINS | RF | 20 | R15C26[2][A] | clkdiv_1/n7_s89/F |
8.255 | 0.859 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n56_s2/I2 |
9.287 | 1.032 | tINS | FF | 1 | R13C25[0][A] | clkdiv_1/n56_s2/F |
9.287 | 0.000 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C25[0][A] | clkdiv_1/count_5_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C25[0][A] | clkdiv_1/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.032, 57.973%; route: 2.465, 35.437%; tC2Q: 0.458, 6.590% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path17
Path Summary:
Slack | 29.682 |
Data Arrival Time | 9.287 |
Data Required Time | 38.969 |
From | clkdiv_1/count_0_s0 |
To | clkdiv_1/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C26[2][B] | clkdiv_1/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 5 | R13C26[2][B] | clkdiv_1/count_0_s0/Q |
3.153 | 0.363 | tNET | FF | 1 | R13C26[3][A] | clkdiv_1/n57_s3/I1 |
4.252 | 1.099 | tINS | FF | 7 | R13C26[3][A] | clkdiv_1/n57_s3/F |
5.076 | 0.824 | tNET | FF | 1 | R15C25[1][A] | clkdiv_1/n7_s80/I0 |
5.878 | 0.802 | tINS | FR | 1 | R15C25[1][A] | clkdiv_1/n7_s80/F |
6.297 | 0.419 | tNET | RR | 1 | R15C26[2][A] | clkdiv_1/n7_s89/I2 |
7.396 | 1.099 | tINS | RF | 20 | R15C26[2][A] | clkdiv_1/n7_s89/F |
8.255 | 0.859 | tNET | FF | 1 | R13C25[1][A] | clkdiv_1/n55_s2/I2 |
9.287 | 1.032 | tINS | FF | 1 | R13C25[1][A] | clkdiv_1/n55_s2/F |
9.287 | 0.000 | tNET | FF | 1 | R13C25[1][A] | clkdiv_1/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/count_6_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C25[1][A] | clkdiv_1/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.032, 57.973%; route: 2.465, 35.437%; tC2Q: 0.458, 6.590% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path18
Path Summary:
Slack | 29.757 |
Data Arrival Time | 9.211 |
Data Required Time | 38.969 |
From | clkdiv_3/count_8_s0 |
To | clkdiv_3/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C23[1][A] | clkdiv_3/count_8_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C23[1][A] | clkdiv_3/count_8_s0/Q |
3.133 | 0.343 | tNET | FF | 1 | R13C23[2][B] | clkdiv_3/n51_s4/I0 |
4.232 | 1.099 | tINS | FF | 2 | R13C23[2][B] | clkdiv_3/n51_s4/F |
4.728 | 0.496 | tNET | FF | 1 | R15C23[3][A] | clkdiv_3/n61_s5/I3 |
5.789 | 1.061 | tINS | FR | 1 | R15C23[3][A] | clkdiv_3/n61_s5/F |
6.208 | 0.419 | tNET | RR | 1 | R15C24[3][B] | clkdiv_3/n61_s14/I0 |
7.240 | 1.032 | tINS | RF | 17 | R15C24[3][B] | clkdiv_3/n61_s14/F |
8.112 | 0.873 | tNET | FF | 1 | R13C24[0][B] | clkdiv_3/n58_s2/I2 |
9.211 | 1.099 | tINS | FF | 1 | R13C24[0][B] | clkdiv_3/n58_s2/F |
9.211 | 0.000 | tNET | FF | 1 | R13C24[0][B] | clkdiv_3/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C24[0][B] | clkdiv_3/count_3_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C24[0][B] | clkdiv_3/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.291, 62.373%; route: 2.130, 30.964%; tC2Q: 0.458, 6.662% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path19
Path Summary:
Slack | 29.759 |
Data Arrival Time | 9.210 |
Data Required Time | 38.969 |
From | clkdiv_2/count_0_s0 |
To | clkdiv_2/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C28[0][B] | clkdiv_2/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 6 | R13C28[0][B] | clkdiv_2/count_0_s0/Q |
3.611 | 0.820 | tNET | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/I0 |
4.710 | 1.099 | tINS | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/F |
4.715 | 0.005 | tNET | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/I1 |
5.747 | 1.032 | tINS | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/F |
6.551 | 0.804 | tNET | FF | 1 | R15C28[2][B] | clkdiv_2/n7_s88/I2 |
7.650 | 1.099 | tINS | FF | 18 | R15C28[2][B] | clkdiv_2/n7_s88/F |
8.178 | 0.528 | tNET | FF | 1 | R13C28[0][B] | clkdiv_2/n61_s2/I1 |
9.210 | 1.032 | tINS | FF | 1 | R13C28[0][B] | clkdiv_2/n61_s2/F |
9.210 | 0.000 | tNET | FF | 1 | R13C28[0][B] | clkdiv_2/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C28[0][B] | clkdiv_2/count_0_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C28[0][B] | clkdiv_2/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.262, 61.966%; route: 2.158, 31.370%; tC2Q: 0.458, 6.664% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path20
Path Summary:
Slack | 29.759 |
Data Arrival Time | 9.210 |
Data Required Time | 38.969 |
From | clkdiv_2/count_0_s0 |
To | clkdiv_2/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C28[0][B] | clkdiv_2/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 6 | R13C28[0][B] | clkdiv_2/count_0_s0/Q |
3.611 | 0.820 | tNET | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/I0 |
4.710 | 1.099 | tINS | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/F |
4.715 | 0.005 | tNET | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/I1 |
5.747 | 1.032 | tINS | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/F |
6.551 | 0.804 | tNET | FF | 1 | R15C28[2][B] | clkdiv_2/n7_s88/I2 |
7.650 | 1.099 | tINS | FF | 18 | R15C28[2][B] | clkdiv_2/n7_s88/F |
8.178 | 0.528 | tNET | FF | 1 | R13C28[0][A] | clkdiv_2/n60_s2/I0 |
9.210 | 1.032 | tINS | FF | 1 | R13C28[0][A] | clkdiv_2/n60_s2/F |
9.210 | 0.000 | tNET | FF | 1 | R13C28[0][A] | clkdiv_2/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C28[0][A] | clkdiv_2/count_1_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C28[0][A] | clkdiv_2/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.262, 61.966%; route: 2.158, 31.370%; tC2Q: 0.458, 6.664% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path21
Path Summary:
Slack | 29.770 |
Data Arrival Time | 9.199 |
Data Required Time | 38.969 |
From | clkdiv_3/count_8_s0 |
To | clkdiv_3/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C23[1][A] | clkdiv_3/count_8_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C23[1][A] | clkdiv_3/count_8_s0/Q |
3.133 | 0.343 | tNET | FF | 1 | R13C23[2][B] | clkdiv_3/n51_s4/I0 |
4.232 | 1.099 | tINS | FF | 2 | R13C23[2][B] | clkdiv_3/n51_s4/F |
4.728 | 0.496 | tNET | FF | 1 | R15C23[3][A] | clkdiv_3/n61_s5/I3 |
5.789 | 1.061 | tINS | FR | 1 | R15C23[3][A] | clkdiv_3/n61_s5/F |
6.208 | 0.419 | tNET | RR | 1 | R15C24[3][B] | clkdiv_3/n61_s14/I0 |
7.240 | 1.032 | tINS | RF | 17 | R15C24[3][B] | clkdiv_3/n61_s14/F |
8.100 | 0.860 | tNET | FF | 1 | R13C23[1][A] | clkdiv_3/n53_s2/I3 |
9.199 | 1.099 | tINS | FF | 1 | R13C23[1][A] | clkdiv_3/n53_s2/F |
9.199 | 0.000 | tNET | FF | 1 | R13C23[1][A] | clkdiv_3/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C23[1][A] | clkdiv_3/count_8_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C23[1][A] | clkdiv_3/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.291, 62.490%; route: 2.117, 30.836%; tC2Q: 0.458, 6.675% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path22
Path Summary:
Slack | 29.770 |
Data Arrival Time | 9.199 |
Data Required Time | 38.969 |
From | clkdiv_3/count_8_s0 |
To | clkdiv_3/count_14_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C23[1][A] | clkdiv_3/count_8_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C23[1][A] | clkdiv_3/count_8_s0/Q |
3.133 | 0.343 | tNET | FF | 1 | R13C23[2][B] | clkdiv_3/n51_s4/I0 |
4.232 | 1.099 | tINS | FF | 2 | R13C23[2][B] | clkdiv_3/n51_s4/F |
4.728 | 0.496 | tNET | FF | 1 | R15C23[3][A] | clkdiv_3/n61_s5/I3 |
5.789 | 1.061 | tINS | FR | 1 | R15C23[3][A] | clkdiv_3/n61_s5/F |
6.208 | 0.419 | tNET | RR | 1 | R15C24[3][B] | clkdiv_3/n61_s14/I0 |
7.240 | 1.032 | tINS | RF | 17 | R15C24[3][B] | clkdiv_3/n61_s14/F |
8.100 | 0.860 | tNET | FF | 1 | R14C24[1][A] | clkdiv_3/n47_s2/I3 |
9.199 | 1.099 | tINS | FF | 1 | R14C24[1][A] | clkdiv_3/n47_s2/F |
9.199 | 0.000 | tNET | FF | 1 | R14C24[1][A] | clkdiv_3/count_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C24[1][A] | clkdiv_3/count_14_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C24[1][A] | clkdiv_3/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.291, 62.490%; route: 2.117, 30.836%; tC2Q: 0.458, 6.675% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path23
Path Summary:
Slack | 29.772 |
Data Arrival Time | 9.196 |
Data Required Time | 38.969 |
From | clkdiv_1/count_12_s0 |
To | clkdiv_1/count_18_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R14C25[1][B] | clkdiv_1/count_12_s0/CLK |
2.790 | 0.458 | tC2Q | RR | 2 | R14C25[1][B] | clkdiv_1/count_12_s0/Q |
3.210 | 0.420 | tNET | RR | 1 | R14C25[2][A] | clkdiv_1/n7_s83/I3 |
4.271 | 1.061 | tINS | RR | 2 | R14C25[2][A] | clkdiv_1/n7_s83/F |
4.692 | 0.421 | tNET | RR | 1 | R15C25[3][A] | clkdiv_1/n48_s3/I0 |
5.791 | 1.099 | tINS | RF | 5 | R15C25[3][A] | clkdiv_1/n48_s3/F |
6.616 | 0.824 | tNET | FF | 1 | R14C26[0][B] | clkdiv_1/n44_s3/I2 |
7.677 | 1.061 | tINS | FR | 2 | R14C26[0][B] | clkdiv_1/n44_s3/F |
8.097 | 0.421 | tNET | RR | 1 | R15C26[2][B] | clkdiv_1/n43_s2/I1 |
9.196 | 1.099 | tINS | RF | 1 | R15C26[2][B] | clkdiv_1/n43_s2/F |
9.196 | 0.000 | tNET | FF | 1 | R15C26[2][B] | clkdiv_1/count_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C26[2][B] | clkdiv_1/count_18_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C26[2][B] | clkdiv_1/count_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.320, 62.932%; route: 2.086, 30.391%; tC2Q: 0.458, 6.677% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path24
Path Summary:
Slack | 29.815 |
Data Arrival Time | 9.154 |
Data Required Time | 38.969 |
From | clkdiv_2/count_0_s0 |
To | clkdiv_2/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C28[0][B] | clkdiv_2/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 6 | R13C28[0][B] | clkdiv_2/count_0_s0/Q |
3.611 | 0.820 | tNET | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/I0 |
4.710 | 1.099 | tINS | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/F |
4.715 | 0.005 | tNET | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/I1 |
5.747 | 1.032 | tINS | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/F |
6.551 | 0.804 | tNET | FF | 1 | R15C28[2][B] | clkdiv_2/n7_s88/I2 |
7.612 | 1.061 | tINS | FR | 18 | R15C28[2][B] | clkdiv_2/n7_s88/F |
8.055 | 0.442 | tNET | RR | 1 | R15C27[1][A] | clkdiv_2/n58_s2/I2 |
9.154 | 1.099 | tINS | RF | 1 | R15C27[1][A] | clkdiv_2/n58_s2/F |
9.154 | 0.000 | tNET | FF | 1 | R15C27[1][A] | clkdiv_2/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C27[1][A] | clkdiv_2/count_3_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C27[1][A] | clkdiv_2/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.291, 62.901%; route: 2.072, 30.380%; tC2Q: 0.458, 6.719% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path25
Path Summary:
Slack | 29.815 |
Data Arrival Time | 9.154 |
Data Required Time | 38.969 |
From | clkdiv_2/count_0_s0 |
To | clkdiv_2/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C28[0][B] | clkdiv_2/count_0_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 6 | R13C28[0][B] | clkdiv_2/count_0_s0/Q |
3.611 | 0.820 | tNET | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/I0 |
4.710 | 1.099 | tINS | FF | 1 | R15C27[2][B] | clkdiv_2/n7_s83/F |
4.715 | 0.005 | tNET | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/I1 |
5.747 | 1.032 | tINS | FF | 1 | R15C27[3][A] | clkdiv_2/n7_s80/F |
6.551 | 0.804 | tNET | FF | 1 | R15C28[2][B] | clkdiv_2/n7_s88/I2 |
7.612 | 1.061 | tINS | FR | 18 | R15C28[2][B] | clkdiv_2/n7_s88/F |
8.055 | 0.442 | tNET | RR | 1 | R15C27[0][A] | clkdiv_2/n45_s2/I3 |
9.154 | 1.099 | tINS | RF | 1 | R15C27[0][A] | clkdiv_2/n45_s2/F |
9.154 | 0.000 | tNET | FF | 1 | R15C27[0][A] | clkdiv_2/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C27[0][A] | clkdiv_2/count_16_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C27[0][A] | clkdiv_2/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.291, 62.901%; route: 2.072, 30.380%; tC2Q: 0.458, 6.719% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_3/count_2_s0 |
To | clkdiv_3/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C24[1][A] | clkdiv_3/count_2_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C24[1][A] | clkdiv_3/count_2_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R13C24[1][A] | clkdiv_3/n59_s2/I2 |
2.284 | 0.372 | tINS | RF | 1 | R13C24[1][A] | clkdiv_3/n59_s2/F |
2.284 | 0.000 | tNET | FF | 1 | R13C24[1][A] | clkdiv_3/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C24[1][A] | clkdiv_3/count_2_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C24[1][A] | clkdiv_3/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path2
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_2/count_1_s0 |
To | clkdiv_2/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C28[0][A] | clkdiv_2/count_1_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R13C28[0][A] | clkdiv_2/count_1_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R13C28[0][A] | clkdiv_2/n60_s2/I1 |
2.284 | 0.372 | tINS | RF | 1 | R13C28[0][A] | clkdiv_2/n60_s2/F |
2.284 | 0.000 | tNET | FF | 1 | R13C28[0][A] | clkdiv_2/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C28[0][A] | clkdiv_2/count_1_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C28[0][A] | clkdiv_2/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path3
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_2/count_3_s0 |
To | clkdiv_2/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C27[1][A] | clkdiv_2/count_3_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R15C27[1][A] | clkdiv_2/count_3_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R15C27[1][A] | clkdiv_2/n58_s2/I3 |
2.284 | 0.372 | tINS | RF | 1 | R15C27[1][A] | clkdiv_2/n58_s2/F |
2.284 | 0.000 | tNET | FF | 1 | R15C27[1][A] | clkdiv_2/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C27[1][A] | clkdiv_2/count_3_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C27[1][A] | clkdiv_2/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path4
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_2/count_16_s0 |
To | clkdiv_2/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C27[0][A] | clkdiv_2/count_16_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R15C27[0][A] | clkdiv_2/count_16_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R15C27[0][A] | clkdiv_2/n45_s2/I2 |
2.284 | 0.372 | tINS | RF | 1 | R15C27[0][A] | clkdiv_2/n45_s2/F |
2.284 | 0.000 | tNET | FF | 1 | R15C27[0][A] | clkdiv_2/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C27[0][A] | clkdiv_2/count_16_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C27[0][A] | clkdiv_2/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path5
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_1/count_2_s0 |
To | clkdiv_1/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C26[0][A] | clkdiv_1/count_2_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R13C26[0][A] | clkdiv_1/count_2_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R13C26[0][A] | clkdiv_1/n59_s4/I1 |
2.284 | 0.372 | tINS | RF | 1 | R13C26[0][A] | clkdiv_1/n59_s4/F |
2.284 | 0.000 | tNET | FF | 1 | R13C26[0][A] | clkdiv_1/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C26[0][A] | clkdiv_1/count_2_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C26[0][A] | clkdiv_1/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path6
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | toggle_2/out_s0 |
To | toggle_2/out_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C28[0][A] | toggle_2/out_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R15C28[0][A] | toggle_2/out_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R15C28[0][A] | toggle_2/n10_s1/I2 |
2.285 | 0.372 | tINS | RF | 1 | R15C28[0][A] | toggle_2/n10_s1/F |
2.285 | 0.000 | tNET | FF | 1 | R15C28[0][A] | toggle_2/out_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C28[0][A] | toggle_2/out_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C28[0][A] | toggle_2/out_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path7
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_3/count_5_s0 |
To | clkdiv_3/count_5_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C23[0][A] | clkdiv_3/count_5_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 6 | R16C23[0][A] | clkdiv_3/count_5_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R16C23[0][A] | clkdiv_3/n56_s2/I2 |
2.285 | 0.372 | tINS | RF | 1 | R16C23[0][A] | clkdiv_3/n56_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R16C23[0][A] | clkdiv_3/count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C23[0][A] | clkdiv_3/count_5_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C23[0][A] | clkdiv_3/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path8
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_3/count_8_s0 |
To | clkdiv_3/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C23[1][A] | clkdiv_3/count_8_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C23[1][A] | clkdiv_3/count_8_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C23[1][A] | clkdiv_3/n53_s2/I2 |
2.285 | 0.372 | tINS | RF | 1 | R13C23[1][A] | clkdiv_3/n53_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C23[1][A] | clkdiv_3/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C23[1][A] | clkdiv_3/count_8_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C23[1][A] | clkdiv_3/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path9
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_3/count_11_s0 |
To | clkdiv_3/count_11_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C23[0][A] | clkdiv_3/count_11_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 6 | R14C23[0][A] | clkdiv_3/count_11_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R14C23[0][A] | clkdiv_3/n50_s2/I2 |
2.285 | 0.372 | tINS | RF | 1 | R14C23[0][A] | clkdiv_3/n50_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R14C23[0][A] | clkdiv_3/count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C23[0][A] | clkdiv_3/count_11_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C23[0][A] | clkdiv_3/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path10
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_2/count_6_s0 |
To | clkdiv_2/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C27[1][A] | clkdiv_2/count_6_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C27[1][A] | clkdiv_2/count_6_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C27[1][A] | clkdiv_2/n55_s2/I3 |
2.285 | 0.372 | tINS | RF | 1 | R13C27[1][A] | clkdiv_2/n55_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C27[1][A] | clkdiv_2/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C27[1][A] | clkdiv_2/count_6_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C27[1][A] | clkdiv_2/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path11
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_2/count_12_s0 |
To | clkdiv_2/count_12_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C28[1][A] | clkdiv_2/count_12_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R14C28[1][A] | clkdiv_2/count_12_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R14C28[1][A] | clkdiv_2/n49_s2/I1 |
2.285 | 0.372 | tINS | RF | 1 | R14C28[1][A] | clkdiv_2/n49_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R14C28[1][A] | clkdiv_2/count_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C28[1][A] | clkdiv_2/count_12_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C28[1][A] | clkdiv_2/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path12
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_2/count_15_s0 |
To | clkdiv_2/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C27[1][A] | clkdiv_2/count_15_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R14C27[1][A] | clkdiv_2/count_15_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R14C27[1][A] | clkdiv_2/n46_s2/I1 |
2.285 | 0.372 | tINS | RF | 1 | R14C27[1][A] | clkdiv_2/n46_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R14C27[1][A] | clkdiv_2/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C27[1][A] | clkdiv_2/count_15_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C27[1][A] | clkdiv_2/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path13
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_4_s0 |
To | clkdiv_1/count_4_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C26[1][A] | clkdiv_1/count_4_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 6 | R13C26[1][A] | clkdiv_1/count_4_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C26[1][A] | clkdiv_1/n57_s2/I1 |
2.285 | 0.372 | tINS | RF | 1 | R13C26[1][A] | clkdiv_1/n57_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C26[1][A] | clkdiv_1/count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C26[1][A] | clkdiv_1/count_4_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C26[1][A] | clkdiv_1/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path14
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_5_s0 |
To | clkdiv_1/count_5_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C25[0][A] | clkdiv_1/count_5_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R13C25[0][A] | clkdiv_1/count_5_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C25[0][A] | clkdiv_1/n56_s2/I3 |
2.285 | 0.372 | tINS | RF | 1 | R13C25[0][A] | clkdiv_1/n56_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C25[0][A] | clkdiv_1/count_5_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C25[0][A] | clkdiv_1/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path15
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/count_6_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C25[1][A] | clkdiv_1/count_6_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/n55_s2/I3 |
2.285 | 0.372 | tINS | RF | 1 | R13C25[1][A] | clkdiv_1/n55_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C25[1][A] | clkdiv_1/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/count_6_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C25[1][A] | clkdiv_1/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path16
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_10_s0 |
To | clkdiv_1/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C25[0][A] | clkdiv_1/count_10_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R14C25[0][A] | clkdiv_1/count_10_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R14C25[0][A] | clkdiv_1/n51_s4/I1 |
2.285 | 0.372 | tINS | RF | 1 | R14C25[0][A] | clkdiv_1/n51_s4/F |
2.285 | 0.000 | tNET | FF | 1 | R14C25[0][A] | clkdiv_1/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C25[0][A] | clkdiv_1/count_10_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C25[0][A] | clkdiv_1/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path17
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_17_s0 |
To | clkdiv_1/count_17_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C26[1][A] | clkdiv_1/count_17_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R14C26[1][A] | clkdiv_1/count_17_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R14C26[1][A] | clkdiv_1/n44_s2/I1 |
2.285 | 0.372 | tINS | RF | 1 | R14C26[1][A] | clkdiv_1/n44_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R14C26[1][A] | clkdiv_1/count_17_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C26[1][A] | clkdiv_1/count_17_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C26[1][A] | clkdiv_1/count_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path18
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | cntr4max_1/cnt_0_s0 |
To | cntr4max_1/cnt_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C30[1][A] | cntr4max_1/cnt_0_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 18 | R13C30[1][A] | cntr4max_1/cnt_0_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R13C30[1][A] | cntr4max_1/n19_s4/I0 |
2.287 | 0.372 | tINS | RF | 1 | R13C30[1][A] | cntr4max_1/n19_s4/F |
2.287 | 0.000 | tNET | FF | 1 | R13C30[1][A] | cntr4max_1/cnt_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C30[1][A] | cntr4max_1/cnt_0_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C30[1][A] | cntr4max_1/cnt_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path19
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_3/count_14_s0 |
To | clkdiv_3/count_14_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C24[1][A] | clkdiv_3/count_14_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 6 | R14C24[1][A] | clkdiv_3/count_14_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R14C24[1][A] | clkdiv_3/n47_s2/I2 |
2.287 | 0.372 | tINS | RF | 1 | R14C24[1][A] | clkdiv_3/n47_s2/F |
2.287 | 0.000 | tNET | FF | 1 | R14C24[1][A] | clkdiv_3/count_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C24[1][A] | clkdiv_3/count_14_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C24[1][A] | clkdiv_3/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path20
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_3/count_16_s0 |
To | clkdiv_3/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C24[1][A] | clkdiv_3/count_16_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 6 | R16C24[1][A] | clkdiv_3/count_16_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R16C24[1][A] | clkdiv_3/n45_s8/I1 |
2.287 | 0.372 | tINS | RF | 1 | R16C24[1][A] | clkdiv_3/n45_s8/F |
2.287 | 0.000 | tNET | FF | 1 | R16C24[1][A] | clkdiv_3/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C24[1][A] | clkdiv_3/count_16_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C24[1][A] | clkdiv_3/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path21
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_1/count_13_s0 |
To | clkdiv_1/count_13_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C26[1][A] | clkdiv_1/count_13_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R15C26[1][A] | clkdiv_1/count_13_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R15C26[1][A] | clkdiv_1/n48_s2/I1 |
2.287 | 0.372 | tINS | RF | 1 | R15C26[1][A] | clkdiv_1/n48_s2/F |
2.287 | 0.000 | tNET | FF | 1 | R15C26[1][A] | clkdiv_1/count_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C26[1][A] | clkdiv_1/count_13_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C26[1][A] | clkdiv_1/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path22
Path Summary:
Slack | 0.711 |
Data Arrival Time | 2.288 |
Data Required Time | 1.577 |
From | cntr4max_4/cnt_1_s0 |
To | cntr4max_4/cnt_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[1][A] | cntr4max_4/cnt_1_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 8 | R14C34[1][A] | cntr4max_4/cnt_1_s0/Q |
1.916 | 0.006 | tNET | RR | 1 | R14C34[1][A] | cntr4max_4/n18_s2/I3 |
2.288 | 0.372 | tINS | RF | 1 | R14C34[1][A] | cntr4max_4/n18_s2/F |
2.288 | 0.000 | tNET | FF | 1 | R14C34[1][A] | cntr4max_4/cnt_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[1][A] | cntr4max_4/cnt_1_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C34[1][A] | cntr4max_4/cnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path23
Path Summary:
Slack | 0.712 |
Data Arrival Time | 2.289 |
Data Required Time | 1.577 |
From | cntr4max_4/cnt_3_s0 |
To | cntr4max_4/cnt_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[0][A] | cntr4max_4/cnt_3_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 12 | R14C34[0][A] | cntr4max_4/cnt_3_s0/Q |
1.917 | 0.007 | tNET | RR | 1 | R14C34[0][A] | cntr4max_4/n16_s2/I3 |
2.289 | 0.372 | tINS | RF | 1 | R14C34[0][A] | cntr4max_4/n16_s2/F |
2.289 | 0.000 | tNET | FF | 1 | R14C34[0][A] | cntr4max_4/cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[0][A] | cntr4max_4/cnt_3_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C34[0][A] | cntr4max_4/cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path24
Path Summary:
Slack | 0.712 |
Data Arrival Time | 2.289 |
Data Required Time | 1.577 |
From | cntr4max_3/cnt_2_s0 |
To | cntr4max_3/cnt_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C30[1][A] | cntr4max_3/cnt_2_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 16 | R14C30[1][A] | cntr4max_3/cnt_2_s0/Q |
1.917 | 0.007 | tNET | RR | 1 | R14C30[1][A] | cntr4max_3/n17_s4/I1 |
2.289 | 0.372 | tINS | RF | 1 | R14C30[1][A] | cntr4max_3/n17_s4/F |
2.289 | 0.000 | tNET | FF | 1 | R14C30[1][A] | cntr4max_3/cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C30[1][A] | cntr4max_3/cnt_2_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C30[1][A] | cntr4max_3/cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path25
Path Summary:
Slack | 0.712 |
Data Arrival Time | 2.289 |
Data Required Time | 1.577 |
From | cntr4max_2/cnt_3_s0 |
To | cntr4max_2/cnt_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C30[0][A] | cntr4max_2/cnt_3_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 9 | R13C30[0][A] | cntr4max_2/cnt_3_s0/Q |
1.917 | 0.007 | tNET | RR | 1 | R13C30[0][A] | cntr4max_2/n16_s2/I3 |
2.289 | 0.372 | tINS | RF | 1 | R13C30[0][A] | cntr4max_2/n16_s2/F |
2.289 | 0.000 | tNET | FF | 1 | R13C30[0][A] | cntr4max_2/cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 79 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C30[0][A] | cntr4max_2/cnt_3_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C30[0][A] | cntr4max_2/cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_18_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_18_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_18_s0/CLK |
MPW2
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_16_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_16_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_16_s0/CLK |
MPW3
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_12_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_12_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_12_s0/CLK |
MPW4
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_4_s0/CLK |
MPW5
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_2/count_6_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_2/count_6_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_2/count_6_s0/CLK |
MPW6
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | cntr4maxe_1/cnt_0_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | cntr4maxe_1/cnt_0_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | cntr4maxe_1/cnt_0_s1/CLK |
MPW7
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | cntr4maxe_1/cnt_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | cntr4maxe_1/cnt_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | cntr4maxe_1/cnt_3_s0/CLK |
MPW8
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_2/count_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_2/count_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_2/count_7_s0/CLK |
MPW9
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | cntr4maxe_1/cnt_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | cntr4maxe_1/cnt_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | cntr4maxe_1/cnt_1_s0/CLK |
MPW10
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | cntr4maxe_1/cnt_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | cntr4maxe_1/cnt_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | cntr4maxe_1/cnt_2_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
79 | clk_d | 28.099 | 0.262 |
21 | col[0] | 6249987.000 | 1.344 |
20 | n7_122 | 29.580 | 1.069 |
19 | cnt100hz[0] | 29.694 | 1.793 |
18 | cnt10s[0] | 31.194 | 1.016 |
18 | cnt1s[0] | 29.712 | 1.651 |
18 | cnt10hz[0] | 29.108 | 1.824 |
18 | cnt100hz[1] | 29.353 | 1.805 |
18 | n7_120 | 29.415 | 1.479 |
17 | n61_20 | 29.757 | 0.873 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R13C30 | 77.78% |
R14C30 | 75.00% |
R13C26 | 68.06% |
R14C28 | 65.28% |
R14C34 | 65.28% |
R14C29 | 65.28% |
R15C28 | 62.50% |
R13C23 | 61.11% |
R13C28 | 58.33% |
R12C28 | 55.56% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk160hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 168750 [get_nets {clk160hz}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk400hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 67500 [get_nets {clk400hz}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk27mhz}] -group [get_clocks {clk400hz}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk27mhz}] -group [get_clocks {clk160hz}] |