Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\SV_240812_mhut_2001\stopwatch\src\clkdiv.sv C:\Gowin\SV_240812_mhut_2001\stopwatch\src\cntr4max.sv C:\Gowin\SV_240812_mhut_2001\stopwatch\src\cntr4maxe.sv C:\Gowin\SV_240812_mhut_2001\stopwatch\src\debounce.sv C:\Gowin\SV_240812_mhut_2001\stopwatch\src\dec_lec.sv C:\Gowin\SV_240812_mhut_2001\stopwatch\src\drv7seg.sv C:\Gowin\SV_240812_mhut_2001\stopwatch\src\mux7seg.sv C:\Gowin\SV_240812_mhut_2001\stopwatch\src\stopwatch.sv C:\Gowin\SV_240812_mhut_2001\stopwatch\src\toggle.sv |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.10.01 (64-bit) |
Part Number | GW1NR-LV9QN88PC6/I5 |
Device | GW1NR-9 |
Device Version | C |
Created Time | Mon Aug 12 11:51:18 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | stopwatch |
Synthesis Process | Running parser: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 133.254MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 133.254MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 133.254MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 133.254MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 133.254MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 133.254MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 133.254MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 133.254MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 133.254MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 133.254MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 133.254MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.562s, Elapsed time = 0h 0m 0.622s, Peak memory usage = 162.152MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.046s, Peak memory usage = 162.152MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 162.152MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.746s, Elapsed time = 0h 0m 0.799s, Peak memory usage = 162.152MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 23 |
I/O Buf | 23 |
    IBUF | 3 |
    OBUF | 20 |
Register | 98 |
    DFFE | 1 |
    DFFP | 8 |
    DFFC | 72 |
    DFFCE | 17 |
LUT | 221 |
    LUT2 | 34 |
    LUT3 | 88 |
    LUT4 | 99 |
INV | 3 |
    INV | 3 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 224(224 LUT, 0 ALU) / 8640 | 3% |
Register | 98 / 6693 | 2% |
  --Register as Latch | 0 / 6693 | 0% |
  --Register as FF | 98 / 6693 | 2% |
BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
2 | clkdiv_2/clk400hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_2/tc_s0/Q | ||
3 | clkdiv_3/clk160hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_3/clk_out_s0/Q |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.000(MHz) | 99.460(MHz) | 5 | TOP |
2 | clkdiv_2/clk400hz | 50.000(MHz) | 257.909(MHz) | 2 | TOP |
3 | clkdiv_3/clk160hz | 50.000(MHz) | 227.101(MHz) | 2 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 9.946 |
Data Arrival Time | 10.380 |
Data Required Time | 20.326 |
From | clkdiv_3/count_5_s0 |
To | clkdiv_3/count_17_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 79 | clk_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | clkdiv_3/count_5_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 6 | clkdiv_3/count_5_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | clkdiv_3/n54_s4/I1 |
3.243 | 1.099 | tINS | FF | 2 | clkdiv_3/n54_s4/F |
4.203 | 0.960 | tNET | FF | 1 | clkdiv_3/n48_s3/I1 |
5.302 | 1.099 | tINS | FF | 4 | clkdiv_3/n48_s3/F |
6.262 | 0.960 | tNET | FF | 1 | clkdiv_3/n45_s7/I1 |
7.361 | 1.099 | tINS | FF | 2 | clkdiv_3/n45_s7/F |
8.321 | 0.960 | tNET | FF | 1 | clkdiv_3/n44_s2/I1 |
9.420 | 1.099 | tINS | FF | 1 | clkdiv_3/n44_s2/F |
10.380 | 0.960 | tNET | FF | 1 | clkdiv_3/count_17_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 79 | clk_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | clkdiv_3/count_17_s0/CLK |
20.326 | -0.400 | tSu | 1 | clkdiv_3/count_17_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:Slack | 9.946 |
Data Arrival Time | 10.380 |
Data Required Time | 20.326 |
From | clkdiv_2/count_8_s0 |
To | clkdiv_2/count_16_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 79 | clk_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | clkdiv_2/count_8_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 3 | clkdiv_2/count_8_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | clkdiv_2/n50_s3/I1 |
3.243 | 1.099 | tINS | FF | 3 | clkdiv_2/n50_s3/F |
4.203 | 0.960 | tNET | FF | 1 | clkdiv_2/n49_s3/I1 |
5.302 | 1.099 | tINS | FF | 4 | clkdiv_2/n49_s3/F |
6.262 | 0.960 | tNET | FF | 1 | clkdiv_2/n46_s4/I1 |
7.361 | 1.099 | tINS | FF | 2 | clkdiv_2/n46_s4/F |
8.321 | 0.960 | tNET | FF | 1 | clkdiv_2/n45_s2/I1 |
9.420 | 1.099 | tINS | FF | 1 | clkdiv_2/n45_s2/F |
10.380 | 0.960 | tNET | FF | 1 | clkdiv_2/count_16_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 79 | clk_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | clkdiv_2/count_16_s0/CLK |
20.326 | -0.400 | tSu | 1 | clkdiv_2/count_16_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:Slack | 9.946 |
Data Arrival Time | 10.380 |
Data Required Time | 20.326 |
From | clkdiv_1/count_5_s0 |
To | clkdiv_1/count_11_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 79 | clk_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | clkdiv_1/count_5_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 5 | clkdiv_1/count_5_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | clkdiv_1/n54_s4/I1 |
3.243 | 1.099 | tINS | FF | 2 | clkdiv_1/n54_s4/F |
4.203 | 0.960 | tNET | FF | 1 | clkdiv_1/n52_s5/I1 |
5.302 | 1.099 | tINS | FF | 4 | clkdiv_1/n52_s5/F |
6.262 | 0.960 | tNET | FF | 1 | clkdiv_1/n51_s3/I1 |
7.361 | 1.099 | tINS | FF | 1 | clkdiv_1/n51_s3/F |
8.321 | 0.960 | tNET | FF | 1 | clkdiv_1/n50_s2/I1 |
9.420 | 1.099 | tINS | FF | 1 | clkdiv_1/n50_s2/F |
10.380 | 0.960 | tNET | FF | 1 | clkdiv_1/count_11_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 79 | clk_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | clkdiv_1/count_11_s0/CLK |
20.326 | -0.400 | tSu | 1 | clkdiv_1/count_11_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:Slack | 10.013 |
Data Arrival Time | 10.313 |
Data Required Time | 20.326 |
From | clkdiv_1/tc_s0 |
To | cntr4max_4/cnt_1_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 79 | clk_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | clkdiv_1/tc_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 3 | clkdiv_1/tc_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | cntr4maxe_1/clk10hz_s1/I1 |
3.243 | 1.099 | tINS | FF | 4 | cntr4maxe_1/clk10hz_s1/F |
4.203 | 0.960 | tNET | FF | 1 | cntr4max_2/clk10s_s/I1 |
5.302 | 1.099 | tINS | FF | 12 | cntr4max_2/clk10s_s/F |
6.262 | 0.960 | tNET | FF | 1 | cntr4max_3/clk1m_s1/I0 |
7.294 | 1.032 | tINS | FF | 8 | cntr4max_3/clk1m_s1/F |
8.254 | 0.960 | tNET | FF | 1 | cntr4max_4/n18_s2/I1 |
9.353 | 1.099 | tINS | FF | 1 | cntr4max_4/n18_s2/F |
10.313 | 0.960 | tNET | FF | 1 | cntr4max_4/cnt_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 79 | clk_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | cntr4max_4/cnt_1_s0/CLK |
20.326 | -0.400 | tSu | 1 | cntr4max_4/cnt_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:Slack | 10.013 |
Data Arrival Time | 10.313 |
Data Required Time | 20.326 |
From | clkdiv_1/tc_s0 |
To | cntr4max_4/cnt_2_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 79 | clk_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | clkdiv_1/tc_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 3 | clkdiv_1/tc_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | cntr4maxe_1/clk10hz_s1/I1 |
3.243 | 1.099 | tINS | FF | 4 | cntr4maxe_1/clk10hz_s1/F |
4.203 | 0.960 | tNET | FF | 1 | cntr4max_2/clk10s_s/I1 |
5.302 | 1.099 | tINS | FF | 12 | cntr4max_2/clk10s_s/F |
6.262 | 0.960 | tNET | FF | 1 | cntr4max_3/clk1m_s1/I0 |
7.294 | 1.032 | tINS | FF | 8 | cntr4max_3/clk1m_s1/F |
8.254 | 0.960 | tNET | FF | 1 | cntr4max_4/n17_s2/I1 |
9.353 | 1.099 | tINS | FF | 1 | cntr4max_4/n17_s2/F |
10.313 | 0.960 | tNET | FF | 1 | cntr4max_4/cnt_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 79 | clk_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | cntr4max_4/cnt_2_s0/CLK |
20.326 | -0.400 | tSu | 1 | cntr4max_4/cnt_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 5 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 4.329, 45.153%; route: 4.800, 50.066%; tC2Q: 0.458, 4.781% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |