Timing Messages

Report Title Timing Analysis Report
Design File C:\Gowin\SV_240812_mhut_2001\pwm_servo\impl\gwsynthesis\pwm_servo.vg
Physical Constraints File C:\Gowin\SV_240812_mhut_2001\pwm_servo\src\pwm_servo.cst
Timing Constraint File C:\Gowin\SV_240812_mhut_2001\pwm_servo\src\pwm_servo.sdc
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Aug 12 11:49:18 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C6/I5
Hold Delay Model Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed 137
Numbers of Endpoints Analyzed 80
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk27mhz Base 37.037 27.000 0.000 18.518 clk
2 clk100khz Generated 9999.989 0.100 0.000 4999.995 clk clk27mhz clk100khz

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk27mhz 27.000(MHz) 182.015(MHz) 4 TOP
2 clk100khz 0.100(MHz) 83.858(MHz) 6 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk27mhz Setup 0.000 0
clk27mhz Hold 0.000 0
clk100khz Setup 0.000 0
clk100khz Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 31.543 clkdiv_1/count_7_s0/Q clkdiv_1/count_8_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.094
2 32.037 clkdiv_1/count_3_s0/Q clkdiv_1/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.600
3 32.042 clkdiv_1/count_3_s0/Q clkdiv_1/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.595
4 32.054 clkdiv_1/count_6_s0/Q clkdiv_1/clk_out_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.583
5 32.145 clkdiv_1/count_3_s0/Q clkdiv_1/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.492
6 32.145 clkdiv_1/count_3_s0/Q clkdiv_1/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.492
7 32.145 clkdiv_1/count_3_s0/Q clkdiv_1/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.492
8 32.239 clkdiv_1/count_3_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.398
9 32.239 clkdiv_1/count_3_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.398
10 32.239 clkdiv_1/count_3_s0/Q clkdiv_1/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.398
11 9988.065 pwm_1/count_0_s0/Q pwm_1/line_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 11.525
12 9993.216 pwm_1/count_0_s0/Q pwm_1/count_12_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 6.373
13 9993.710 pwm_1/count_0_s0/Q pwm_1/count_9_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.880
14 9993.710 pwm_1/count_0_s0/Q pwm_1/count_10_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.880
15 9993.760 pwm_1/count_4_s0/Q pwm_1/count_15_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.830
16 9993.760 pwm_1/count_4_s0/Q pwm_1/count_14_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.830
17 9993.872 pwm_1/count_0_s0/Q pwm_1/count_6_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.718
18 9993.938 pwm_1/count_0_s0/Q pwm_1/count_4_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.651
19 9994.112 pwm_1/count_4_s0/Q pwm_1/count_13_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.478
20 9994.206 pwm_1/count_9_s0/Q pwm_1/tc_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.384
21 9994.278 pwm_1/count_0_s0/Q pwm_1/count_5_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.310
22 9994.347 pwm_1/count_0_s0/Q pwm_1/count_7_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.243
23 9994.347 pwm_1/count_0_s0/Q pwm_1/count_8_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.243
24 9994.346 pwm_1/count_0_s0/Q pwm_1/count_11_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 5.243
25 9995.268 pwm_1/count_0_s0/Q pwm_1/count_3_s0/D clk100khz:[R] clk100khz:[R] 9999.989 0.000 4.321

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.709 clkdiv_1/count_0_s0/Q clkdiv_1/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
2 0.709 clkdiv_1/count_1_s0/Q clkdiv_1/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
3 0.709 pwm_1/count_2_s0/Q pwm_1/count_2_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 0.709
4 0.709 pwm_1/count_4_s0/Q pwm_1/count_4_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 0.709
5 0.709 pwm_1/count_6_s0/Q pwm_1/count_6_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 0.709
6 0.709 pwm_1/count_13_s0/Q pwm_1/count_13_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 0.709
7 0.710 clkdiv_1/count_4_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.710
8 0.710 pwm_1/count_10_s0/Q pwm_1/count_10_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 0.710
9 0.892 pwm_1/count_15_s0/Q pwm_1/count_15_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 0.892
10 0.893 pwm_1/count_3_s0/Q pwm_1/count_3_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 0.893
11 0.893 pwm_1/count_8_s0/Q pwm_1/count_8_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 0.893
12 0.894 pwm_1/count_1_s0/Q pwm_1/count_1_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 0.894
13 0.943 clkdiv_1/count_8_s0/Q clkdiv_1/clk_out_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.943
14 0.946 clkdiv_1/count_4_s0/Q clkdiv_1/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.946
15 0.980 clkdiv_1/count_1_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.980
16 1.061 pwm_1/count_11_s0/Q pwm_1/count_11_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 1.061
17 1.061 pwm_1/count_12_s0/Q pwm_1/count_12_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 1.061
18 1.062 pwm_1/count_7_s0/Q pwm_1/count_7_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 1.062
19 1.062 pwm_1/count_14_s0/Q pwm_1/count_14_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 1.062
20 1.062 pwm_1/count_5_s0/Q pwm_1/count_5_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 1.062
21 1.065 pwm_1/count_0_s0/Q pwm_1/count_0_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 1.065
22 1.164 pwm_1/count_8_s0/Q pwm_1/tc_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 1.164
23 1.305 pwm_1/count_9_s0/Q pwm_1/count_9_s0/D clk100khz:[R] clk100khz:[R] 0.000 0.000 1.305
24 1.778 clkdiv_1/count_5_s0/Q clkdiv_1/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 1.778
25 2.187 clkdiv_1/count_4_s0/Q clkdiv_1/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 2.187

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 16.269 17.519 1.250 Low Pulse Width clk27mhz compare_7_s1
2 16.269 17.519 1.250 Low Pulse Width clk27mhz compare_2_s1
3 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_7_s0
4 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/clk_out_s0
5 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_0_s0
6 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_8_s0
7 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_1_s0
8 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_2_s0
9 16.269 17.519 1.250 Low Pulse Width clk27mhz compare_4_s1
10 16.269 17.519 1.250 Low Pulse Width clk27mhz compare_6_s1

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 31.543
Data Arrival Time 7.426
Data Required Time 38.969
From clkdiv_1/count_7_s0
To clkdiv_1/count_8_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R12C16[2][A] clkdiv_1/count_7_s0/CLK
2.790 0.458 tC2Q RF 4 R12C16[2][A] clkdiv_1/count_7_s0/Q
3.633 0.843 tNET FF 1 R12C18[0][B] clkdiv_1/n53_s4/I1
4.732 1.099 tINS FF 1 R12C18[0][B] clkdiv_1/n53_s4/F
4.738 0.005 tNET FF 1 R12C18[1][B] clkdiv_1/n53_s3/I2
5.837 1.099 tINS FF 1 R12C18[1][B] clkdiv_1/n53_s3/F
6.327 0.490 tNET FF 1 R12C16[1][B] clkdiv_1/n53_s5/I1
7.426 1.099 tINS FF 1 R12C16[1][B] clkdiv_1/n53_s5/F
7.426 0.000 tNET FF 1 R12C16[1][B] clkdiv_1/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R12C16[1][B] clkdiv_1/count_8_s0/CLK
38.969 -0.400 tSu 1 R12C16[1][B] clkdiv_1/count_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.297, 64.723%; route: 1.339, 26.280%; tC2Q: 0.458, 8.997%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path2

Path Summary:

Slack 32.037
Data Arrival Time 6.932
Data Required Time 38.969
From clkdiv_1/count_3_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/CLK
2.790 0.458 tC2Q RF 4 R12C16[1][A] clkdiv_1/count_3_s0/Q
3.624 0.833 tNET FF 1 R12C18[3][B] clkdiv_1/n61_s5/I3
4.446 0.822 tINS FF 1 R12C18[3][B] clkdiv_1/n61_s5/F
4.451 0.005 tNET FF 1 R12C18[3][A] clkdiv_1/n61_s4/I1
5.477 1.026 tINS FR 9 R12C18[3][A] clkdiv_1/n61_s4/F
5.900 0.423 tNET RR 1 R12C19[0][A] clkdiv_1/n60_s5/I0
6.932 1.032 tINS RF 1 R12C19[0][A] clkdiv_1/n60_s5/F
6.932 0.000 tNET FF 1 R12C19[0][A] clkdiv_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R12C19[0][A] clkdiv_1/count_1_s0/CLK
38.969 -0.400 tSu 1 R12C19[0][A] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 2.880, 62.609%; route: 1.262, 27.427%; tC2Q: 0.458, 9.964%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path3

Path Summary:

Slack 32.042
Data Arrival Time 6.927
Data Required Time 38.969
From clkdiv_1/count_3_s0
To clkdiv_1/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/CLK
2.790 0.458 tC2Q RF 4 R12C16[1][A] clkdiv_1/count_3_s0/Q
3.624 0.833 tNET FF 1 R12C18[2][A] clkdiv_1/n57_s4/I3
4.426 0.802 tINS FR 5 R12C18[2][A] clkdiv_1/n57_s4/F
4.856 0.431 tNET RR 1 R12C17[0][A] clkdiv_1/n55_s5/I0
5.882 1.026 tINS RR 1 R12C17[0][A] clkdiv_1/n55_s5/F
6.301 0.419 tNET RR 1 R12C16[0][B] clkdiv_1/n55_s6/I1
6.927 0.626 tINS RF 1 R12C16[0][B] clkdiv_1/n55_s6/F
6.927 0.000 tNET FF 1 R12C16[0][B] clkdiv_1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R12C16[0][B] clkdiv_1/count_6_s0/CLK
38.969 -0.400 tSu 1 R12C16[0][B] clkdiv_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 2.454, 53.403%; route: 1.683, 36.623%; tC2Q: 0.458, 9.974%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path4

Path Summary:

Slack 32.054
Data Arrival Time 6.915
Data Required Time 38.969
From clkdiv_1/count_6_s0
To clkdiv_1/clk_out_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R12C16[0][B] clkdiv_1/count_6_s0/CLK
2.790 0.458 tC2Q RF 4 R12C16[0][B] clkdiv_1/count_6_s0/Q
3.602 0.812 tNET FF 1 R12C18[0][A] clkdiv_1/n63_s84/I2
4.628 1.026 tINS FR 2 R12C18[0][A] clkdiv_1/n63_s84/F
5.049 0.421 tNET RR 1 R12C17[2][B] clkdiv_1/n63_s80/I2
5.674 0.625 tINS RR 1 R12C17[2][B] clkdiv_1/n63_s80/F
6.093 0.419 tNET RR 1 R12C16[2][B] clkdiv_1/n63_s89/I1
6.915 0.822 tINS RF 1 R12C16[2][B] clkdiv_1/n63_s89/F
6.915 0.000 tNET FF 1 R12C16[2][B] clkdiv_1/clk_out_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R12C16[2][B] clkdiv_1/clk_out_s0/CLK
38.969 -0.400 tSu 1 R12C16[2][B] clkdiv_1/clk_out_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 2.473, 53.964%; route: 1.651, 36.034%; tC2Q: 0.458, 10.001%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path5

Path Summary:

Slack 32.145
Data Arrival Time 6.824
Data Required Time 38.969
From clkdiv_1/count_3_s0
To clkdiv_1/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/CLK
2.790 0.458 tC2Q RF 4 R12C16[1][A] clkdiv_1/count_3_s0/Q
3.624 0.833 tNET FF 1 R12C18[3][B] clkdiv_1/n61_s5/I3
4.446 0.822 tINS FF 1 R12C18[3][B] clkdiv_1/n61_s5/F
4.451 0.005 tNET FF 1 R12C18[3][A] clkdiv_1/n61_s4/I1
5.483 1.032 tINS FF 9 R12C18[3][A] clkdiv_1/n61_s4/F
6.002 0.519 tNET FF 1 R12C16[0][A] clkdiv_1/n61_s6/I1
6.824 0.822 tINS FF 1 R12C16[0][A] clkdiv_1/n61_s6/F
6.824 0.000 tNET FF 1 R12C16[0][A] clkdiv_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R12C16[0][A] clkdiv_1/count_0_s0/CLK
38.969 -0.400 tSu 1 R12C16[0][A] clkdiv_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 2.676, 59.567%; route: 1.358, 30.231%; tC2Q: 0.458, 10.202%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path6

Path Summary:

Slack 32.145
Data Arrival Time 6.824
Data Required Time 38.969
From clkdiv_1/count_3_s0
To clkdiv_1/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/CLK
2.790 0.458 tC2Q RF 4 R12C16[1][A] clkdiv_1/count_3_s0/Q
3.624 0.833 tNET FF 1 R12C18[3][B] clkdiv_1/n61_s5/I3
4.446 0.822 tINS FF 1 R12C18[3][B] clkdiv_1/n61_s5/F
4.451 0.005 tNET FF 1 R12C18[3][A] clkdiv_1/n61_s4/I1
5.483 1.032 tINS FF 9 R12C18[3][A] clkdiv_1/n61_s4/F
6.002 0.519 tNET FF 1 R12C16[1][A] clkdiv_1/n58_s5/I0
6.824 0.822 tINS FF 1 R12C16[1][A] clkdiv_1/n58_s5/F
6.824 0.000 tNET FF 1 R12C16[1][A] clkdiv_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/CLK
38.969 -0.400 tSu 1 R12C16[1][A] clkdiv_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 2.676, 59.567%; route: 1.358, 30.231%; tC2Q: 0.458, 10.202%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path7

Path Summary:

Slack 32.145
Data Arrival Time 6.824
Data Required Time 38.969
From clkdiv_1/count_3_s0
To clkdiv_1/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/CLK
2.790 0.458 tC2Q RF 4 R12C16[1][A] clkdiv_1/count_3_s0/Q
3.624 0.833 tNET FF 1 R12C18[3][B] clkdiv_1/n61_s5/I3
4.446 0.822 tINS FF 1 R12C18[3][B] clkdiv_1/n61_s5/F
4.451 0.005 tNET FF 1 R12C18[3][A] clkdiv_1/n61_s4/I1
5.483 1.032 tINS FF 9 R12C18[3][A] clkdiv_1/n61_s4/F
6.002 0.519 tNET FF 1 R12C16[2][A] clkdiv_1/n54_s4/I0
6.824 0.822 tINS FF 1 R12C16[2][A] clkdiv_1/n54_s4/F
6.824 0.000 tNET FF 1 R12C16[2][A] clkdiv_1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R12C16[2][A] clkdiv_1/count_7_s0/CLK
38.969 -0.400 tSu 1 R12C16[2][A] clkdiv_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 2.676, 59.567%; route: 1.358, 30.231%; tC2Q: 0.458, 10.202%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path8

Path Summary:

Slack 32.239
Data Arrival Time 6.730
Data Required Time 38.969
From clkdiv_1/count_3_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/CLK
2.790 0.458 tC2Q RF 4 R12C16[1][A] clkdiv_1/count_3_s0/Q
3.624 0.833 tNET FF 1 R12C18[3][B] clkdiv_1/n61_s5/I3
4.446 0.822 tINS FF 1 R12C18[3][B] clkdiv_1/n61_s5/F
4.451 0.005 tNET FF 1 R12C18[3][A] clkdiv_1/n61_s4/I1
5.477 1.026 tINS FR 9 R12C18[3][A] clkdiv_1/n61_s4/F
5.908 0.431 tNET RR 1 R12C17[0][B] clkdiv_1/n59_s5/I0
6.730 0.822 tINS RF 1 R12C17[0][B] clkdiv_1/n59_s5/F
6.730 0.000 tNET FF 1 R12C17[0][B] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R12C17[0][B] clkdiv_1/count_2_s0/CLK
38.969 -0.400 tSu 1 R12C17[0][B] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 2.670, 60.711%; route: 1.270, 28.867%; tC2Q: 0.458, 10.422%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path9

Path Summary:

Slack 32.239
Data Arrival Time 6.730
Data Required Time 38.969
From clkdiv_1/count_3_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/CLK
2.790 0.458 tC2Q RF 4 R12C16[1][A] clkdiv_1/count_3_s0/Q
3.624 0.833 tNET FF 1 R12C18[3][B] clkdiv_1/n61_s5/I3
4.446 0.822 tINS FF 1 R12C18[3][B] clkdiv_1/n61_s5/F
4.451 0.005 tNET FF 1 R12C18[3][A] clkdiv_1/n61_s4/I1
5.477 1.026 tINS FR 9 R12C18[3][A] clkdiv_1/n61_s4/F
5.908 0.431 tNET RR 1 R12C17[1][A] clkdiv_1/n57_s6/I0
6.730 0.822 tINS RF 1 R12C17[1][A] clkdiv_1/n57_s6/F
6.730 0.000 tNET FF 1 R12C17[1][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R12C17[1][A] clkdiv_1/count_4_s0/CLK
38.969 -0.400 tSu 1 R12C17[1][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 2.670, 60.711%; route: 1.270, 28.867%; tC2Q: 0.458, 10.422%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path10

Path Summary:

Slack 32.239
Data Arrival Time 6.730
Data Required Time 38.969
From clkdiv_1/count_3_s0
To clkdiv_1/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/CLK
2.790 0.458 tC2Q RF 4 R12C16[1][A] clkdiv_1/count_3_s0/Q
3.624 0.833 tNET FF 1 R12C18[3][B] clkdiv_1/n61_s5/I3
4.446 0.822 tINS FF 1 R12C18[3][B] clkdiv_1/n61_s5/F
4.451 0.005 tNET FF 1 R12C18[3][A] clkdiv_1/n61_s4/I1
5.477 1.026 tINS FR 9 R12C18[3][A] clkdiv_1/n61_s4/F
5.908 0.431 tNET RR 1 R12C17[1][B] clkdiv_1/n56_s5/I0
6.730 0.822 tINS RF 1 R12C17[1][B] clkdiv_1/n56_s5/F
6.730 0.000 tNET FF 1 R12C17[1][B] clkdiv_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 15 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R12C17[1][B] clkdiv_1/count_5_s0/CLK
38.969 -0.400 tSu 1 R12C17[1][B] clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 2.670, 60.711%; route: 1.270, 28.867%; tC2Q: 0.458, 10.422%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path11

Path Summary:

Slack 9988.065
Data Arrival Time 13.384
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/line_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
3.958 1.639 tNET FF 2 R12C32[0][B] pwm_1/n40_s42/I0
4.916 0.958 tINS FF 1 R12C32[0][B] pwm_1/n40_s42/COUT
4.916 0.000 tNET FF 2 R12C32[1][A] pwm_1/n40_s43/CIN
4.973 0.057 tINS FF 1 R12C32[1][A] pwm_1/n40_s43/COUT
4.973 0.000 tNET FF 2 R12C32[1][B] pwm_1/n40_s44/CIN
5.030 0.057 tINS FF 1 R12C32[1][B] pwm_1/n40_s44/COUT
5.030 0.000 tNET FF 2 R12C32[2][A] pwm_1/n40_s45/CIN
5.087 0.057 tINS FF 1 R12C32[2][A] pwm_1/n40_s45/COUT
6.618 1.532 tNET FF 1 R12C25[0][B] pwm_1/n61_s5/I3
7.717 1.099 tINS FF 1 R12C25[0][B] pwm_1/n61_s5/F
7.723 0.005 tNET FF 1 R12C25[2][A] pwm_1/n61_s2/I2
8.822 1.099 tINS FF 1 R12C25[2][A] pwm_1/n61_s2/F
8.827 0.005 tNET FF 1 R12C25[1][A] pwm_1/n61_s7/I0
9.649 0.822 tINS FF 1 R12C25[1][A] pwm_1/n61_s7/F
13.385 3.736 tNET FF 1 IOR24[B] pwm_1/line_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 IOR24[B] pwm_1/line_s0/CLK
10001.449 -0.400 tSu 1 IOR24[B] pwm_1/line_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 6
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 4.149, 36.002%; route: 6.917, 60.021%; tC2Q: 0.458, 3.977%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path12

Path Summary:

Slack 9993.216
Data Arrival Time 8.233
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/count_12_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
4.112 1.793 tNET FF 1 R12C24[3][A] pwm_1/n35_s3/I1
5.144 1.032 tINS FF 9 R12C24[3][A] pwm_1/n35_s3/F
5.645 0.501 tNET FF 1 R12C23[1][A] pwm_1/n28_s3/I1
6.467 0.822 tINS FF 2 R12C23[1][A] pwm_1/n28_s3/F
7.607 1.141 tNET FF 1 R12C25[1][B] pwm_1/n27_s2/I0
8.233 0.626 tINS FF 1 R12C25[1][B] pwm_1/n27_s2/F
8.233 0.000 tNET FF 1 R12C25[1][B] pwm_1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C25[1][B] pwm_1/count_12_s0/CLK
10001.449 -0.400 tSu 1 R12C25[1][B] pwm_1/count_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.480, 38.914%; route: 3.435, 53.894%; tC2Q: 0.458, 7.192%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path13

Path Summary:

Slack 9993.710
Data Arrival Time 7.739
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/count_9_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
4.112 1.793 tNET FF 1 R12C24[3][A] pwm_1/n35_s3/I1
5.144 1.032 tINS FF 9 R12C24[3][A] pwm_1/n35_s3/F
6.004 0.861 tNET FF 1 R12C22[0][B] pwm_1/n30_s3/I1
6.630 0.626 tINS FF 2 R12C22[0][B] pwm_1/n30_s3/F
6.641 0.011 tNET FF 1 R12C22[1][B] pwm_1/n30_s2/I2
7.740 1.099 tINS FF 1 R12C22[1][B] pwm_1/n30_s2/F
7.740 0.000 tNET FF 1 R12C22[1][B] pwm_1/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C22[1][B] pwm_1/count_9_s0/CLK
10001.449 -0.400 tSu 1 R12C22[1][B] pwm_1/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.757, 46.889%; route: 2.665, 45.316%; tC2Q: 0.458, 7.795%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path14

Path Summary:

Slack 9993.710
Data Arrival Time 7.739
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/count_10_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
4.112 1.793 tNET FF 1 R12C24[3][A] pwm_1/n35_s3/I1
5.144 1.032 tINS FF 9 R12C24[3][A] pwm_1/n35_s3/F
6.004 0.861 tNET FF 1 R12C22[0][B] pwm_1/n30_s3/I1
6.630 0.626 tINS FF 2 R12C22[0][B] pwm_1/n30_s3/F
6.641 0.011 tNET FF 1 R12C22[1][A] pwm_1/n29_s2/I1
7.740 1.099 tINS FF 1 R12C22[1][A] pwm_1/n29_s2/F
7.740 0.000 tNET FF 1 R12C22[1][A] pwm_1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C22[1][A] pwm_1/count_10_s0/CLK
10001.449 -0.400 tSu 1 R12C22[1][A] pwm_1/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.757, 46.889%; route: 2.665, 45.316%; tC2Q: 0.458, 7.795%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path15

Path Summary:

Slack 9993.760
Data Arrival Time 7.689
Data Required Time 10001.449
From pwm_1/count_4_s0
To pwm_1/count_15_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[1][A] pwm_1/count_4_s0/CLK
2.319 0.458 tC2Q RF 7 R12C21[1][A] pwm_1/count_4_s0/Q
3.642 1.323 tNET FF 1 R12C25[3][A] pwm_1/n31_s3/I3
4.703 1.061 tINS FR 5 R12C25[3][A] pwm_1/n31_s3/F
5.129 0.427 tNET RR 1 R12C24[0][B] pwm_1/n26_s3/I2
6.228 1.099 tINS RF 3 R12C24[0][B] pwm_1/n26_s3/F
7.065 0.836 tNET FF 1 R12C23[2][A] pwm_1/n24_s2/I0
7.691 0.626 tINS FF 1 R12C23[2][A] pwm_1/n24_s2/F
7.691 0.000 tNET FF 1 R12C23[2][A] pwm_1/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C23[2][A] pwm_1/count_15_s0/CLK
10001.449 -0.400 tSu 1 R12C23[2][A] pwm_1/count_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.786, 47.787%; route: 2.586, 44.352%; tC2Q: 0.458, 7.862%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path16

Path Summary:

Slack 9993.760
Data Arrival Time 7.689
Data Required Time 10001.449
From pwm_1/count_4_s0
To pwm_1/count_14_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[1][A] pwm_1/count_4_s0/CLK
2.319 0.458 tC2Q RF 7 R12C21[1][A] pwm_1/count_4_s0/Q
3.642 1.323 tNET FF 1 R12C25[3][A] pwm_1/n31_s3/I3
4.703 1.061 tINS FR 5 R12C25[3][A] pwm_1/n31_s3/F
5.129 0.427 tNET RR 1 R12C24[0][B] pwm_1/n26_s3/I2
6.228 1.099 tINS RF 3 R12C24[0][B] pwm_1/n26_s3/F
7.065 0.836 tNET FF 1 R12C23[2][B] pwm_1/n25_s2/I1
7.691 0.626 tINS FF 1 R12C23[2][B] pwm_1/n25_s2/F
7.691 0.000 tNET FF 1 R12C23[2][B] pwm_1/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C23[2][B] pwm_1/count_14_s0/CLK
10001.449 -0.400 tSu 1 R12C23[2][B] pwm_1/count_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.786, 47.787%; route: 2.586, 44.352%; tC2Q: 0.458, 7.862%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path17

Path Summary:

Slack 9993.872
Data Arrival Time 7.577
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/count_6_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
4.112 1.793 tNET FF 1 R12C24[3][A] pwm_1/n35_s3/I1
5.144 1.032 tINS FF 9 R12C24[3][A] pwm_1/n35_s3/F
6.479 1.335 tNET FF 1 R12C21[0][A] pwm_1/n33_s2/I0
7.578 1.099 tINS FF 1 R12C21[0][A] pwm_1/n33_s2/F
7.578 0.000 tNET FF 1 R12C21[0][A] pwm_1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C21[0][A] pwm_1/count_6_s0/CLK
10001.449 -0.400 tSu 1 R12C21[0][A] pwm_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.131, 37.270%; route: 3.128, 54.713%; tC2Q: 0.458, 8.016%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path18

Path Summary:

Slack 9993.938
Data Arrival Time 7.511
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/count_4_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
4.112 1.793 tNET FF 1 R12C24[3][A] pwm_1/n35_s3/I1
5.144 1.032 tINS FF 9 R12C24[3][A] pwm_1/n35_s3/F
6.479 1.335 tNET FF 1 R12C21[1][A] pwm_1/n35_s2/I2
7.511 1.032 tINS FF 1 R12C21[1][A] pwm_1/n35_s2/F
7.511 0.000 tNET FF 1 R12C21[1][A] pwm_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C21[1][A] pwm_1/count_4_s0/CLK
10001.449 -0.400 tSu 1 R12C21[1][A] pwm_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.064, 36.527%; route: 3.128, 55.362%; tC2Q: 0.458, 8.111%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path19

Path Summary:

Slack 9994.112
Data Arrival Time 7.337
Data Required Time 10001.449
From pwm_1/count_4_s0
To pwm_1/count_13_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[1][A] pwm_1/count_4_s0/CLK
2.319 0.458 tC2Q RF 7 R12C21[1][A] pwm_1/count_4_s0/Q
3.642 1.323 tNET FF 1 R12C25[3][A] pwm_1/n31_s3/I3
4.703 1.061 tINS FR 5 R12C25[3][A] pwm_1/n31_s3/F
5.129 0.427 tNET RR 1 R12C24[0][B] pwm_1/n26_s3/I2
6.228 1.099 tINS RF 3 R12C24[0][B] pwm_1/n26_s3/F
6.239 0.011 tNET FF 1 R12C24[0][A] pwm_1/n26_s2/I2
7.338 1.099 tINS FF 1 R12C24[0][A] pwm_1/n26_s2/F
7.338 0.000 tNET FF 1 R12C24[0][A] pwm_1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C24[0][A] pwm_1/count_13_s0/CLK
10001.449 -0.400 tSu 1 R12C24[0][A] pwm_1/count_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 3.259, 59.493%; route: 1.761, 32.140%; tC2Q: 0.458, 8.367%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path20

Path Summary:

Slack 9994.206
Data Arrival Time 7.243
Data Required Time 10001.449
From pwm_1/count_9_s0
To pwm_1/tc_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C22[1][B] pwm_1/count_9_s0/CLK
2.319 0.458 tC2Q RF 7 R12C22[1][B] pwm_1/count_9_s0/Q
3.628 1.309 tNET FF 1 R12C25[0][A] pwm_1/n43_s50/I2
4.689 1.061 tINS FR 1 R12C25[0][A] pwm_1/n43_s50/F
5.108 0.419 tNET RR 1 R12C24[1][B] pwm_1/n43_s49/I3
6.140 1.032 tINS RF 1 R12C24[1][B] pwm_1/n43_s49/F
6.145 0.005 tNET FF 1 R12C24[1][A] pwm_1/n43_s51/I1
7.244 1.099 tINS FF 1 R12C24[1][A] pwm_1/n43_s51/F
7.244 0.000 tNET FF 1 R12C24[1][A] pwm_1/tc_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C24[1][A] pwm_1/tc_s0/CLK
10001.449 -0.400 tSu 1 R12C24[1][A] pwm_1/tc_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 3.192, 59.291%; route: 1.733, 32.196%; tC2Q: 0.458, 8.513%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path21

Path Summary:

Slack 9994.278
Data Arrival Time 7.171
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/count_5_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
4.112 1.793 tNET FF 1 R12C24[3][A] pwm_1/n35_s3/I1
5.144 1.032 tINS FF 9 R12C24[3][A] pwm_1/n35_s3/F
6.139 0.995 tNET FF 1 R12C21[0][B] pwm_1/n34_s2/I1
7.171 1.032 tINS FF 1 R12C21[0][B] pwm_1/n34_s2/F
7.171 0.000 tNET FF 1 R12C21[0][B] pwm_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C21[0][B] pwm_1/count_5_s0/CLK
10001.449 -0.400 tSu 1 R12C21[0][B] pwm_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.064, 38.870%; route: 2.788, 52.499%; tC2Q: 0.458, 8.631%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path22

Path Summary:

Slack 9994.347
Data Arrival Time 7.103
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/count_7_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
4.112 1.793 tNET FF 1 R12C24[3][A] pwm_1/n35_s3/I1
5.144 1.032 tINS FF 9 R12C24[3][A] pwm_1/n35_s3/F
6.004 0.861 tNET FF 1 R12C22[2][B] pwm_1/n32_s2/I0
7.103 1.099 tINS FF 1 R12C22[2][B] pwm_1/n32_s2/F
7.103 0.000 tNET FF 1 R12C22[2][B] pwm_1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C22[2][B] pwm_1/count_7_s0/CLK
10001.449 -0.400 tSu 1 R12C22[2][B] pwm_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.131, 40.645%; route: 2.654, 50.613%; tC2Q: 0.458, 8.742%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path23

Path Summary:

Slack 9994.347
Data Arrival Time 7.103
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/count_8_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
4.112 1.793 tNET FF 1 R12C24[3][A] pwm_1/n35_s3/I1
5.144 1.032 tINS FF 9 R12C24[3][A] pwm_1/n35_s3/F
6.004 0.861 tNET FF 1 R12C22[2][A] pwm_1/n31_s2/I0
7.103 1.099 tINS FF 1 R12C22[2][A] pwm_1/n31_s2/F
7.103 0.000 tNET FF 1 R12C22[2][A] pwm_1/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C22[2][A] pwm_1/count_8_s0/CLK
10001.449 -0.400 tSu 1 R12C22[2][A] pwm_1/count_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.131, 40.645%; route: 2.654, 50.613%; tC2Q: 0.458, 8.742%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path24

Path Summary:

Slack 9994.346
Data Arrival Time 7.104
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/count_11_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
4.112 1.793 tNET FF 1 R12C24[3][A] pwm_1/n35_s3/I1
5.144 1.032 tINS FF 9 R12C24[3][A] pwm_1/n35_s3/F
5.645 0.501 tNET FF 1 R12C23[1][A] pwm_1/n28_s3/I1
6.467 0.822 tINS FF 2 R12C23[1][A] pwm_1/n28_s3/F
6.478 0.011 tNET FF 1 R12C23[1][B] pwm_1/n28_s2/I0
7.104 0.626 tINS FF 1 R12C23[1][B] pwm_1/n28_s2/F
7.104 0.000 tNET FF 1 R12C23[1][B] pwm_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C23[1][B] pwm_1/count_11_s0/CLK
10001.449 -0.400 tSu 1 R12C23[1][B] pwm_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 4
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.480, 47.298%; route: 2.305, 43.961%; tC2Q: 0.458, 8.741%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Path25

Path Summary:

Slack 9995.268
Data Arrival Time 6.182
Data Required Time 10001.449
From pwm_1/count_0_s0
To pwm_1/count_3_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.860 1.860 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
2.319 0.458 tC2Q RF 6 R12C21[2][B] pwm_1/count_0_s0/Q
4.112 1.793 tNET FF 1 R12C24[2][B] pwm_1/n37_s3/I1
5.144 1.032 tINS FF 1 R12C24[2][B] pwm_1/n37_s3/F
5.149 0.005 tNET FF 1 R12C24[2][A] pwm_1/n36_s2/I1
6.181 1.032 tINS FF 1 R12C24[2][A] pwm_1/n36_s2/F
6.181 0.000 tNET FF 1 R12C24[2][A] pwm_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
9999.989 9999.989 active clock edge time
9999.989 0.000 clk100khz
9999.989 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
10001.850 1.860 tNET RR 1 R12C24[2][A] pwm_1/count_3_s0/CLK
10001.449 -0.400 tSu 1 R12C24[2][A] pwm_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 9999.989
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%
Arrival Data Path Delay cell: 2.064, 47.768%; route: 1.799, 41.624%; tC2Q: 0.458, 10.608%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.860, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_1/count_0_s0
To clkdiv_1/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C16[0][A] clkdiv_1/count_0_s0/CLK
1.910 0.333 tC2Q RR 7 R12C16[0][A] clkdiv_1/count_0_s0/Q
1.913 0.004 tNET RR 1 R12C16[0][A] clkdiv_1/n61_s6/I0
2.285 0.372 tINS RF 1 R12C16[0][A] clkdiv_1/n61_s6/F
2.285 0.000 tNET FF 1 R12C16[0][A] clkdiv_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C16[0][A] clkdiv_1/count_0_s0/CLK
1.577 0.000 tHld 1 R12C16[0][A] clkdiv_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path2

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_1/count_1_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C19[0][A] clkdiv_1/count_1_s0/CLK
1.910 0.333 tC2Q RR 6 R12C19[0][A] clkdiv_1/count_1_s0/Q
1.913 0.004 tNET RR 1 R12C19[0][A] clkdiv_1/n60_s5/I2
2.285 0.372 tINS RF 1 R12C19[0][A] clkdiv_1/n60_s5/F
2.285 0.000 tNET FF 1 R12C19[0][A] clkdiv_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C19[0][A] clkdiv_1/count_1_s0/CLK
1.577 0.000 tHld 1 R12C19[0][A] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path3

Path Summary:

Slack 0.709
Data Arrival Time 2.051
Data Required Time 1.342
From pwm_1/count_2_s0
To pwm_1/count_2_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C26[1][A] pwm_1/count_2_s0/CLK
1.675 0.333 tC2Q RR 4 R12C26[1][A] pwm_1/count_2_s0/Q
1.679 0.004 tNET RR 1 R12C26[1][A] pwm_1/n37_s4/I1
2.051 0.372 tINS RF 1 R12C26[1][A] pwm_1/n37_s4/F
2.051 0.000 tNET FF 1 R12C26[1][A] pwm_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C26[1][A] pwm_1/count_2_s0/CLK
1.342 0.000 tHld 1 R12C26[1][A] pwm_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path4

Path Summary:

Slack 0.709
Data Arrival Time 2.051
Data Required Time 1.342
From pwm_1/count_4_s0
To pwm_1/count_4_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C21[1][A] pwm_1/count_4_s0/CLK
1.675 0.333 tC2Q RR 7 R12C21[1][A] pwm_1/count_4_s0/Q
1.679 0.004 tNET RR 1 R12C21[1][A] pwm_1/n35_s2/I1
2.051 0.372 tINS RF 1 R12C21[1][A] pwm_1/n35_s2/F
2.051 0.000 tNET FF 1 R12C21[1][A] pwm_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C21[1][A] pwm_1/count_4_s0/CLK
1.342 0.000 tHld 1 R12C21[1][A] pwm_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path5

Path Summary:

Slack 0.709
Data Arrival Time 2.051
Data Required Time 1.342
From pwm_1/count_6_s0
To pwm_1/count_6_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C21[0][A] pwm_1/count_6_s0/CLK
1.675 0.333 tC2Q RR 5 R12C21[0][A] pwm_1/count_6_s0/Q
1.679 0.004 tNET RR 1 R12C21[0][A] pwm_1/n33_s2/I3
2.051 0.372 tINS RF 1 R12C21[0][A] pwm_1/n33_s2/F
2.051 0.000 tNET FF 1 R12C21[0][A] pwm_1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C21[0][A] pwm_1/count_6_s0/CLK
1.342 0.000 tHld 1 R12C21[0][A] pwm_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path6

Path Summary:

Slack 0.709
Data Arrival Time 2.051
Data Required Time 1.342
From pwm_1/count_13_s0
To pwm_1/count_13_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C24[0][A] pwm_1/count_13_s0/CLK
1.675 0.333 tC2Q RR 4 R12C24[0][A] pwm_1/count_13_s0/Q
1.679 0.004 tNET RR 1 R12C24[0][A] pwm_1/n26_s2/I1
2.051 0.372 tINS RF 1 R12C24[0][A] pwm_1/n26_s2/F
2.051 0.000 tNET FF 1 R12C24[0][A] pwm_1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C24[0][A] pwm_1/count_13_s0/CLK
1.342 0.000 tHld 1 R12C24[0][A] pwm_1/count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path7

Path Summary:

Slack 0.710
Data Arrival Time 2.287
Data Required Time 1.577
From clkdiv_1/count_4_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C17[1][A] clkdiv_1/count_4_s0/CLK
1.910 0.333 tC2Q RR 5 R12C17[1][A] clkdiv_1/count_4_s0/Q
1.915 0.005 tNET RR 1 R12C17[1][A] clkdiv_1/n57_s6/I1
2.287 0.372 tINS RF 1 R12C17[1][A] clkdiv_1/n57_s6/F
2.287 0.000 tNET FF 1 R12C17[1][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C17[1][A] clkdiv_1/count_4_s0/CLK
1.577 0.000 tHld 1 R12C17[1][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path8

Path Summary:

Slack 0.710
Data Arrival Time 2.052
Data Required Time 1.342
From pwm_1/count_10_s0
To pwm_1/count_10_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C22[1][A] pwm_1/count_10_s0/CLK
1.675 0.333 tC2Q RR 6 R12C22[1][A] pwm_1/count_10_s0/Q
1.680 0.005 tNET RR 1 R12C22[1][A] pwm_1/n29_s2/I3
2.052 0.372 tINS RF 1 R12C22[1][A] pwm_1/n29_s2/F
2.052 0.000 tNET FF 1 R12C22[1][A] pwm_1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C22[1][A] pwm_1/count_10_s0/CLK
1.342 0.000 tHld 1 R12C22[1][A] pwm_1/count_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path9

Path Summary:

Slack 0.892
Data Arrival Time 2.233
Data Required Time 1.342
From pwm_1/count_15_s0
To pwm_1/count_15_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C23[2][A] pwm_1/count_15_s0/CLK
1.675 0.333 tC2Q RR 2 R12C23[2][A] pwm_1/count_15_s0/Q
1.677 0.002 tNET RR 1 R12C23[2][A] pwm_1/n24_s2/I3
2.233 0.556 tINS RR 1 R12C23[2][A] pwm_1/n24_s2/F
2.233 0.000 tNET RR 1 R12C23[2][A] pwm_1/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C23[2][A] pwm_1/count_15_s0/CLK
1.342 0.000 tHld 1 R12C23[2][A] pwm_1/count_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path10

Path Summary:

Slack 0.893
Data Arrival Time 2.235
Data Required Time 1.342
From pwm_1/count_3_s0
To pwm_1/count_3_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C24[2][A] pwm_1/count_3_s0/CLK
1.675 0.333 tC2Q RR 3 R12C24[2][A] pwm_1/count_3_s0/Q
1.679 0.004 tNET RR 1 R12C24[2][A] pwm_1/n36_s2/I3
2.235 0.556 tINS RR 1 R12C24[2][A] pwm_1/n36_s2/F
2.235 0.000 tNET RR 1 R12C24[2][A] pwm_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C24[2][A] pwm_1/count_3_s0/CLK
1.342 0.000 tHld 1 R12C24[2][A] pwm_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path11

Path Summary:

Slack 0.893
Data Arrival Time 2.235
Data Required Time 1.342
From pwm_1/count_8_s0
To pwm_1/count_8_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C22[2][A] pwm_1/count_8_s0/CLK
1.675 0.333 tC2Q RR 6 R12C22[2][A] pwm_1/count_8_s0/Q
1.679 0.004 tNET RR 1 R12C22[2][A] pwm_1/n31_s2/I3
2.235 0.556 tINS RR 1 R12C22[2][A] pwm_1/n31_s2/F
2.235 0.000 tNET RR 1 R12C22[2][A] pwm_1/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C22[2][A] pwm_1/count_8_s0/CLK
1.342 0.000 tHld 1 R12C22[2][A] pwm_1/count_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path12

Path Summary:

Slack 0.894
Data Arrival Time 2.236
Data Required Time 1.342
From pwm_1/count_1_s0
To pwm_1/count_1_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C26[2][A] pwm_1/count_1_s0/CLK
1.675 0.333 tC2Q RR 5 R12C26[2][A] pwm_1/count_1_s0/Q
1.680 0.005 tNET RR 1 R12C26[2][A] pwm_1/n38_s2/I1
2.236 0.556 tINS RR 1 R12C26[2][A] pwm_1/n38_s2/F
2.236 0.000 tNET RR 1 R12C26[2][A] pwm_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C26[2][A] pwm_1/count_1_s0/CLK
1.342 0.000 tHld 1 R12C26[2][A] pwm_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.556, 62.189%; route: 0.005, 0.528%; tC2Q: 0.333, 37.283%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path13

Path Summary:

Slack 0.943
Data Arrival Time 2.519
Data Required Time 1.577
From clkdiv_1/count_8_s0
To clkdiv_1/clk_out_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C16[1][B] clkdiv_1/count_8_s0/CLK
1.910 0.333 tC2Q RR 3 R12C16[1][B] clkdiv_1/count_8_s0/Q
2.147 0.238 tNET RR 1 R12C16[2][B] clkdiv_1/n63_s89/I0
2.519 0.372 tINS RF 1 R12C16[2][B] clkdiv_1/n63_s89/F
2.519 0.000 tNET FF 1 R12C16[2][B] clkdiv_1/clk_out_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C16[2][B] clkdiv_1/clk_out_s0/CLK
1.577 0.000 tHld 1 R12C16[2][B] clkdiv_1/clk_out_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 39.452%; route: 0.238, 25.196%; tC2Q: 0.333, 35.352%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path14

Path Summary:

Slack 0.946
Data Arrival Time 2.523
Data Required Time 1.577
From clkdiv_1/count_4_s0
To clkdiv_1/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C17[1][A] clkdiv_1/count_4_s0/CLK
1.910 0.333 tC2Q RF 5 R12C17[1][A] clkdiv_1/count_4_s0/Q
2.151 0.241 tNET FF 1 R12C17[1][B] clkdiv_1/n56_s5/I1
2.523 0.372 tINS FF 1 R12C17[1][B] clkdiv_1/n56_s5/F
2.523 0.000 tNET FF 1 R12C17[1][B] clkdiv_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C17[1][B] clkdiv_1/count_5_s0/CLK
1.577 0.000 tHld 1 R12C17[1][B] clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 39.312%; route: 0.241, 25.462%; tC2Q: 0.333, 35.226%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path15

Path Summary:

Slack 0.980
Data Arrival Time 2.557
Data Required Time 1.577
From clkdiv_1/count_1_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C19[0][A] clkdiv_1/count_1_s0/CLK
1.910 0.333 tC2Q RR 6 R12C19[0][A] clkdiv_1/count_1_s0/Q
2.185 0.275 tNET RR 1 R12C17[0][B] clkdiv_1/n59_s5/I2
2.557 0.372 tINS RF 1 R12C17[0][B] clkdiv_1/n59_s5/F
2.557 0.000 tNET FF 1 R12C17[0][B] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C17[0][B] clkdiv_1/count_2_s0/CLK
1.577 0.000 tHld 1 R12C17[0][B] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 37.954%; route: 0.275, 28.036%; tC2Q: 0.333, 34.009%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path16

Path Summary:

Slack 1.061
Data Arrival Time 2.403
Data Required Time 1.342
From pwm_1/count_11_s0
To pwm_1/count_11_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C23[1][B] pwm_1/count_11_s0/CLK
1.675 0.333 tC2Q RR 5 R12C23[1][B] pwm_1/count_11_s0/Q
1.679 0.004 tNET RR 1 R12C23[1][B] pwm_1/n28_s2/I3
2.403 0.724 tINS RR 1 R12C23[1][B] pwm_1/n28_s2/F
2.403 0.000 tNET RR 1 R12C23[1][B] pwm_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C23[1][B] pwm_1/count_11_s0/CLK
1.342 0.000 tHld 1 R12C23[1][B] pwm_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path17

Path Summary:

Slack 1.061
Data Arrival Time 2.403
Data Required Time 1.342
From pwm_1/count_12_s0
To pwm_1/count_12_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C25[1][B] pwm_1/count_12_s0/CLK
1.675 0.333 tC2Q RR 3 R12C25[1][B] pwm_1/count_12_s0/Q
1.679 0.004 tNET RR 1 R12C25[1][B] pwm_1/n27_s2/I3
2.403 0.724 tINS RR 1 R12C25[1][B] pwm_1/n27_s2/F
2.403 0.000 tNET RR 1 R12C25[1][B] pwm_1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C25[1][B] pwm_1/count_12_s0/CLK
1.342 0.000 tHld 1 R12C25[1][B] pwm_1/count_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path18

Path Summary:

Slack 1.062
Data Arrival Time 2.403
Data Required Time 1.342
From pwm_1/count_7_s0
To pwm_1/count_7_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C22[2][B] pwm_1/count_7_s0/CLK
1.675 0.333 tC2Q RR 4 R12C22[2][B] pwm_1/count_7_s0/Q
1.677 0.002 tNET RR 1 R12C22[2][B] pwm_1/n32_s2/I3
2.403 0.726 tINS RR 1 R12C22[2][B] pwm_1/n32_s2/F
2.403 0.000 tNET RR 1 R12C22[2][B] pwm_1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C22[2][B] pwm_1/count_7_s0/CLK
1.342 0.000 tHld 1 R12C22[2][B] pwm_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.726, 68.381%; route: 0.002, 0.222%; tC2Q: 0.333, 31.396%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path19

Path Summary:

Slack 1.062
Data Arrival Time 2.403
Data Required Time 1.342
From pwm_1/count_14_s0
To pwm_1/count_14_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C23[2][B] pwm_1/count_14_s0/CLK
1.675 0.333 tC2Q RR 3 R12C23[2][B] pwm_1/count_14_s0/Q
1.677 0.002 tNET RR 1 R12C23[2][B] pwm_1/n25_s2/I3
2.403 0.726 tINS RR 1 R12C23[2][B] pwm_1/n25_s2/F
2.403 0.000 tNET RR 1 R12C23[2][B] pwm_1/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C23[2][B] pwm_1/count_14_s0/CLK
1.342 0.000 tHld 1 R12C23[2][B] pwm_1/count_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.726, 68.381%; route: 0.002, 0.222%; tC2Q: 0.333, 31.396%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path20

Path Summary:

Slack 1.062
Data Arrival Time 2.404
Data Required Time 1.342
From pwm_1/count_5_s0
To pwm_1/count_5_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C21[0][B] pwm_1/count_5_s0/CLK
1.675 0.333 tC2Q RR 6 R12C21[0][B] pwm_1/count_5_s0/Q
1.680 0.005 tNET RR 1 R12C21[0][B] pwm_1/n34_s2/I3
2.404 0.724 tINS RR 1 R12C21[0][B] pwm_1/n34_s2/F
2.404 0.000 tNET RR 1 R12C21[0][B] pwm_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C21[0][B] pwm_1/count_5_s0/CLK
1.342 0.000 tHld 1 R12C21[0][B] pwm_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.724, 68.170%; route: 0.005, 0.445%; tC2Q: 0.333, 31.386%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path21

Path Summary:

Slack 1.065
Data Arrival Time 2.407
Data Required Time 1.342
From pwm_1/count_0_s0
To pwm_1/count_0_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
1.675 0.333 tC2Q RR 6 R12C21[2][B] pwm_1/count_0_s0/Q
1.681 0.006 tNET RR 1 R12C21[2][B] pwm_1/n39_s2/I0
2.407 0.726 tINS RR 1 R12C21[2][B] pwm_1/n39_s2/F
2.407 0.000 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C21[2][B] pwm_1/count_0_s0/CLK
1.342 0.000 tHld 1 R12C21[2][B] pwm_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.726, 68.154%; route: 0.006, 0.554%; tC2Q: 0.333, 31.292%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path22

Path Summary:

Slack 1.164
Data Arrival Time 2.506
Data Required Time 1.342
From pwm_1/count_8_s0
To pwm_1/tc_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C22[2][A] pwm_1/count_8_s0/CLK
1.675 0.333 tC2Q RR 6 R12C22[2][A] pwm_1/count_8_s0/Q
1.950 0.275 tNET RR 1 R12C24[1][A] pwm_1/n43_s51/I0
2.506 0.556 tINS RR 1 R12C24[1][A] pwm_1/n43_s51/F
2.506 0.000 tNET RR 1 R12C24[1][A] pwm_1/tc_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C24[1][A] pwm_1/tc_s0/CLK
1.342 0.000 tHld 1 R12C24[1][A] pwm_1/tc_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.556, 47.761%; route: 0.275, 23.605%; tC2Q: 0.333, 28.634%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path23

Path Summary:

Slack 1.305
Data Arrival Time 2.647
Data Required Time 1.342
From pwm_1/count_9_s0
To pwm_1/count_9_s0
Launch Clk clk100khz:[R]
Latch Clk clk100khz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C22[1][B] pwm_1/count_9_s0/CLK
1.675 0.333 tC2Q RR 7 R12C22[1][B] pwm_1/count_9_s0/Q
1.921 0.246 tNET RR 1 R12C22[1][B] pwm_1/n30_s2/I1
2.647 0.726 tINS RR 1 R12C22[1][B] pwm_1/n30_s2/F
2.647 0.000 tNET RR 1 R12C22[1][B] pwm_1/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk100khz
0.000 0.000 tCL RR 18 R12C16[2][B] clkdiv_1/clk_out_s0/Q
1.342 1.342 tNET RR 1 R12C22[1][B] pwm_1/count_9_s0/CLK
1.342 0.000 tHld 1 R12C22[1][B] pwm_1/count_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%
Arrival Data Path Delay cell: 0.726, 55.612%; route: 0.246, 18.855%; tC2Q: 0.333, 25.533%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.342, 100.000%

Path24

Path Summary:

Slack 1.778
Data Arrival Time 3.355
Data Required Time 1.577
From clkdiv_1/count_5_s0
To clkdiv_1/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C17[1][B] clkdiv_1/count_5_s0/CLK
1.910 0.333 tC2Q RR 4 R12C17[1][B] clkdiv_1/count_5_s0/Q
2.149 0.239 tNET RR 1 R12C17[0][A] clkdiv_1/n55_s5/I2
2.751 0.602 tINS RF 1 R12C17[0][A] clkdiv_1/n55_s5/F
2.983 0.232 tNET FF 1 R12C16[0][B] clkdiv_1/n55_s6/I1
3.355 0.372 tINS FF 1 R12C16[0][B] clkdiv_1/n55_s6/F
3.355 0.000 tNET FF 1 R12C16[0][B] clkdiv_1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C16[0][B] clkdiv_1/count_6_s0/CLK
1.577 0.000 tHld 1 R12C16[0][B] clkdiv_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.974, 54.765%; route: 0.471, 26.492%; tC2Q: 0.333, 18.742%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path25

Path Summary:

Slack 2.187
Data Arrival Time 3.763
Data Required Time 1.577
From clkdiv_1/count_4_s0
To clkdiv_1/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C17[1][A] clkdiv_1/count_4_s0/CLK
1.910 0.333 tC2Q RF 5 R12C17[1][A] clkdiv_1/count_4_s0/Q
2.158 0.248 tNET FF 1 R12C18[0][A] clkdiv_1/n63_s84/I0
2.530 0.372 tINS FF 2 R12C18[0][A] clkdiv_1/n63_s84/F
2.539 0.009 tNET FF 1 R12C18[3][A] clkdiv_1/n61_s4/I2
2.924 0.385 tINS FR 9 R12C18[3][A] clkdiv_1/n61_s4/F
3.207 0.284 tNET RR 1 R12C16[1][A] clkdiv_1/n58_s5/I0
3.763 0.556 tINS RR 1 R12C16[1][A] clkdiv_1/n58_s5/F
3.763 0.000 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 15 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R12C16[1][A] clkdiv_1/count_3_s0/CLK
1.577 0.000 tHld 1 R12C16[1][A] clkdiv_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 4
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 1.313, 60.048%; route: 0.540, 24.707%; tC2Q: 0.333, 15.245%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: compare_7_s1

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF compare_7_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR compare_7_s1/CLK

MPW2

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: compare_2_s1

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF compare_2_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR compare_2_s1/CLK

MPW3

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_7_s0/CLK

MPW4

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/clk_out_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/clk_out_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/clk_out_s0/CLK

MPW5

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_0_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_0_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_0_s0/CLK

MPW6

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_8_s0/CLK

MPW7

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_1_s0/CLK

MPW8

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_2_s0/CLK

MPW9

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: compare_4_s1

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF compare_4_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR compare_4_s1/CLK

MPW10

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: compare_6_s1

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF compare_6_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR compare_6_s1/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
18 clk100khz 9988.065 2.023
16 tc 9997.175 0.857
15 clk_d 31.543 0.262
9 n35_7 9993.216 1.335
9 n61_8 32.037 0.519
7 count[9] 9992.710 1.309
7 count[0] 32.184 0.847
7 count[4] 9988.402 1.472
6 count[10] 9992.906 0.824
6 count[8] 9992.003 1.321

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R12C16 77.78%
R12C21 61.11%
R12C24 58.33%
R12C22 55.56%
R12C23 54.17%
R12C17 47.22%
R12C31 45.83%
R12C26 41.67%
R12C25 33.33%
R12C27 30.56%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk100khz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 270 [get_nets {clk100khz}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk27mhz}] -to [get_clocks {clk100khz}]