PnR Messages

Report Title PnR Report
Design File C:\Gowin\SV_240812_mhut_2001\organ\impl\gwsynthesis\organ.vg
Physical Constraints File C:\Gowin\SV_240812_mhut_2001\organ\src\organ.cst
Timing Constraints File C:\Gowin\SV_240812_mhut_2001\organ\src\organ.sdc
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Aug 12 11:43:08 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.013s, Elapsed time = 0h 0m 0.012s Placement Phase 1: CPU time = 0h 0m 0.061s, Elapsed time = 0h 0m 0.061s Placement Phase 2: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.005s Placement Phase 3: CPU time = 0h 0m 0.737s, Elapsed time = 0h 0m 0.737s Total Placement: CPU time = 0h 0m 0.816s, Elapsed time = 0h 0m 0.815s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.109s Routing Phase 2: CPU time = 0h 0m 0.099s, Elapsed time = 0h 0m 0.099s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.208s, Elapsed time = 0h 0m 0.208s Generate output files: CPU time = 0h 0m 0.658s, Elapsed time = 0h 0m 0.658s
Total Time and Memory Usage CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s, Peak memory usage = 260MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 201/8640 3%
    --LUT,ALU,ROM16 201(165 LUT, 36 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 80/6693 2%
    --Logic Register as Latch 0/6480 0%
    --Logic Register as FF 75/6480 2%
    --I/O Register as Latch 0/213 0%
    --I/O Register as FF 5/213 3%
CLS 124/4320 3%
I/O Port 24 -
I/O Buf 24 -
    --Input Buf 6 -
    --Output Buf 18 -
    --Inout Buf 0 -
IOLOGIC 0 0%
BSRAM 0 0%
DSP 00%
PLL 0/2 0%
DCS 0/8 0%
DQCE 0/24 0%
OSC 0/1 0%
User Flash 0/1 0%
CLKDIV 0/8 0%
DLLDLY 0/8 0%
DHCEN 0/8 0%
DHCENC 0/4 0%

I/O Bank Usage Summary:

I/O Bank Usage
bank 1 8/25(32%)
bank 2 16/23(69%)
bank 3 0/23(0%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 2/8(25%)
LW 1/8(13%)
GCLK_PIN 2/3(67%)
PLL 0/2(0%)
CLKDIV 0/8(0%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
clk_d PRIMARY BR BL
clk50hz PRIMARY TR BR BL
nrst_d LW -

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
nrst 73/1 Y in IOT39[A] LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
clk 52/1 Y in IOR17[A] LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
row[0] 25/2 Y in IOB8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
row[1] 26/2 Y in IOB8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
row[2] 27/2 Y in IOB11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
row[3] 28/2 Y in IOB11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
col[0] 38/2 Y out IOB31[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
col[1] 37/2 Y out IOB31[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
col[2] 36/2 Y out IOB29[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
col[3] 39/2 Y out IOB33[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
bz 49/1 Y out IOR24[A] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
seg[0] 42/2 Y out IOB41[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
seg[1] 41/2 Y out IOB41[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
seg[2] 35/2 Y out IOB29[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
seg[3] 40/2 Y out IOB33[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
seg[4] 34/2 Y out IOB23[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
seg[5] 33/2 Y out IOB23[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
seg[6] 30/2 Y out IOB13[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
seg[7] 29/2 Y out IOB13[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
dig[0] 74/1 Y out IOT38[B] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
dig[1] 75/1 Y out IOT38[A] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
dig[2] 76/1 Y out IOT37[B] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
dig[3] 77/1 Y out IOT37[A] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
ready 69/1 Y out IOT42[A] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/3 - in IOT2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
88/3 - in IOT5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
87/3 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
86/3 - in IOT8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
85/3 - in IOT8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
84/3 - in IOT10[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
83/3 - in IOT10[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
82/3 - in IOT11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
81/3 - in IOT11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
80/3 - in IOT12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
79/3 - in IOT12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
77/1 dig[3] out IOT37[A] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
76/1 dig[2] out IOT37[B] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
75/1 dig[1] out IOT38[A] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
74/1 dig[0] out IOT38[B] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
73/1 nrst in IOT39[A] LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
72/1 - in IOT39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
71/1 - in IOT41[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
70/1 - in IOT41[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
69/1 ready out IOT42[A] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
68/1 - in IOT42[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/2 - in IOB2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
18/2 - in IOB2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/2 - in IOB4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
20/2 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
25/2 row[0] in IOB8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
26/2 row[1] in IOB8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
27/2 row[2] in IOB11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
28/2 row[3] in IOB11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
29/2 seg[7] out IOB13[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
30/2 seg[6] out IOB13[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
31/2 - in IOB15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
32/2 - in IOB15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
33/2 seg[5] out IOB23[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
34/2 seg[4] out IOB23[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
35/2 seg[2] out IOB29[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
36/2 col[2] out IOB29[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
37/2 col[1] out IOB31[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
38/2 col[0] out IOB31[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
39/2 col[3] out IOB33[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
40/2 seg[3] out IOB33[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
41/2 seg[1] out IOB41[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
42/2 seg[0] out IOB41[B] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
47/2 - in IOB43[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
4/3 - in IOL5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
5/3 - in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
6/3 - in IOL11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/3 - in IOL12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/3 - out IOL13[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
9/3 - in IOL13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/3 - in IOL15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
11/3 - in IOL16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/3 - in IOL21[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/3 - in IOL22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 - in IOL25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
16/3 - in IOL26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
63/1 - in IOR5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
62/1 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
61/1 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
60/1 - in IOR12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
59/1 - in IOR12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
57/1 - in IOR13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
56/1 - in IOR14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
55/1 - in IOR14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
54/1 - in IOR15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
53/1 - in IOR15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
52/1 clk in IOR17[A] LVCMOS18 NA UP ON NONE NA NA OFF NA 1.8
51/1 - in IOR17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
50/1 - in IOR22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
49/1 bz out IOR24[A] LVCMOS18 8 UP NA NA OFF NA OFF NA 1.8
48/1 - in IOR24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8