Timing Messages
Report Title | Timing Analysis Report |
Design File | C:\Gowin\SV_240812_mhut_2001\stopwatchB\impl\gwsynthesis\stopwatchB.vg |
Physical Constraints File | C:\Gowin\SV_240812_mhut_2001\stopwatchB\src\stopwatch.cst |
Timing Constraint File | C:\Gowin\SV_240812_mhut_2001\stopwatchB\src\stopwatchB.sdc |
Tool Version | V1.9.10.01 (64-bit) |
Part Number | GW1NR-LV9QN88PC6/I5 |
Device | GW1NR-9 |
Device Version | C |
Created Time | Mon Aug 12 11:54:45 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C C6/I5 |
Hold Delay Model | Fast 1.26V 0C C6/I5 |
Numbers of Paths Analyzed | 303 |
Numbers of Endpoints Analyzed | 255 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | clk27mhz | Base | 37.037 | 27.000 | 0.000 | 18.518 | clk | ||
2 | clk160hz | Generated | 9999990.000 | 0.000 | 0.000 | 4999995.000 | clk | clk27mhz | clk160hz |
3 | clk400hz | Generated | 2499997.500 | 0.000 | 0.000 | 1249998.750 | clk | clk27mhz | clk400hz |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk27mhz | 27.000(MHz) | 115.903(MHz) | 4 | TOP |
2 | clk160hz | 0.000(MHz) | 166.666(MHz) | 2 | TOP |
3 | clk400hz | 0.000(MHz) | 190.476(MHz) | 2 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk27mhz | Setup | 0.000 | 0 |
clk27mhz | Hold | 0.000 | 0 |
clk160hz | Setup | 0.000 | 0 |
clk160hz | Hold | 0.000 | 0 |
clk400hz | Setup | 0.000 | 0 |
clk400hz | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 28.409 | run_led_1/count_1_s0/Q | run_led_1/led_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.228 |
2 | 28.473 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.164 |
3 | 28.473 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.164 |
4 | 28.823 | clkdiv_2/count_7_s0/Q | clkdiv_2/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.814 |
5 | 28.836 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.801 |
6 | 28.881 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.756 |
7 | 28.940 | run_led_1/count_1_s0/Q | run_led_1/led_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.697 |
8 | 28.968 | clkdiv_1/count_1_s0/Q | clkdiv_1/tc_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.669 |
9 | 29.051 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.586 |
10 | 29.079 | run_led_1/count_1_s0/Q | run_led_1/led_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.558 |
11 | 29.100 | clkdiv_2/count_7_s0/Q | clkdiv_2/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.537 |
12 | 29.159 | toggle_2/out_s0/Q | cntr4max_3/cnt_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.478 |
13 | 29.159 | toggle_2/out_s0/Q | cntr4max_3/cnt_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.478 |
14 | 29.159 | toggle_2/out_s0/Q | cntr4max_3/cnt_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.478 |
15 | 29.256 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.381 |
16 | 29.256 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.381 |
17 | 29.303 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.334 |
18 | 29.303 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.334 |
19 | 29.370 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.267 |
20 | 29.370 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.267 |
21 | 29.382 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_18_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.255 |
22 | 29.427 | clkdiv_3/count_9_s0/Q | clkdiv_3/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.210 |
23 | 29.447 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.190 |
24 | 29.479 | run_led_1/count_1_s0/Q | run_led_1/led_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.158 |
25 | 29.732 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.905 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.708 | clkdiv_3/count_15_s0/Q | clkdiv_3/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
2 | 0.708 | clkdiv_3/count_17_s0/Q | clkdiv_3/count_17_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
3 | 0.708 | clkdiv_1/count_2_s0/Q | clkdiv_1/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
4 | 0.708 | clkdiv_1/count_12_s0/Q | clkdiv_1/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
5 | 0.709 | toggle_2/out_s0/Q | toggle_2/out_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
6 | 0.709 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
7 | 0.709 | clkdiv_3/count_8_s0/Q | clkdiv_3/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
8 | 0.709 | clkdiv_2/count_2_s0/Q | clkdiv_2/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
9 | 0.709 | clkdiv_2/count_3_s0/Q | clkdiv_2/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
10 | 0.709 | clkdiv_2/count_6_s0/Q | clkdiv_2/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
11 | 0.709 | clkdiv_2/count_11_s0/Q | clkdiv_2/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
12 | 0.709 | clkdiv_1/count_9_s0/Q | clkdiv_1/count_9_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
13 | 0.709 | clkdiv_1/count_10_s0/Q | clkdiv_1/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
14 | 0.709 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
15 | 0.709 | clkdiv_1/count_18_s0/Q | clkdiv_1/count_18_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
16 | 0.710 | run_led_1/count_1_s0/Q | run_led_1/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
17 | 0.710 | clkdiv_3/count_10_s0/Q | clkdiv_3/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
18 | 0.710 | clkdiv_3/count_11_s0/Q | clkdiv_3/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
19 | 0.710 | clkdiv_3/count_13_s0/Q | clkdiv_3/count_13_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
20 | 0.710 | clkdiv_2/count_1_s0/Q | clkdiv_2/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
21 | 0.710 | clkdiv_1/count_15_s0/Q | clkdiv_1/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
22 | 0.711 | inst20/col_0_s0/Q | inst20/col_0_s0/D | clk160hz:[R] | clk160hz:[R] | 0.000 | 0.000 | 0.711 |
23 | 0.711 | run_led_1/count_0_s0/Q | run_led_1/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.711 |
24 | 0.711 | cntr4max_3/cnt_2_s0/Q | cntr4max_3/cnt_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.711 |
25 | 0.711 | cntr4max_2/cnt_0_s1/Q | cntr4max_2/cnt_0_s1/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.711 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_18_s0 |
2 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_16_s0 |
3 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_12_s0 |
4 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_4_s0 |
5 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_2/count_6_s0 |
6 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_0_s1 |
7 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_3_s0 |
8 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_2/count_7_s0 |
9 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_1_s0 |
10 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_2_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 28.409 |
Data Arrival Time | 10.560 |
Data Required Time | 38.969 |
From | run_led_1/count_1_s0 |
To | run_led_1/led_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R14C29[1][A] | run_led_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 16 | R14C29[1][A] | run_led_1/count_1_s0/Q |
3.689 | 0.899 | tNET | FF | 1 | R15C28[3][A] | run_led_1/n18_s5/I0 |
4.788 | 1.099 | tINS | FF | 2 | R15C28[3][A] | run_led_1/n18_s5/F |
5.614 | 0.825 | tNET | FF | 1 | R16C28[2][A] | run_led_1/n50_s6/I2 |
6.646 | 1.032 | tINS | FF | 1 | R16C28[2][A] | run_led_1/n50_s6/F |
6.651 | 0.005 | tNET | FF | 1 | R16C28[2][B] | run_led_1/n50_s5/I0 |
7.473 | 0.822 | tINS | FF | 1 | R16C28[2][B] | run_led_1/n50_s5/F |
10.560 | 3.086 | tNET | FF | 1 | IOT42[B] | run_led_1/led_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | IOT42[B] | run_led_1/led_1_s0/CLK |
38.969 | -0.400 | tSu | 1 | IOT42[B] | run_led_1/led_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 2.953, 35.890%; route: 4.817, 58.539%; tC2Q: 0.458, 5.571% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path2
Path Summary:
Slack | 28.473 |
Data Arrival Time | 10.496 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
9.397 | 1.376 | tNET | FF | 1 | R13C24[1][A] | clkdiv_1/n51_s2/I0 |
10.496 | 1.099 | tINS | FF | 1 | R13C24[1][A] | clkdiv_1/n51_s2/F |
10.496 | 0.000 | tNET | FF | 1 | R13C24[1][A] | clkdiv_1/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C24[1][A] | clkdiv_1/count_10_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C24[1][A] | clkdiv_1/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.329, 53.025%; route: 3.377, 41.361%; tC2Q: 0.458, 5.614% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path3
Path Summary:
Slack | 28.473 |
Data Arrival Time | 10.496 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_12_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
9.397 | 1.376 | tNET | FF | 1 | R13C24[0][A] | clkdiv_1/n49_s2/I2 |
10.496 | 1.099 | tINS | FF | 1 | R13C24[0][A] | clkdiv_1/n49_s2/F |
10.496 | 0.000 | tNET | FF | 1 | R13C24[0][A] | clkdiv_1/count_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C24[0][A] | clkdiv_1/count_12_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C24[0][A] | clkdiv_1/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.329, 53.025%; route: 3.377, 41.361%; tC2Q: 0.458, 5.614% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path4
Path Summary:
Slack | 28.823 |
Data Arrival Time | 10.146 |
Data Required Time | 38.969 |
From | clkdiv_2/count_7_s0 |
To | clkdiv_2/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C26[1][B] | clkdiv_2/count_7_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R15C26[1][B] | clkdiv_2/count_7_s0/Q |
3.606 | 0.815 | tNET | FF | 1 | R14C27[3][A] | clkdiv_2/n50_s3/I0 |
4.428 | 0.822 | tINS | FF | 3 | R14C27[3][A] | clkdiv_2/n50_s3/F |
5.254 | 0.826 | tNET | FF | 1 | R14C26[2][A] | clkdiv_2/n49_s3/I1 |
6.286 | 1.032 | tINS | FF | 4 | R14C26[2][A] | clkdiv_2/n49_s3/F |
7.590 | 1.304 | tNET | FF | 1 | R14C27[1][B] | clkdiv_2/n46_s3/I3 |
8.216 | 0.626 | tINS | FF | 2 | R14C27[1][B] | clkdiv_2/n46_s3/F |
9.047 | 0.831 | tNET | FF | 1 | R15C27[2][A] | clkdiv_2/n46_s2/I2 |
10.146 | 1.099 | tINS | FF | 1 | R15C27[2][A] | clkdiv_2/n46_s2/F |
10.146 | 0.000 | tNET | FF | 1 | R15C27[2][A] | clkdiv_2/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C27[2][A] | clkdiv_2/count_15_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C27[2][A] | clkdiv_2/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.579, 45.802%; route: 3.777, 48.332%; tC2Q: 0.458, 5.866% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path5
Path Summary:
Slack | 28.836 |
Data Arrival Time | 10.133 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_7_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
9.034 | 1.013 | tNET | FF | 1 | R13C24[2][B] | clkdiv_1/n54_s2/I0 |
10.133 | 1.099 | tINS | FF | 1 | R13C24[2][B] | clkdiv_1/n54_s2/F |
10.133 | 0.000 | tNET | FF | 1 | R13C24[2][B] | clkdiv_1/count_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C24[2][B] | clkdiv_1/count_7_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C24[2][B] | clkdiv_1/count_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.329, 55.495%; route: 3.013, 38.630%; tC2Q: 0.458, 5.876% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path6
Path Summary:
Slack | 28.881 |
Data Arrival Time | 10.088 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_11_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
9.056 | 1.036 | tNET | FF | 1 | R13C24[0][B] | clkdiv_1/n50_s2/I2 |
10.088 | 1.032 | tINS | FF | 1 | R13C24[0][B] | clkdiv_1/n50_s2/F |
10.088 | 0.000 | tNET | FF | 1 | R13C24[0][B] | clkdiv_1/count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C24[0][B] | clkdiv_1/count_11_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C24[0][B] | clkdiv_1/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.262, 54.947%; route: 3.036, 39.143%; tC2Q: 0.458, 5.909% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path7
Path Summary:
Slack | 28.940 |
Data Arrival Time | 10.029 |
Data Required Time | 38.969 |
From | run_led_1/count_1_s0 |
To | run_led_1/led_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R14C29[1][A] | run_led_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 16 | R14C29[1][A] | run_led_1/count_1_s0/Q |
3.689 | 0.899 | tNET | FF | 1 | R15C28[1][A] | run_led_1/n17_s5/I2 |
4.788 | 1.099 | tINS | FF | 2 | R15C28[1][A] | run_led_1/n17_s5/F |
5.614 | 0.825 | tNET | FF | 1 | R16C28[0][A] | run_led_1/n49_s6/I3 |
6.646 | 1.032 | tINS | FF | 1 | R16C28[0][A] | run_led_1/n49_s6/F |
6.651 | 0.005 | tNET | FF | 1 | R16C28[0][B] | run_led_1/n49_s5/I0 |
7.277 | 0.626 | tINS | FF | 1 | R16C28[0][B] | run_led_1/n49_s5/F |
10.029 | 2.752 | tNET | FF | 1 | IOR13[A] | run_led_1/led_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | IOR13[A] | run_led_1/led_2_s0/CLK |
38.969 | -0.400 | tSu | 1 | IOR13[A] | run_led_1/led_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 2.757, 35.819%; route: 4.482, 58.226%; tC2Q: 0.458, 5.955% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path8
Path Summary:
Slack | 28.968 |
Data Arrival Time | 10.001 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/tc_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
10.001 | 1.980 | tNET | FF | 1 | R14C28[0][A] | clkdiv_1/tc_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C28[0][A] | clkdiv_1/tc_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C28[0][A] | clkdiv_1/tc_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.230, 42.117%; route: 3.981, 51.907%; tC2Q: 0.458, 5.976% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path9
Path Summary:
Slack | 29.051 |
Data Arrival Time | 9.918 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_4_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
8.886 | 0.865 | tNET | FF | 1 | R14C25[1][B] | clkdiv_1/n57_s2/I0 |
9.918 | 1.032 | tINS | FF | 1 | R14C25[1][B] | clkdiv_1/n57_s2/F |
9.918 | 0.000 | tNET | FF | 1 | R14C25[1][B] | clkdiv_1/count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C25[1][B] | clkdiv_1/count_4_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C25[1][B] | clkdiv_1/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.262, 56.182%; route: 2.866, 37.776%; tC2Q: 0.458, 6.042% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path10
Path Summary:
Slack | 29.079 |
Data Arrival Time | 9.890 |
Data Required Time | 38.969 |
From | run_led_1/count_1_s0 |
To | run_led_1/led_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R14C29[1][A] | run_led_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 16 | R14C29[1][A] | run_led_1/count_1_s0/Q |
3.689 | 0.899 | tNET | FF | 1 | R15C28[3][A] | run_led_1/n18_s5/I0 |
4.788 | 1.099 | tINS | FF | 2 | R15C28[3][A] | run_led_1/n18_s5/F |
5.614 | 0.825 | tNET | FF | 1 | R16C28[3][A] | run_led_1/n45_s6/I2 |
6.646 | 1.032 | tINS | FF | 1 | R16C28[3][A] | run_led_1/n45_s6/F |
6.651 | 0.005 | tNET | FF | 1 | R16C28[3][B] | run_led_1/n45_s5/I0 |
7.473 | 0.822 | tINS | FF | 1 | R16C28[3][B] | run_led_1/n45_s5/F |
9.890 | 2.417 | tNET | FF | 1 | IOR15[B] | run_led_1/led_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | IOR15[B] | run_led_1/led_6_s0/CLK |
38.969 | -0.400 | tSu | 1 | IOR15[B] | run_led_1/led_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 2.953, 39.070%; route: 4.147, 54.866%; tC2Q: 0.458, 6.064% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path11
Path Summary:
Slack | 29.100 |
Data Arrival Time | 9.869 |
Data Required Time | 38.969 |
From | clkdiv_2/count_7_s0 |
To | clkdiv_2/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C26[1][B] | clkdiv_2/count_7_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R15C26[1][B] | clkdiv_2/count_7_s0/Q |
3.606 | 0.815 | tNET | FF | 1 | R14C27[3][A] | clkdiv_2/n50_s3/I0 |
4.428 | 0.822 | tINS | FF | 3 | R14C27[3][A] | clkdiv_2/n50_s3/F |
5.254 | 0.826 | tNET | FF | 1 | R14C26[2][A] | clkdiv_2/n49_s3/I1 |
6.286 | 1.032 | tINS | FF | 4 | R14C26[2][A] | clkdiv_2/n49_s3/F |
7.590 | 1.304 | tNET | FF | 1 | R14C27[1][B] | clkdiv_2/n46_s3/I3 |
8.216 | 0.626 | tINS | FF | 2 | R14C27[1][B] | clkdiv_2/n46_s3/F |
9.047 | 0.831 | tNET | FF | 1 | R15C27[2][B] | clkdiv_2/n45_s2/I1 |
9.869 | 0.822 | tINS | FF | 1 | R15C27[2][B] | clkdiv_2/n45_s2/F |
9.869 | 0.000 | tNET | FF | 1 | R15C27[2][B] | clkdiv_2/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C27[2][B] | clkdiv_2/count_16_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C27[2][B] | clkdiv_2/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.302, 43.810%; route: 3.777, 50.108%; tC2Q: 0.458, 6.081% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path12
Path Summary:
Slack | 29.159 |
Data Arrival Time | 9.810 |
Data Required Time | 38.969 |
From | toggle_2/out_s0 |
To | cntr4max_3/cnt_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C27[0][A] | toggle_2/out_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 5 | R15C27[0][A] | toggle_2/out_s0/Q |
4.091 | 1.300 | tNET | FF | 1 | R14C30[2][B] | cntr4maxe_1/clk10hz_s1/I0 |
5.190 | 1.099 | tINS | FF | 4 | R14C30[2][B] | cntr4maxe_1/clk10hz_s1/F |
6.181 | 0.991 | tNET | FF | 1 | R13C32[2][B] | cntr4max_2/clk10s_s/I1 |
7.213 | 1.032 | tINS | FF | 10 | R13C32[2][B] | cntr4max_2/clk10s_s/F |
7.729 | 0.517 | tNET | FF | 1 | R13C34[2][B] | cntr4max_3/n19_s4/I3 |
8.761 | 1.032 | tINS | FF | 3 | R13C34[2][B] | cntr4max_3/n19_s4/F |
8.778 | 0.016 | tNET | FF | 1 | R13C34[1][B] | cntr4max_3/n19_s3/I1 |
9.810 | 1.032 | tINS | FF | 1 | R13C34[1][B] | cntr4max_3/n19_s3/F |
9.810 | 0.000 | tNET | FF | 1 | R13C34[1][B] | cntr4max_3/cnt_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C34[1][B] | cntr4max_3/cnt_0_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C34[1][B] | cntr4max_3/cnt_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.195, 56.101%; route: 2.824, 37.770%; tC2Q: 0.458, 6.129% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path13
Path Summary:
Slack | 29.159 |
Data Arrival Time | 9.810 |
Data Required Time | 38.969 |
From | toggle_2/out_s0 |
To | cntr4max_3/cnt_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C27[0][A] | toggle_2/out_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 5 | R15C27[0][A] | toggle_2/out_s0/Q |
4.091 | 1.300 | tNET | FF | 1 | R14C30[2][B] | cntr4maxe_1/clk10hz_s1/I0 |
5.190 | 1.099 | tINS | FF | 4 | R14C30[2][B] | cntr4maxe_1/clk10hz_s1/F |
6.181 | 0.991 | tNET | FF | 1 | R13C32[2][B] | cntr4max_2/clk10s_s/I1 |
7.213 | 1.032 | tINS | FF | 10 | R13C32[2][B] | cntr4max_2/clk10s_s/F |
7.729 | 0.517 | tNET | FF | 1 | R13C34[2][B] | cntr4max_3/n19_s4/I3 |
8.761 | 1.032 | tINS | FF | 3 | R13C34[2][B] | cntr4max_3/n19_s4/F |
8.778 | 0.016 | tNET | FF | 1 | R13C34[1][A] | cntr4max_3/n18_s2/I0 |
9.810 | 1.032 | tINS | FF | 1 | R13C34[1][A] | cntr4max_3/n18_s2/F |
9.810 | 0.000 | tNET | FF | 1 | R13C34[1][A] | cntr4max_3/cnt_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C34[1][A] | cntr4max_3/cnt_1_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C34[1][A] | cntr4max_3/cnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.195, 56.101%; route: 2.824, 37.770%; tC2Q: 0.458, 6.129% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path14
Path Summary:
Slack | 29.159 |
Data Arrival Time | 9.810 |
Data Required Time | 38.969 |
From | toggle_2/out_s0 |
To | cntr4max_3/cnt_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C27[0][A] | toggle_2/out_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 5 | R15C27[0][A] | toggle_2/out_s0/Q |
4.091 | 1.300 | tNET | FF | 1 | R14C30[2][B] | cntr4maxe_1/clk10hz_s1/I0 |
5.190 | 1.099 | tINS | FF | 4 | R14C30[2][B] | cntr4maxe_1/clk10hz_s1/F |
6.181 | 0.991 | tNET | FF | 1 | R13C32[2][B] | cntr4max_2/clk10s_s/I1 |
7.213 | 1.032 | tINS | FF | 10 | R13C32[2][B] | cntr4max_2/clk10s_s/F |
7.729 | 0.517 | tNET | FF | 1 | R13C34[2][B] | cntr4max_3/n19_s4/I3 |
8.761 | 1.032 | tINS | FF | 3 | R13C34[2][B] | cntr4max_3/n19_s4/F |
8.778 | 0.016 | tNET | FF | 1 | R13C34[0][A] | cntr4max_3/n17_s4/I0 |
9.810 | 1.032 | tINS | FF | 1 | R13C34[0][A] | cntr4max_3/n17_s4/F |
9.810 | 0.000 | tNET | FF | 1 | R13C34[0][A] | cntr4max_3/cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C34[0][A] | cntr4max_3/cnt_2_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C34[0][A] | cntr4max_3/cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.195, 56.101%; route: 2.824, 37.770%; tC2Q: 0.458, 6.129% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path15
Path Summary:
Slack | 29.256 |
Data Arrival Time | 9.713 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
8.891 | 0.870 | tNET | FF | 1 | R14C24[1][A] | clkdiv_1/n55_s2/I2 |
9.713 | 0.822 | tINS | FF | 1 | R14C24[1][A] | clkdiv_1/n55_s2/F |
9.713 | 0.000 | tNET | FF | 1 | R14C24[1][A] | clkdiv_1/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C24[1][A] | clkdiv_1/count_6_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C24[1][A] | clkdiv_1/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.052, 54.900%; route: 2.870, 38.890%; tC2Q: 0.458, 6.210% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path16
Path Summary:
Slack | 29.256 |
Data Arrival Time | 9.713 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
8.891 | 0.870 | tNET | FF | 1 | R14C24[1][B] | clkdiv_1/n53_s2/I2 |
9.713 | 0.822 | tINS | FF | 1 | R14C24[1][B] | clkdiv_1/n53_s2/F |
9.713 | 0.000 | tNET | FF | 1 | R14C24[1][B] | clkdiv_1/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C24[1][B] | clkdiv_1/count_8_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C24[1][B] | clkdiv_1/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.052, 54.900%; route: 2.870, 38.890%; tC2Q: 0.458, 6.210% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path17
Path Summary:
Slack | 29.303 |
Data Arrival Time | 9.666 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
8.567 | 0.547 | tNET | FF | 1 | R13C25[2][B] | clkdiv_1/n61_s2/I1 |
9.666 | 1.099 | tINS | FF | 1 | R13C25[2][B] | clkdiv_1/n61_s2/F |
9.666 | 0.000 | tNET | FF | 1 | R13C25[2][B] | clkdiv_1/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C25[2][B] | clkdiv_1/count_0_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C25[2][B] | clkdiv_1/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.329, 59.023%; route: 2.547, 34.728%; tC2Q: 0.458, 6.249% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path18
Path Summary:
Slack | 29.303 |
Data Arrival Time | 9.666 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
8.567 | 0.547 | tNET | FF | 1 | R13C25[2][A] | clkdiv_1/n60_s2/I0 |
9.666 | 1.099 | tINS | FF | 1 | R13C25[2][A] | clkdiv_1/n60_s2/F |
9.666 | 0.000 | tNET | FF | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C25[2][A] | clkdiv_1/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.329, 59.023%; route: 2.547, 34.728%; tC2Q: 0.458, 6.249% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path19
Path Summary:
Slack | 29.370 |
Data Arrival Time | 9.599 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
8.567 | 0.547 | tNET | FF | 1 | R13C25[1][A] | clkdiv_1/n59_s4/I0 |
9.599 | 1.032 | tINS | FF | 1 | R13C25[1][A] | clkdiv_1/n59_s4/F |
9.599 | 0.000 | tNET | FF | 1 | R13C25[1][A] | clkdiv_1/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/count_2_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C25[1][A] | clkdiv_1/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.262, 58.646%; route: 2.547, 35.048%; tC2Q: 0.458, 6.307% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path20
Path Summary:
Slack | 29.370 |
Data Arrival Time | 9.599 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
8.021 | 1.099 | tINS | FF | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
8.567 | 0.547 | tNET | FF | 1 | R13C25[1][B] | clkdiv_1/n58_s2/I2 |
9.599 | 1.032 | tINS | FF | 1 | R13C25[1][B] | clkdiv_1/n58_s2/F |
9.599 | 0.000 | tNET | FF | 1 | R13C25[1][B] | clkdiv_1/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C25[1][B] | clkdiv_1/count_3_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C25[1][B] | clkdiv_1/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.262, 58.646%; route: 2.547, 35.048%; tC2Q: 0.458, 6.307% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path21
Path Summary:
Slack | 29.382 |
Data Arrival Time | 9.587 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_18_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[3][A] | clkdiv_1/n54_s4/I1 |
6.130 | 1.061 | tINS | FR | 6 | R15C24[3][A] | clkdiv_1/n54_s4/F |
6.562 | 0.433 | tNET | RR | 1 | R14C24[2][A] | clkdiv_1/n48_s4/I1 |
7.661 | 1.099 | tINS | RF | 3 | R14C24[2][A] | clkdiv_1/n48_s4/F |
8.488 | 0.827 | tNET | FF | 1 | R15C25[0][A] | clkdiv_1/n43_s2/I0 |
9.587 | 1.099 | tINS | FF | 1 | R15C25[0][A] | clkdiv_1/n43_s2/F |
9.587 | 0.000 | tNET | FF | 1 | R15C25[0][A] | clkdiv_1/count_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C25[0][A] | clkdiv_1/count_18_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C25[0][A] | clkdiv_1/count_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.358, 60.065%; route: 2.439, 33.618%; tC2Q: 0.458, 6.317% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path22
Path Summary:
Slack | 29.427 |
Data Arrival Time | 9.542 |
Data Required Time | 38.969 |
From | clkdiv_3/count_9_s0 |
To | clkdiv_3/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C21[2][B] | clkdiv_3/count_9_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C21[2][B] | clkdiv_3/count_9_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C21[2][A] | clkdiv_3/n51_s4/I1 |
4.242 | 1.099 | tINS | FF | 2 | R13C21[2][A] | clkdiv_3/n51_s4/F |
5.052 | 0.810 | tNET | FF | 1 | R14C22[2][B] | clkdiv_3/n48_s5/I3 |
6.151 | 1.099 | tINS | FF | 3 | R14C22[2][B] | clkdiv_3/n48_s5/F |
6.167 | 0.016 | tNET | FF | 1 | R14C22[1][B] | clkdiv_3/n46_s3/I3 |
7.199 | 1.032 | tINS | FF | 3 | R14C22[1][B] | clkdiv_3/n46_s3/F |
8.510 | 1.311 | tNET | FF | 1 | R16C23[1][A] | clkdiv_3/n46_s2/I1 |
9.542 | 1.032 | tINS | FF | 1 | R16C23[1][A] | clkdiv_3/n46_s2/F |
9.542 | 0.000 | tNET | FF | 1 | R16C23[1][A] | clkdiv_3/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R16C23[1][A] | clkdiv_3/count_15_s0/CLK |
38.969 | -0.400 | tSu | 1 | R16C23[1][A] | clkdiv_3/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.262, 59.109%; route: 2.490, 34.535%; tC2Q: 0.458, 6.357% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path23
Path Summary:
Slack | 29.447 |
Data Arrival Time | 9.522 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
7.983 | 1.061 | tINS | FR | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
8.423 | 0.440 | tNET | RR | 1 | R14C25[1][A] | clkdiv_1/n45_s2/I2 |
9.522 | 1.099 | tINS | RF | 1 | R14C25[1][A] | clkdiv_1/n45_s2/F |
9.522 | 0.000 | tNET | FF | 1 | R14C25[1][A] | clkdiv_1/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C25[1][A] | clkdiv_1/count_16_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C25[1][A] | clkdiv_1/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.291, 59.679%; route: 2.441, 33.946%; tC2Q: 0.458, 6.375% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path24
Path Summary:
Slack | 29.479 |
Data Arrival Time | 9.489 |
Data Required Time | 38.969 |
From | run_led_1/count_1_s0 |
To | run_led_1/led_5_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R14C29[1][A] | run_led_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 16 | R14C29[1][A] | run_led_1/count_1_s0/Q |
3.689 | 0.899 | tNET | FF | 1 | R15C28[2][B] | run_led_1/n14_s4/I0 |
4.788 | 1.099 | tINS | FF | 2 | R15C28[2][B] | run_led_1/n14_s4/F |
5.619 | 0.831 | tNET | FF | 1 | R16C28[1][A] | run_led_1/n46_s6/I2 |
6.441 | 0.822 | tINS | FF | 1 | R16C28[1][A] | run_led_1/n46_s6/F |
6.447 | 0.005 | tNET | FF | 1 | R16C28[1][B] | run_led_1/n46_s5/I0 |
7.073 | 0.626 | tINS | FF | 1 | R16C28[1][B] | run_led_1/n46_s5/F |
9.489 | 2.417 | tNET | FF | 1 | IOR15[A] | run_led_1/led_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | IOR15[A] | run_led_1/led_5_s0/CLK |
38.969 | -0.400 | tSu | 1 | IOR15[A] | run_led_1/led_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 2.547, 35.585%; route: 4.152, 58.011%; tC2Q: 0.458, 6.404% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path25
Path Summary:
Slack | 29.732 |
Data Arrival Time | 9.237 |
Data Required Time | 38.969 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C25[2][A] | clkdiv_1/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C25[2][A] | clkdiv_1/count_1_s0/Q |
3.143 | 0.353 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/n57_s3/I0 |
4.242 | 1.099 | tINS | FF | 5 | R13C25[0][A] | clkdiv_1/n57_s3/F |
5.069 | 0.827 | tNET | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/I0 |
6.101 | 1.032 | tINS | FF | 1 | R15C24[2][A] | clkdiv_1/n7_s80/F |
6.922 | 0.821 | tNET | FF | 1 | R15C25[3][B] | clkdiv_1/n7_s89/I2 |
7.983 | 1.061 | tINS | FR | 20 | R15C25[3][B] | clkdiv_1/n7_s89/F |
8.415 | 0.432 | tNET | RR | 1 | R16C25[0][A] | clkdiv_1/n46_s2/I0 |
9.237 | 0.822 | tINS | RF | 1 | R16C25[0][A] | clkdiv_1/n46_s2/F |
9.237 | 0.000 | tNET | FF | 1 | R16C25[0][A] | clkdiv_1/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R16C25[0][A] | clkdiv_1/count_15_s0/CLK |
38.969 | -0.400 | tSu | 1 | R16C25[0][A] | clkdiv_1/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.014, 58.130%; route: 2.433, 35.232%; tC2Q: 0.458, 6.638% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_3/count_15_s0 |
To | clkdiv_3/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C23[1][A] | clkdiv_3/count_15_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R16C23[1][A] | clkdiv_3/count_15_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R16C23[1][A] | clkdiv_3/n46_s2/I0 |
2.284 | 0.372 | tINS | RF | 1 | R16C23[1][A] | clkdiv_3/n46_s2/F |
2.284 | 0.000 | tNET | FF | 1 | R16C23[1][A] | clkdiv_3/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C23[1][A] | clkdiv_3/count_15_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C23[1][A] | clkdiv_3/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path2
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_3/count_17_s0 |
To | clkdiv_3/count_17_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C23[0][A] | clkdiv_3/count_17_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R14C23[0][A] | clkdiv_3/count_17_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R14C23[0][A] | clkdiv_3/n44_s2/I2 |
2.284 | 0.372 | tINS | RF | 1 | R14C23[0][A] | clkdiv_3/n44_s2/F |
2.284 | 0.000 | tNET | FF | 1 | R14C23[0][A] | clkdiv_3/count_17_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C23[0][A] | clkdiv_3/count_17_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C23[0][A] | clkdiv_3/count_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path3
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_1/count_2_s0 |
To | clkdiv_1/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/count_2_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R13C25[1][A] | clkdiv_1/count_2_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/n59_s4/I1 |
2.284 | 0.372 | tINS | RF | 1 | R13C25[1][A] | clkdiv_1/n59_s4/F |
2.284 | 0.000 | tNET | FF | 1 | R13C25[1][A] | clkdiv_1/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/count_2_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C25[1][A] | clkdiv_1/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path4
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_1/count_12_s0 |
To | clkdiv_1/count_12_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C24[0][A] | clkdiv_1/count_12_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 2 | R13C24[0][A] | clkdiv_1/count_12_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R13C24[0][A] | clkdiv_1/n49_s2/I3 |
2.284 | 0.372 | tINS | RF | 1 | R13C24[0][A] | clkdiv_1/n49_s2/F |
2.284 | 0.000 | tNET | FF | 1 | R13C24[0][A] | clkdiv_1/count_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C24[0][A] | clkdiv_1/count_12_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C24[0][A] | clkdiv_1/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path5
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | toggle_2/out_s0 |
To | toggle_2/out_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C27[0][A] | toggle_2/out_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R15C27[0][A] | toggle_2/out_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R15C27[0][A] | toggle_2/n10_s1/I2 |
2.285 | 0.372 | tINS | RF | 1 | R15C27[0][A] | toggle_2/n10_s1/F |
2.285 | 0.000 | tNET | FF | 1 | R15C27[0][A] | toggle_2/out_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C27[0][A] | toggle_2/out_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C27[0][A] | toggle_2/out_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path6
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_3/count_2_s0 |
To | clkdiv_3/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C23[1][A] | clkdiv_3/count_2_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C23[1][A] | clkdiv_3/count_2_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C23[1][A] | clkdiv_3/n59_s2/I2 |
2.285 | 0.372 | tINS | RF | 1 | R13C23[1][A] | clkdiv_3/n59_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C23[1][A] | clkdiv_3/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C23[1][A] | clkdiv_3/count_2_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C23[1][A] | clkdiv_3/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path7
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_3/count_8_s0 |
To | clkdiv_3/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C21[1][A] | clkdiv_3/count_8_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R13C21[1][A] | clkdiv_3/count_8_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C21[1][A] | clkdiv_3/n53_s2/I0 |
2.285 | 0.372 | tINS | RF | 1 | R13C21[1][A] | clkdiv_3/n53_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C21[1][A] | clkdiv_3/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C21[1][A] | clkdiv_3/count_8_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C21[1][A] | clkdiv_3/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path8
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_2/count_2_s0 |
To | clkdiv_2/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C26[0][A] | clkdiv_2/count_2_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C26[0][A] | clkdiv_2/count_2_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C26[0][A] | clkdiv_2/n59_s4/I1 |
2.285 | 0.372 | tINS | RF | 1 | R13C26[0][A] | clkdiv_2/n59_s4/F |
2.285 | 0.000 | tNET | FF | 1 | R13C26[0][A] | clkdiv_2/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C26[0][A] | clkdiv_2/count_2_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C26[0][A] | clkdiv_2/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path9
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_2/count_3_s0 |
To | clkdiv_2/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C26[0][A] | clkdiv_2/count_3_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R15C26[0][A] | clkdiv_2/count_3_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R15C26[0][A] | clkdiv_2/n58_s2/I3 |
2.285 | 0.372 | tINS | RF | 1 | R15C26[0][A] | clkdiv_2/n58_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R15C26[0][A] | clkdiv_2/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C26[0][A] | clkdiv_2/count_3_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C26[0][A] | clkdiv_2/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path10
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_2/count_6_s0 |
To | clkdiv_2/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C26[1][A] | clkdiv_2/count_6_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C26[1][A] | clkdiv_2/count_6_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C26[1][A] | clkdiv_2/n55_s2/I3 |
2.285 | 0.372 | tINS | RF | 1 | R13C26[1][A] | clkdiv_2/n55_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C26[1][A] | clkdiv_2/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C26[1][A] | clkdiv_2/count_6_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C26[1][A] | clkdiv_2/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path11
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_2/count_11_s0 |
To | clkdiv_2/count_11_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C26[1][A] | clkdiv_2/count_11_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R15C26[1][A] | clkdiv_2/count_11_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R15C26[1][A] | clkdiv_2/n50_s2/I3 |
2.285 | 0.372 | tINS | RF | 1 | R15C26[1][A] | clkdiv_2/n50_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R15C26[1][A] | clkdiv_2/count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C26[1][A] | clkdiv_2/count_11_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C26[1][A] | clkdiv_2/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path12
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_9_s0 |
To | clkdiv_1/count_9_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C25[1][A] | clkdiv_1/count_9_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R15C25[1][A] | clkdiv_1/count_9_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R15C25[1][A] | clkdiv_1/n52_s2/I1 |
2.285 | 0.372 | tINS | RF | 1 | R15C25[1][A] | clkdiv_1/n52_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R15C25[1][A] | clkdiv_1/count_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C25[1][A] | clkdiv_1/count_9_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C25[1][A] | clkdiv_1/count_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path13
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_10_s0 |
To | clkdiv_1/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C24[1][A] | clkdiv_1/count_10_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C24[1][A] | clkdiv_1/count_10_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C24[1][A] | clkdiv_1/n51_s2/I1 |
2.285 | 0.372 | tINS | RF | 1 | R13C24[1][A] | clkdiv_1/n51_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C24[1][A] | clkdiv_1/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C24[1][A] | clkdiv_1/count_10_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C24[1][A] | clkdiv_1/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path14
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_16_s0 |
To | clkdiv_1/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C25[1][A] | clkdiv_1/count_16_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R14C25[1][A] | clkdiv_1/count_16_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R14C25[1][A] | clkdiv_1/n45_s2/I3 |
2.285 | 0.372 | tINS | RF | 1 | R14C25[1][A] | clkdiv_1/n45_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R14C25[1][A] | clkdiv_1/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C25[1][A] | clkdiv_1/count_16_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C25[1][A] | clkdiv_1/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path15
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_18_s0 |
To | clkdiv_1/count_18_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C25[0][A] | clkdiv_1/count_18_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R15C25[0][A] | clkdiv_1/count_18_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R15C25[0][A] | clkdiv_1/n43_s2/I3 |
2.285 | 0.372 | tINS | RF | 1 | R15C25[0][A] | clkdiv_1/n43_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R15C25[0][A] | clkdiv_1/count_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C25[0][A] | clkdiv_1/count_18_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C25[0][A] | clkdiv_1/count_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path16
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | run_led_1/count_1_s0 |
To | run_led_1/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C29[1][A] | run_led_1/count_1_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 16 | R14C29[1][A] | run_led_1/count_1_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R14C29[1][A] | run_led_1/n10_s0/I1 |
2.287 | 0.372 | tINS | RF | 1 | R14C29[1][A] | run_led_1/n10_s0/F |
2.287 | 0.000 | tNET | FF | 1 | R14C29[1][A] | run_led_1/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C29[1][A] | run_led_1/count_1_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C29[1][A] | run_led_1/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path17
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_3/count_10_s0 |
To | clkdiv_3/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C23[1][A] | clkdiv_3/count_10_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 6 | R15C23[1][A] | clkdiv_3/count_10_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R15C23[1][A] | clkdiv_3/n51_s2/I0 |
2.287 | 0.372 | tINS | RF | 1 | R15C23[1][A] | clkdiv_3/n51_s2/F |
2.287 | 0.000 | tNET | FF | 1 | R15C23[1][A] | clkdiv_3/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C23[1][A] | clkdiv_3/count_10_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C23[1][A] | clkdiv_3/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path18
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_3/count_11_s0 |
To | clkdiv_3/count_11_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C23[0][A] | clkdiv_3/count_11_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 6 | R15C23[0][A] | clkdiv_3/count_11_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R15C23[0][A] | clkdiv_3/n50_s2/I2 |
2.287 | 0.372 | tINS | RF | 1 | R15C23[0][A] | clkdiv_3/n50_s2/F |
2.287 | 0.000 | tNET | FF | 1 | R15C23[0][A] | clkdiv_3/count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C23[0][A] | clkdiv_3/count_11_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C23[0][A] | clkdiv_3/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path19
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_3/count_13_s0 |
To | clkdiv_3/count_13_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C22[0][A] | clkdiv_3/count_13_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 6 | R14C22[0][A] | clkdiv_3/count_13_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R14C22[0][A] | clkdiv_3/n48_s6/I0 |
2.287 | 0.372 | tINS | RF | 1 | R14C22[0][A] | clkdiv_3/n48_s6/F |
2.287 | 0.000 | tNET | FF | 1 | R14C22[0][A] | clkdiv_3/count_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C22[0][A] | clkdiv_3/count_13_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C22[0][A] | clkdiv_3/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path20
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_2/count_1_s0 |
To | clkdiv_2/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C27[0][A] | clkdiv_2/count_1_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R13C27[0][A] | clkdiv_2/count_1_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R13C27[0][A] | clkdiv_2/n60_s2/I1 |
2.287 | 0.372 | tINS | RF | 1 | R13C27[0][A] | clkdiv_2/n60_s2/F |
2.287 | 0.000 | tNET | FF | 1 | R13C27[0][A] | clkdiv_2/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C27[0][A] | clkdiv_2/count_1_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C27[0][A] | clkdiv_2/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path21
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_1/count_15_s0 |
To | clkdiv_1/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C25[0][A] | clkdiv_1/count_15_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R16C25[0][A] | clkdiv_1/count_15_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R16C25[0][A] | clkdiv_1/n46_s2/I1 |
2.287 | 0.372 | tINS | RF | 1 | R16C25[0][A] | clkdiv_1/n46_s2/F |
2.287 | 0.000 | tNET | FF | 1 | R16C25[0][A] | clkdiv_1/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C25[0][A] | clkdiv_1/count_15_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C25[0][A] | clkdiv_1/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path22
Path Summary:
Slack | 0.711 |
Data Arrival Time | 2.011 |
Data Required Time | 1.300 |
From | inst20/col_0_s0 |
To | inst20/col_0_s0 |
Launch Clk | clk160hz:[R] |
Latch Clk | clk160hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk160hz | ||||
0.000 | 0.000 | tCL | RR | 14 | R14C23[2][A] | clkdiv_3/clk_out_s0/Q |
1.300 | 1.300 | tNET | RR | 1 | R14C32[0][A] | inst20/col_0_s0/CLK |
1.633 | 0.333 | tC2Q | RR | 21 | R14C32[0][A] | inst20/col_0_s0/Q |
1.639 | 0.006 | tNET | RR | 1 | R14C32[0][A] | inst20/n12_s4/I0 |
2.011 | 0.372 | tINS | RF | 1 | R14C32[0][A] | inst20/n12_s4/F |
2.011 | 0.000 | tNET | FF | 1 | R14C32[0][A] | inst20/col_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk160hz | ||||
0.000 | 0.000 | tCL | RR | 14 | R14C23[2][A] | clkdiv_3/clk_out_s0/Q |
1.300 | 1.300 | tNET | RR | 1 | R14C32[0][A] | inst20/col_0_s0/CLK |
1.300 | 0.000 | tHld | 1 | R14C32[0][A] | inst20/col_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.300, 100.000% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.300, 100.000% |
Path23
Path Summary:
Slack | 0.711 |
Data Arrival Time | 2.288 |
Data Required Time | 1.577 |
From | run_led_1/count_0_s0 |
To | run_led_1/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C29[0][A] | run_led_1/count_0_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 16 | R14C29[0][A] | run_led_1/count_0_s0/Q |
1.916 | 0.006 | tNET | RR | 1 | R14C29[0][A] | run_led_1/n11_s2/I0 |
2.288 | 0.372 | tINS | RF | 1 | R14C29[0][A] | run_led_1/n11_s2/F |
2.288 | 0.000 | tNET | FF | 1 | R14C29[0][A] | run_led_1/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C29[0][A] | run_led_1/count_0_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C29[0][A] | run_led_1/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path24
Path Summary:
Slack | 0.711 |
Data Arrival Time | 2.288 |
Data Required Time | 1.577 |
From | cntr4max_3/cnt_2_s0 |
To | cntr4max_3/cnt_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C34[0][A] | cntr4max_3/cnt_2_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 16 | R13C34[0][A] | cntr4max_3/cnt_2_s0/Q |
1.916 | 0.006 | tNET | RR | 1 | R13C34[0][A] | cntr4max_3/n17_s4/I1 |
2.288 | 0.372 | tINS | RF | 1 | R13C34[0][A] | cntr4max_3/n17_s4/F |
2.288 | 0.000 | tNET | FF | 1 | R13C34[0][A] | cntr4max_3/cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C34[0][A] | cntr4max_3/cnt_2_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C34[0][A] | cntr4max_3/cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path25
Path Summary:
Slack | 0.711 |
Data Arrival Time | 2.288 |
Data Required Time | 1.577 |
From | cntr4max_2/cnt_0_s1 |
To | cntr4max_2/cnt_0_s1 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C31[0][A] | cntr4max_2/cnt_0_s1/CLK |
1.910 | 0.333 | tC2Q | RR | 18 | R13C31[0][A] | cntr4max_2/cnt_0_s1/Q |
1.916 | 0.006 | tNET | RR | 1 | R13C31[0][A] | cntr4max_2/n19_s5/I1 |
2.288 | 0.372 | tINS | RF | 1 | R13C31[0][A] | cntr4max_2/n19_s5/F |
2.288 | 0.000 | tNET | FF | 1 | R13C31[0][A] | cntr4max_2/cnt_0_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 86 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C31[0][A] | cntr4max_2/cnt_0_s1/CLK |
1.577 | 0.000 | tHld | 1 | R13C31[0][A] | cntr4max_2/cnt_0_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_18_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_18_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_18_s0/CLK |
MPW2
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_16_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_16_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_16_s0/CLK |
MPW3
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_12_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_12_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_12_s0/CLK |
MPW4
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_4_s0/CLK |
MPW5
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_2/count_6_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_2/count_6_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_2/count_6_s0/CLK |
MPW6
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | cntr4maxe_1/cnt_0_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | cntr4maxe_1/cnt_0_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | cntr4maxe_1/cnt_0_s1/CLK |
MPW7
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | cntr4maxe_1/cnt_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | cntr4maxe_1/cnt_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | cntr4maxe_1/cnt_3_s0/CLK |
MPW8
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_2/count_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_2/count_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_2/count_7_s0/CLK |
MPW9
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | cntr4maxe_1/cnt_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | cntr4maxe_1/cnt_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | cntr4maxe_1/cnt_1_s0/CLK |
MPW10
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | cntr4maxe_1/cnt_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | cntr4maxe_1/cnt_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | cntr4maxe_1/cnt_2_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
86 | clk_d | 28.409 | 0.262 |
21 | col[0] | 9999984.000 | 1.335 |
21 | n7_4 | 29.782 | 3.129 |
20 | n7_122 | 28.473 | 1.980 |
19 | cnt10hz[0] | 30.286 | 2.471 |
19 | cnt100hz[0] | 30.621 | 1.344 |
18 | cnt10s[0] | 32.530 | 1.789 |
18 | n61_20 | 29.838 | 1.022 |
18 | cnt1s[0] | 31.422 | 1.809 |
18 | cnt10hz[1] | 30.763 | 2.138 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R15C27 | 77.78% |
R13C27 | 73.61% |
R14C25 | 63.89% |
R13C34 | 63.89% |
R13C23 | 63.89% |
R13C24 | 61.11% |
R14C22 | 58.33% |
R14C23 | 56.94% |
R13C29 | 56.94% |
R14C32 | 55.56% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk160hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 270000 [get_nets {clk160hz}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk400hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 67500 [get_nets {clk400hz}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk27mhz}] -group [get_clocks {clk400hz}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk27mhz}] -group [get_clocks {clk160hz}] |