Timing Messages

Report Title Timing Analysis Report
Design File C:\Gowin\SV_240812_mhut_2001\uart\impl\gwsynthesis\uart.vg
Physical Constraints File C:\Gowin\SV_240812_mhut_2001\uart\src\uart.cst
Timing Constraint File C:\Gowin\SV_240812_mhut_2001\uart\src\uart.sdc
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Aug 12 12:10:31 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.14V 85C C6/I5
Hold Delay Model Fast 1.26V 0C C6/I5
Numbers of Paths Analyzed 554
Numbers of Endpoints Analyzed 307
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk27mhz Base 37.037 27.000 0.000 18.518 clk
2 clkbaud Generated 8666.657 0.115 0.000 4333.329 clk clk27mhz clkbaudhz
3 clk400hz Generated 2499997.500 0.000 0.000 1249998.750 clk clk27mhz clk400hz
4 clk160hz Generated 6249993.500 0.000 0.000 3124996.750 clk clk27mhz clk160hz
5 clkbaudx2 Generated 4333.329 0.231 0.000 2166.664 clk clk27mhz clkbaudx2hz

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk27mhz 27.000(MHz) 120.954(MHz) 5 TOP
2 clkbaud 0.115(MHz) 128.096(MHz) 4 TOP
3 clk400hz 0.000(MHz) 222.222(MHz) 2 TOP
4 clk160hz 0.000(MHz) 153.846(MHz) 2 TOP
5 clkbaudx2 0.231(MHz) 106.800(MHz) 4 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk27mhz Setup 0.000 0
clk27mhz Hold 0.000 0
clkbaud Setup 0.000 0
clkbaud Hold 0.000 0
clk400hz Setup 0.000 0
clk400hz Hold 0.000 0
clk160hz Setup 0.000 0
clk160hz Hold 0.000 0
clkbaudx2 Setup 0.000 0
clkbaudx2 Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 28.769 clkdiv_3/count_1_s0/Q clkdiv_3/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.868
2 28.866 clkdiv_3/count_1_s0/Q clkdiv_3/clk_out_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.771
3 28.879 clkdiv_4/count_0_s0/Q clkdiv_4/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.758
4 28.879 clkdiv_4/count_0_s0/Q clkdiv_4/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.758
5 29.073 clkdiv_4/count_0_s0/Q clkdiv_4/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.564
6 29.073 clkdiv_4/count_0_s0/Q clkdiv_4/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.564
7 29.073 clkdiv_4/count_0_s0/Q clkdiv_4/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.564
8 29.297 clkdiv_4/count_0_s0/Q clkdiv_4/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.340
9 29.297 clkdiv_4/count_0_s0/Q clkdiv_4/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.340
10 29.336 clkdiv_3/count_1_s0/Q clkdiv_3/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.301
11 29.401 clkdiv_3/count_1_s0/Q clkdiv_3/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.236
12 29.482 clkdiv_3/count_8_s0/Q clkdiv_3/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.155
13 29.482 clkdiv_3/count_8_s0/Q clkdiv_3/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.155
14 29.545 clkdiv_3/count_8_s0/Q clkdiv_3/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.092
15 29.545 clkdiv_3/count_8_s0/Q clkdiv_3/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.092
16 29.545 clkdiv_3/count_8_s0/Q clkdiv_3/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.092
17 29.558 clkdiv_4/count_0_s0/Q clkdiv_4/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.079
18 29.558 clkdiv_4/count_0_s0/Q clkdiv_4/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.079
19 29.558 clkdiv_4/count_0_s0/Q clkdiv_4/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.079
20 29.572 clkdiv_3/count_1_s0/Q clkdiv_3/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.065
21 29.633 clkdiv_4/count_0_s0/Q clkdiv_4/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 7.004
22 29.754 clkdiv_4/count_0_s0/Q clkdiv_4/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.883
23 29.754 clkdiv_4/count_0_s0/Q clkdiv_4/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.883
24 29.754 clkdiv_4/count_0_s0/Q clkdiv_4/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.883
25 29.770 clkdiv_4/count_0_s0/Q clkdiv_4/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.867

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.708 clkdiv_1/count_6_s0/Q clkdiv_1/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.708
2 0.709 clkdiv_4/count_3_s0/Q clkdiv_4/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
3 0.709 clkdiv_4/count_15_s0/Q clkdiv_4/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
4 0.709 clkdiv_3/count_6_s0/Q clkdiv_3/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
5 0.709 clkdiv_3/count_10_s0/Q clkdiv_3/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
6 0.709 clkdiv_3/count_12_s0/Q clkdiv_3/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
7 0.709 clkdiv_2/count_0_s0/Q clkdiv_2/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
8 0.709 clkdiv_1/count_4_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
9 0.709 clkdiv_1/count_7_s0/Q clkdiv_1/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.709
10 0.709 rx_1/count_3_s0/Q rx_1/count_3_s0/D clkbaudx2:[R] clkbaudx2:[R] 0.000 0.000 0.709
11 0.710 rx_1/count_1_s0/Q rx_1/count_1_s0/D clkbaudx2:[R] clkbaudx2:[R] 0.000 0.000 0.710
12 0.710 clkdiv_4/count_5_s0/Q clkdiv_4/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.710
13 0.710 clkdiv_3/count_3_s0/Q clkdiv_3/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.710
14 0.710 clkdiv_3/count_4_s0/Q clkdiv_3/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.710
15 0.710 clkdiv_2/count_5_s0/Q clkdiv_2/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.710
16 0.710 clkdiv_1/count_2_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.710
17 0.711 clkdiv_4/count_9_s0/Q clkdiv_4/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.711
18 0.711 clkdiv_4/count_16_s0/Q clkdiv_4/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.711
19 0.711 clkdiv_3/count_5_s0/Q clkdiv_3/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.711
20 0.712 tx_1/state_1_s3/Q tx_1/state_1_s3/D clkbaud:[R] clkbaud:[R] 0.000 0.000 0.712
21 0.714 mux7seg_1/col_1_s0/Q mux7seg_1/col_1_s0/D clk160hz:[R] clk160hz:[R] 0.000 0.000 0.714
22 0.892 clkdiv_1/count_1_s0/Q clkdiv_1/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.892
23 0.893 clkdiv_4/count_1_s0/Q clkdiv_4/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.893
24 0.893 clkdiv_4/count_7_s0/Q clkdiv_4/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.893
25 0.893 clkdiv_3/count_8_s0/Q clkdiv_3/count_8_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.893

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_7_s0
2 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_5_s0
3 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_1_s0
4 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_2/count_1_s0
5 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_3/count_3_s0
6 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_3/count_4_s0
7 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_2/count_2_s0
8 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_3/count_5_s0
9 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_3/count_6_s0
10 16.269 17.519 1.250 Low Pulse Width clk27mhz clkdiv_1/count_2_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 28.769
Data Arrival Time 10.199
Data Required Time 38.969
From clkdiv_3/count_1_s0
To clkdiv_3/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R16C19[2][A] clkdiv_3/count_1_s0/CLK
2.790 0.458 tC2Q RF 6 R16C19[2][A] clkdiv_3/count_1_s0/Q
4.583 1.793 tNET FF 1 R16C16[2][A] clkdiv_3/n57_s3/I0
5.682 1.099 tINS FF 8 R16C16[2][A] clkdiv_3/n57_s3/F
6.523 0.841 tNET FF 1 R16C14[2][A] clkdiv_3/n47_s3/I1
7.622 1.099 tINS FF 3 R16C14[2][A] clkdiv_3/n47_s3/F
8.942 1.320 tNET FF 1 R16C17[1][A] clkdiv_3/n46_s3/I1
9.568 0.626 tINS FF 1 R16C17[1][A] clkdiv_3/n46_s3/F
9.573 0.005 tNET FF 1 R16C17[1][B] clkdiv_3/n45_s2/I1
10.199 0.626 tINS FF 1 R16C17[1][B] clkdiv_3/n45_s2/F
10.199 0.000 tNET FF 1 R16C17[1][B] clkdiv_3/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R16C17[1][B] clkdiv_3/count_16_s0/CLK
38.969 -0.400 tSu 1 R16C17[1][B] clkdiv_3/count_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.450, 43.851%; route: 3.959, 50.323%; tC2Q: 0.458, 5.826%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path2

Path Summary:

Slack 28.866
Data Arrival Time 10.103
Data Required Time 38.969
From clkdiv_3/count_1_s0
To clkdiv_3/clk_out_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R16C19[2][A] clkdiv_3/count_1_s0/CLK
2.790 0.458 tC2Q RF 6 R16C19[2][A] clkdiv_3/count_1_s0/Q
4.583 1.793 tNET FF 1 R16C16[3][A] clkdiv_3/n63_s84/I1
5.682 1.099 tINS FF 1 R16C16[3][A] clkdiv_3/n63_s84/F
6.487 0.804 tNET FF 1 R16C15[2][B] clkdiv_3/n63_s80/I0
7.548 1.061 tINS FR 1 R16C15[2][B] clkdiv_3/n63_s80/F
7.967 0.419 tNET RR 1 R16C16[2][B] clkdiv_3/n63_s78/I1
9.066 1.099 tINS RF 1 R16C16[2][B] clkdiv_3/n63_s78/F
9.071 0.005 tNET FF 1 R16C16[1][B] clkdiv_3/n63_s85/I1
10.103 1.032 tINS FF 1 R16C16[1][B] clkdiv_3/n63_s85/F
10.103 0.000 tNET FF 1 R16C16[1][B] clkdiv_3/clk_out_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R16C16[1][B] clkdiv_3/clk_out_s0/CLK
38.969 -0.400 tSu 1 R16C16[1][B] clkdiv_3/clk_out_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.291, 55.218%; route: 3.022, 38.885%; tC2Q: 0.458, 5.898%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path3

Path Summary:

Slack 28.879
Data Arrival Time 10.090
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
9.058 1.315 tNET FF 1 R15C25[2][A] clkdiv_4/n48_s2/I2
10.090 1.032 tINS FF 1 R15C25[2][A] clkdiv_4/n48_s2/F
10.090 0.000 tNET FF 1 R15C25[2][A] clkdiv_4/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C25[2][A] clkdiv_4/count_13_s0/CLK
38.969 -0.400 tSu 1 R15C25[2][A] clkdiv_4/count_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.256, 54.859%; route: 3.044, 39.233%; tC2Q: 0.458, 5.908%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path4

Path Summary:

Slack 28.879
Data Arrival Time 10.090
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
9.058 1.315 tNET FF 1 R15C25[1][B] clkdiv_4/n47_s2/I3
10.090 1.032 tINS FF 1 R15C25[1][B] clkdiv_4/n47_s2/F
10.090 0.000 tNET FF 1 R15C25[1][B] clkdiv_4/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C25[1][B] clkdiv_4/count_14_s0/CLK
38.969 -0.400 tSu 1 R15C25[1][B] clkdiv_4/count_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.256, 54.859%; route: 3.044, 39.233%; tC2Q: 0.458, 5.908%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path5

Path Summary:

Slack 29.073
Data Arrival Time 9.896
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
9.074 1.331 tNET FF 1 R15C25[2][B] clkdiv_4/n49_s2/I1
9.896 0.822 tINS FF 1 R15C25[2][B] clkdiv_4/n49_s2/F
9.896 0.000 tNET FF 1 R15C25[2][B] clkdiv_4/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C25[2][B] clkdiv_4/count_12_s0/CLK
38.969 -0.400 tSu 1 R15C25[2][B] clkdiv_4/count_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.046, 53.491%; route: 3.060, 40.450%; tC2Q: 0.458, 6.059%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path6

Path Summary:

Slack 29.073
Data Arrival Time 9.896
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
9.074 1.331 tNET FF 1 R15C25[1][A] clkdiv_4/n46_s2/I2
9.896 0.822 tINS FF 1 R15C25[1][A] clkdiv_4/n46_s2/F
9.896 0.000 tNET FF 1 R15C25[1][A] clkdiv_4/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C25[1][A] clkdiv_4/count_15_s0/CLK
38.969 -0.400 tSu 1 R15C25[1][A] clkdiv_4/count_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.046, 53.491%; route: 3.060, 40.450%; tC2Q: 0.458, 6.059%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path7

Path Summary:

Slack 29.073
Data Arrival Time 9.896
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
9.074 1.331 tNET FF 1 R15C25[0][B] clkdiv_4/n44_s2/I3
9.896 0.822 tINS FF 1 R15C25[0][B] clkdiv_4/n44_s2/F
9.896 0.000 tNET FF 1 R15C25[0][B] clkdiv_4/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C25[0][B] clkdiv_4/count_17_s0/CLK
38.969 -0.400 tSu 1 R15C25[0][B] clkdiv_4/count_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.046, 53.491%; route: 3.060, 40.450%; tC2Q: 0.458, 6.059%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path8

Path Summary:

Slack 29.297
Data Arrival Time 9.672
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
8.573 0.831 tNET FF 1 R14C24[2][B] clkdiv_4/n55_s2/I3
9.672 1.099 tINS FF 1 R14C24[2][B] clkdiv_4/n55_s2/F
9.672 0.000 tNET FF 1 R14C24[2][B] clkdiv_4/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R14C24[2][B] clkdiv_4/count_6_s0/CLK
38.969 -0.400 tSu 1 R14C24[2][B] clkdiv_4/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.323, 58.893%; route: 2.559, 34.863%; tC2Q: 0.458, 6.244%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path9

Path Summary:

Slack 29.297
Data Arrival Time 9.672
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
8.573 0.831 tNET FF 1 R14C24[1][A] clkdiv_4/n52_s2/I3
9.672 1.099 tINS FF 1 R14C24[1][A] clkdiv_4/n52_s2/F
9.672 0.000 tNET FF 1 R14C24[1][A] clkdiv_4/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R14C24[1][A] clkdiv_4/count_9_s0/CLK
38.969 -0.400 tSu 1 R14C24[1][A] clkdiv_4/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.323, 58.893%; route: 2.559, 34.863%; tC2Q: 0.458, 6.244%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path10

Path Summary:

Slack 29.336
Data Arrival Time 9.633
Data Required Time 38.969
From clkdiv_3/count_1_s0
To clkdiv_3/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R16C19[2][A] clkdiv_3/count_1_s0/CLK
2.790 0.458 tC2Q RF 6 R16C19[2][A] clkdiv_3/count_1_s0/Q
4.583 1.793 tNET FF 1 R16C16[2][A] clkdiv_3/n57_s3/I0
5.682 1.099 tINS FF 8 R16C16[2][A] clkdiv_3/n57_s3/F
6.523 0.841 tNET FF 1 R16C14[2][A] clkdiv_3/n47_s3/I1
7.622 1.099 tINS FF 3 R16C14[2][A] clkdiv_3/n47_s3/F
8.601 0.979 tNET FF 1 R16C17[2][A] clkdiv_3/n47_s2/I1
9.633 1.032 tINS FF 1 R16C17[2][A] clkdiv_3/n47_s2/F
9.633 0.000 tNET FF 1 R16C17[2][A] clkdiv_3/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R16C17[2][A] clkdiv_3/count_14_s0/CLK
38.969 -0.400 tSu 1 R16C17[2][A] clkdiv_3/count_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.230, 44.238%; route: 3.613, 49.485%; tC2Q: 0.458, 6.277%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path11

Path Summary:

Slack 29.401
Data Arrival Time 9.568
Data Required Time 38.969
From clkdiv_3/count_1_s0
To clkdiv_3/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R16C19[2][A] clkdiv_3/count_1_s0/CLK
2.790 0.458 tC2Q RF 6 R16C19[2][A] clkdiv_3/count_1_s0/Q
4.583 1.793 tNET FF 1 R16C16[2][A] clkdiv_3/n57_s3/I0
5.682 1.099 tINS FF 8 R16C16[2][A] clkdiv_3/n57_s3/F
6.523 0.841 tNET FF 1 R16C14[2][A] clkdiv_3/n47_s3/I1
7.622 1.099 tINS FF 3 R16C14[2][A] clkdiv_3/n47_s3/F
8.942 1.320 tNET FF 1 R16C17[0][B] clkdiv_3/n46_s4/I2
9.568 0.626 tINS FF 1 R16C17[0][B] clkdiv_3/n46_s4/F
9.568 0.000 tNET FF 1 R16C17[0][B] clkdiv_3/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R16C17[0][B] clkdiv_3/count_15_s0/CLK
38.969 -0.400 tSu 1 R16C17[0][B] clkdiv_3/count_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 2.824, 39.027%; route: 3.954, 54.639%; tC2Q: 0.458, 6.334%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path12

Path Summary:

Slack 29.482
Data Arrival Time 9.487
Data Required Time 38.969
From clkdiv_3/count_8_s0
To clkdiv_3/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R16C18[2][A] clkdiv_3/count_8_s0/CLK
2.790 0.458 tC2Q RF 4 R16C18[2][A] clkdiv_3/count_8_s0/Q
4.107 1.317 tNET FF 1 R16C15[3][B] clkdiv_3/n47_s4/I1
5.168 1.061 tINS FR 4 R16C15[3][B] clkdiv_3/n47_s4/F
5.591 0.423 tNET RR 1 R16C16[0][B] clkdiv_3/n61_s4/I3
6.413 0.822 tINS RF 1 R16C16[0][B] clkdiv_3/n61_s4/F
6.418 0.005 tNET FF 1 R16C16[3][B] clkdiv_3/n61_s9/I1
7.517 1.099 tINS FF 17 R16C16[3][B] clkdiv_3/n61_s9/F
8.388 0.870 tNET FF 1 R16C19[2][B] clkdiv_3/n61_s2/I1
9.487 1.099 tINS FF 1 R16C19[2][B] clkdiv_3/n61_s2/F
9.487 0.000 tNET FF 1 R16C19[2][B] clkdiv_3/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R16C19[2][B] clkdiv_3/count_0_s0/CLK
38.969 -0.400 tSu 1 R16C19[2][B] clkdiv_3/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.081, 57.040%; route: 2.615, 36.554%; tC2Q: 0.458, 6.406%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path13

Path Summary:

Slack 29.482
Data Arrival Time 9.487
Data Required Time 38.969
From clkdiv_3/count_8_s0
To clkdiv_3/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R16C18[2][A] clkdiv_3/count_8_s0/CLK
2.790 0.458 tC2Q RF 4 R16C18[2][A] clkdiv_3/count_8_s0/Q
4.107 1.317 tNET FF 1 R16C15[3][B] clkdiv_3/n47_s4/I1
5.168 1.061 tINS FR 4 R16C15[3][B] clkdiv_3/n47_s4/F
5.591 0.423 tNET RR 1 R16C16[0][B] clkdiv_3/n61_s4/I3
6.413 0.822 tINS RF 1 R16C16[0][B] clkdiv_3/n61_s4/F
6.418 0.005 tNET FF 1 R16C16[3][B] clkdiv_3/n61_s9/I1
7.517 1.099 tINS FF 17 R16C16[3][B] clkdiv_3/n61_s9/F
8.388 0.870 tNET FF 1 R16C19[2][A] clkdiv_3/n60_s2/I2
9.487 1.099 tINS FF 1 R16C19[2][A] clkdiv_3/n60_s2/F
9.487 0.000 tNET FF 1 R16C19[2][A] clkdiv_3/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R16C19[2][A] clkdiv_3/count_1_s0/CLK
38.969 -0.400 tSu 1 R16C19[2][A] clkdiv_3/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.081, 57.040%; route: 2.615, 36.554%; tC2Q: 0.458, 6.406%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path14

Path Summary:

Slack 29.545
Data Arrival Time 9.424
Data Required Time 38.969
From clkdiv_3/count_8_s0
To clkdiv_3/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R16C18[2][A] clkdiv_3/count_8_s0/CLK
2.790 0.458 tC2Q RF 4 R16C18[2][A] clkdiv_3/count_8_s0/Q
4.107 1.317 tNET FF 1 R16C15[3][B] clkdiv_3/n47_s4/I1
5.168 1.061 tINS FR 4 R16C15[3][B] clkdiv_3/n47_s4/F
5.591 0.423 tNET RR 1 R16C16[0][B] clkdiv_3/n61_s4/I3
6.413 0.822 tINS RF 1 R16C16[0][B] clkdiv_3/n61_s4/F
6.418 0.005 tNET FF 1 R16C16[3][B] clkdiv_3/n61_s9/I1
7.517 1.099 tINS FF 17 R16C16[3][B] clkdiv_3/n61_s9/F
8.392 0.875 tNET FF 1 R16C19[1][B] clkdiv_3/n59_s4/I3
9.424 1.032 tINS FF 1 R16C19[1][B] clkdiv_3/n59_s4/F
9.424 0.000 tNET FF 1 R16C19[1][B] clkdiv_3/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R16C19[1][B] clkdiv_3/count_2_s0/CLK
38.969 -0.400 tSu 1 R16C19[1][B] clkdiv_3/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.014, 56.598%; route: 2.620, 36.940%; tC2Q: 0.458, 6.463%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path15

Path Summary:

Slack 29.545
Data Arrival Time 9.424
Data Required Time 38.969
From clkdiv_3/count_8_s0
To clkdiv_3/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R16C18[2][A] clkdiv_3/count_8_s0/CLK
2.790 0.458 tC2Q RF 4 R16C18[2][A] clkdiv_3/count_8_s0/Q
4.107 1.317 tNET FF 1 R16C15[3][B] clkdiv_3/n47_s4/I1
5.168 1.061 tINS FR 4 R16C15[3][B] clkdiv_3/n47_s4/F
5.591 0.423 tNET RR 1 R16C16[0][B] clkdiv_3/n61_s4/I3
6.413 0.822 tINS RF 1 R16C16[0][B] clkdiv_3/n61_s4/F
6.418 0.005 tNET FF 1 R16C16[3][B] clkdiv_3/n61_s9/I1
7.517 1.099 tINS FF 17 R16C16[3][B] clkdiv_3/n61_s9/F
8.392 0.875 tNET FF 1 R16C19[1][A] clkdiv_3/n57_s2/I2
9.424 1.032 tINS FF 1 R16C19[1][A] clkdiv_3/n57_s2/F
9.424 0.000 tNET FF 1 R16C19[1][A] clkdiv_3/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R16C19[1][A] clkdiv_3/count_4_s0/CLK
38.969 -0.400 tSu 1 R16C19[1][A] clkdiv_3/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.014, 56.598%; route: 2.620, 36.940%; tC2Q: 0.458, 6.463%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path16

Path Summary:

Slack 29.545
Data Arrival Time 9.424
Data Required Time 38.969
From clkdiv_3/count_8_s0
To clkdiv_3/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R16C18[2][A] clkdiv_3/count_8_s0/CLK
2.790 0.458 tC2Q RF 4 R16C18[2][A] clkdiv_3/count_8_s0/Q
4.107 1.317 tNET FF 1 R16C15[3][B] clkdiv_3/n47_s4/I1
5.168 1.061 tINS FR 4 R16C15[3][B] clkdiv_3/n47_s4/F
5.591 0.423 tNET RR 1 R16C16[0][B] clkdiv_3/n61_s4/I3
6.413 0.822 tINS RF 1 R16C16[0][B] clkdiv_3/n61_s4/F
6.418 0.005 tNET FF 1 R16C16[3][B] clkdiv_3/n61_s9/I1
7.517 1.099 tINS FF 17 R16C16[3][B] clkdiv_3/n61_s9/F
8.392 0.875 tNET FF 1 R16C19[0][A] clkdiv_3/n55_s2/I3
9.424 1.032 tINS FF 1 R16C19[0][A] clkdiv_3/n55_s2/F
9.424 0.000 tNET FF 1 R16C19[0][A] clkdiv_3/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R16C19[0][A] clkdiv_3/count_6_s0/CLK
38.969 -0.400 tSu 1 R16C19[0][A] clkdiv_3/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.014, 56.598%; route: 2.620, 36.940%; tC2Q: 0.458, 6.463%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path17

Path Summary:

Slack 29.558
Data Arrival Time 9.411
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
8.589 0.847 tNET FF 1 R14C25[2][B] clkdiv_4/n61_s3/I1
9.411 0.822 tINS FF 1 R14C25[2][B] clkdiv_4/n61_s3/F
9.411 0.000 tNET FF 1 R14C25[2][B] clkdiv_4/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
38.969 -0.400 tSu 1 R14C25[2][B] clkdiv_4/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.046, 57.152%; route: 2.575, 36.373%; tC2Q: 0.458, 6.474%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path18

Path Summary:

Slack 29.558
Data Arrival Time 9.411
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
8.589 0.847 tNET FF 1 R14C25[1][A] clkdiv_4/n58_s2/I2
9.411 0.822 tINS FF 1 R14C25[1][A] clkdiv_4/n58_s2/F
9.411 0.000 tNET FF 1 R14C25[1][A] clkdiv_4/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R14C25[1][A] clkdiv_4/count_3_s0/CLK
38.969 -0.400 tSu 1 R14C25[1][A] clkdiv_4/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.046, 57.152%; route: 2.575, 36.373%; tC2Q: 0.458, 6.474%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path19

Path Summary:

Slack 29.558
Data Arrival Time 9.411
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
8.589 0.847 tNET FF 1 R14C25[0][A] clkdiv_4/n56_s2/I3
9.411 0.822 tINS FF 1 R14C25[0][A] clkdiv_4/n56_s2/F
9.411 0.000 tNET FF 1 R14C25[0][A] clkdiv_4/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R14C25[0][A] clkdiv_4/count_5_s0/CLK
38.969 -0.400 tSu 1 R14C25[0][A] clkdiv_4/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 4.046, 57.152%; route: 2.575, 36.373%; tC2Q: 0.458, 6.474%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path20

Path Summary:

Slack 29.572
Data Arrival Time 9.397
Data Required Time 38.969
From clkdiv_3/count_1_s0
To clkdiv_3/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R16C19[2][A] clkdiv_3/count_1_s0/CLK
2.790 0.458 tC2Q RF 6 R16C19[2][A] clkdiv_3/count_1_s0/Q
4.583 1.793 tNET FF 1 R16C16[2][A] clkdiv_3/n57_s3/I0
5.682 1.099 tINS FF 8 R16C16[2][A] clkdiv_3/n57_s3/F
6.828 1.146 tNET FF 1 R16C18[0][B] clkdiv_3/n54_s5/I0
7.650 0.822 tINS FF 3 R16C18[0][B] clkdiv_3/n54_s5/F
7.667 0.016 tNET FF 1 R16C18[0][A] clkdiv_3/n52_s3/I2
8.766 1.099 tINS FF 1 R16C18[0][A] clkdiv_3/n52_s3/F
8.771 0.005 tNET FF 1 R16C18[1][B] clkdiv_3/n52_s2/I0
9.397 0.626 tINS FF 1 R16C18[1][B] clkdiv_3/n52_s2/F
9.397 0.000 tNET FF 1 R16C18[1][B] clkdiv_3/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R16C18[1][B] clkdiv_3/count_9_s0/CLK
38.969 -0.400 tSu 1 R16C18[1][B] clkdiv_3/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.646, 51.603%; route: 2.961, 41.910%; tC2Q: 0.458, 6.487%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path21

Path Summary:

Slack 29.633
Data Arrival Time 9.336
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.105 1.315 tNET FF 1 R14C24[0][A] clkdiv_4/n57_s3/I0
4.927 0.822 tINS FF 5 R14C24[0][A] clkdiv_4/n57_s3/F
5.764 0.836 tNET FF 1 R15C24[1][A] clkdiv_4/n48_s3/I0
6.796 1.032 tINS FF 3 R15C24[1][A] clkdiv_4/n48_s3/F
6.807 0.011 tNET FF 1 R15C24[2][A] clkdiv_4/n46_s3/I2
7.433 0.626 tINS FF 3 R15C24[2][A] clkdiv_4/n46_s3/F
8.237 0.804 tNET FF 1 R14C23[0][A] clkdiv_4/n45_s3/I1
9.336 1.099 tINS FF 1 R14C23[0][A] clkdiv_4/n45_s3/F
9.336 0.000 tNET FF 1 R14C23[0][A] clkdiv_4/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R14C23[0][A] clkdiv_4/count_16_s0/CLK
38.969 -0.400 tSu 1 R14C23[0][A] clkdiv_4/count_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.579, 51.098%; route: 2.967, 42.359%; tC2Q: 0.458, 6.544%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path22

Path Summary:

Slack 29.754
Data Arrival Time 9.215
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
8.589 0.847 tNET FF 1 R14C25[2][A] clkdiv_4/n60_s2/I2
9.215 0.626 tINS FF 1 R14C25[2][A] clkdiv_4/n60_s2/F
9.215 0.000 tNET FF 1 R14C25[2][A] clkdiv_4/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R14C25[2][A] clkdiv_4/count_1_s0/CLK
38.969 -0.400 tSu 1 R14C25[2][A] clkdiv_4/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.850, 55.932%; route: 2.575, 37.409%; tC2Q: 0.458, 6.659%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path23

Path Summary:

Slack 29.754
Data Arrival Time 9.215
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
8.589 0.847 tNET FF 1 R14C25[1][B] clkdiv_4/n59_s2/I3
9.215 0.626 tINS FF 1 R14C25[1][B] clkdiv_4/n59_s2/F
9.215 0.000 tNET FF 1 R14C25[1][B] clkdiv_4/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R14C25[1][B] clkdiv_4/count_2_s0/CLK
38.969 -0.400 tSu 1 R14C25[1][B] clkdiv_4/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.850, 55.932%; route: 2.575, 37.409%; tC2Q: 0.458, 6.659%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path24

Path Summary:

Slack 29.754
Data Arrival Time 9.215
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
8.589 0.847 tNET FF 1 R14C25[0][B] clkdiv_4/n57_s2/I2
9.215 0.626 tINS FF 1 R14C25[0][B] clkdiv_4/n57_s2/F
9.215 0.000 tNET FF 1 R14C25[0][B] clkdiv_4/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R14C25[0][B] clkdiv_4/count_4_s0/CLK
38.969 -0.400 tSu 1 R14C25[0][B] clkdiv_4/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.850, 55.932%; route: 2.575, 37.409%; tC2Q: 0.458, 6.659%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Path25

Path Summary:

Slack 29.770
Data Arrival Time 9.199
Data Required Time 38.969
From clkdiv_4/count_0_s0
To clkdiv_4/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
2.088 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
2.332 0.244 tNET RR 1 R14C25[2][B] clkdiv_4/count_0_s0/CLK
2.790 0.458 tC2Q RF 6 R14C25[2][B] clkdiv_4/count_0_s0/Q
4.094 1.304 tNET FF 1 R14C23[2][A] clkdiv_4/n61_s9/I1
5.120 1.026 tINS FR 1 R14C23[2][A] clkdiv_4/n61_s9/F
5.539 0.419 tNET RR 1 R14C22[1][B] clkdiv_4/n61_s5/I1
6.638 1.099 tINS RF 1 R14C22[1][B] clkdiv_4/n61_s5/F
6.644 0.005 tNET FF 1 R14C22[0][A] clkdiv_4/n61_s15/I0
7.743 1.099 tINS FF 17 R14C22[0][A] clkdiv_4/n61_s15/F
8.573 0.831 tNET FF 1 R15C24[0][A] clkdiv_4/n51_s2/I0
9.199 0.626 tINS FF 1 R15C24[0][A] clkdiv_4/n51_s2/F
9.199 0.000 tNET FF 1 R15C24[0][A] clkdiv_4/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
39.125 2.088 tINS RR 54 IOR17[A] clk_ibuf/O
39.369 0.244 tNET RR 1 R15C24[0][A] clkdiv_4/count_10_s0/CLK
38.969 -0.400 tSu 1 R15C24[0][A] clkdiv_4/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%
Arrival Data Path Delay cell: 3.850, 56.061%; route: 2.559, 37.265%; tC2Q: 0.458, 6.674%
Required Clock Path Delay cell: 2.088, 89.539%; route: 0.244, 10.461%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.708
Data Arrival Time 2.284
Data Required Time 1.577
From clkdiv_1/count_6_s0
To clkdiv_1/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C16[0][A] clkdiv_1/count_6_s0/CLK
1.910 0.333 tC2Q RR 3 R14C16[0][A] clkdiv_1/count_6_s0/Q
1.912 0.002 tNET RR 1 R14C16[0][A] clkdiv_1/n55_s2/I2
2.284 0.372 tINS RF 1 R14C16[0][A] clkdiv_1/n55_s2/F
2.284 0.000 tNET FF 1 R14C16[0][A] clkdiv_1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C16[0][A] clkdiv_1/count_6_s0/CLK
1.577 0.000 tHld 1 R14C16[0][A] clkdiv_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path2

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_4/count_3_s0
To clkdiv_4/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C25[1][A] clkdiv_4/count_3_s0/CLK
1.910 0.333 tC2Q RR 4 R14C25[1][A] clkdiv_4/count_3_s0/Q
1.913 0.004 tNET RR 1 R14C25[1][A] clkdiv_4/n58_s2/I0
2.285 0.372 tINS RF 1 R14C25[1][A] clkdiv_4/n58_s2/F
2.285 0.000 tNET FF 1 R14C25[1][A] clkdiv_4/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C25[1][A] clkdiv_4/count_3_s0/CLK
1.577 0.000 tHld 1 R14C25[1][A] clkdiv_4/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path3

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_4/count_15_s0
To clkdiv_4/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[1][A] clkdiv_4/count_15_s0/CLK
1.910 0.333 tC2Q RR 4 R15C25[1][A] clkdiv_4/count_15_s0/Q
1.913 0.004 tNET RR 1 R15C25[1][A] clkdiv_4/n46_s2/I0
2.285 0.372 tINS RF 1 R15C25[1][A] clkdiv_4/n46_s2/F
2.285 0.000 tNET FF 1 R15C25[1][A] clkdiv_4/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C25[1][A] clkdiv_4/count_15_s0/CLK
1.577 0.000 tHld 1 R15C25[1][A] clkdiv_4/count_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path4

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_3/count_6_s0
To clkdiv_3/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C19[0][A] clkdiv_3/count_6_s0/CLK
1.910 0.333 tC2Q RR 5 R16C19[0][A] clkdiv_3/count_6_s0/Q
1.913 0.004 tNET RR 1 R16C19[0][A] clkdiv_3/n55_s2/I2
2.285 0.372 tINS RF 1 R16C19[0][A] clkdiv_3/n55_s2/F
2.285 0.000 tNET FF 1 R16C19[0][A] clkdiv_3/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C19[0][A] clkdiv_3/count_6_s0/CLK
1.577 0.000 tHld 1 R16C19[0][A] clkdiv_3/count_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path5

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_3/count_10_s0
To clkdiv_3/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C18[1][A] clkdiv_3/count_10_s0/CLK
1.910 0.333 tC2Q RR 3 R16C18[1][A] clkdiv_3/count_10_s0/Q
1.913 0.004 tNET RR 1 R16C18[1][A] clkdiv_3/n51_s2/I0
2.285 0.372 tINS RF 1 R16C18[1][A] clkdiv_3/n51_s2/F
2.285 0.000 tNET FF 1 R16C18[1][A] clkdiv_3/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C18[1][A] clkdiv_3/count_10_s0/CLK
1.577 0.000 tHld 1 R16C18[1][A] clkdiv_3/count_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path6

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_3/count_12_s0
To clkdiv_3/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C15[0][A] clkdiv_3/count_12_s0/CLK
1.910 0.333 tC2Q RR 4 R16C15[0][A] clkdiv_3/count_12_s0/Q
1.913 0.004 tNET RR 1 R16C15[0][A] clkdiv_3/n49_s2/I2
2.285 0.372 tINS RF 1 R16C15[0][A] clkdiv_3/n49_s2/F
2.285 0.000 tNET FF 1 R16C15[0][A] clkdiv_3/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C15[0][A] clkdiv_3/count_12_s0/CLK
1.577 0.000 tHld 1 R16C15[0][A] clkdiv_3/count_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path7

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_2/count_0_s0
To clkdiv_2/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C17[0][A] clkdiv_2/count_0_s0/CLK
1.910 0.333 tC2Q RR 6 R15C17[0][A] clkdiv_2/count_0_s0/Q
1.913 0.004 tNET RR 1 R15C17[0][A] clkdiv_2/n61_s8/I0
2.285 0.372 tINS RF 1 R15C17[0][A] clkdiv_2/n61_s8/F
2.285 0.000 tNET FF 1 R15C17[0][A] clkdiv_2/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C17[0][A] clkdiv_2/count_0_s0/CLK
1.577 0.000 tHld 1 R15C17[0][A] clkdiv_2/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path8

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_1/count_4_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C18[1][A] clkdiv_1/count_4_s0/CLK
1.910 0.333 tC2Q RR 4 R14C18[1][A] clkdiv_1/count_4_s0/Q
1.913 0.004 tNET RR 1 R14C18[1][A] clkdiv_1/n57_s2/I2
2.285 0.372 tINS RF 1 R14C18[1][A] clkdiv_1/n57_s2/F
2.285 0.000 tNET FF 1 R14C18[1][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C18[1][A] clkdiv_1/count_4_s0/CLK
1.577 0.000 tHld 1 R14C18[1][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path9

Path Summary:

Slack 0.709
Data Arrival Time 2.285
Data Required Time 1.577
From clkdiv_1/count_7_s0
To clkdiv_1/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C16[1][A] clkdiv_1/count_7_s0/CLK
1.910 0.333 tC2Q RR 3 R14C16[1][A] clkdiv_1/count_7_s0/Q
1.913 0.004 tNET RR 1 R14C16[1][A] clkdiv_1/n54_s2/I2
2.285 0.372 tINS RF 1 R14C16[1][A] clkdiv_1/n54_s2/F
2.285 0.000 tNET FF 1 R14C16[1][A] clkdiv_1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C16[1][A] clkdiv_1/count_7_s0/CLK
1.577 0.000 tHld 1 R14C16[1][A] clkdiv_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path10

Path Summary:

Slack 0.709
Data Arrival Time 1.675
Data Required Time 0.966
From rx_1/count_3_s0
To rx_1/count_3_s0
Launch Clk clkbaudx2:[R]
Latch Clk clkbaudx2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkbaudx2
0.000 0.000 tCL RR 33 R15C17[1][A] clkdiv_2/clk_out_s0/Q
0.966 0.966 tNET RR 1 R14C28[0][A] rx_1/count_3_s0/CLK
1.299 0.333 tC2Q RR 3 R14C28[0][A] rx_1/count_3_s0/Q
1.303 0.004 tNET RR 1 R14C28[0][A] rx_1/n142_s7/I3
1.675 0.372 tINS RF 1 R14C28[0][A] rx_1/n142_s7/F
1.675 0.000 tNET FF 1 R14C28[0][A] rx_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkbaudx2
0.000 0.000 tCL RR 33 R15C17[1][A] clkdiv_2/clk_out_s0/Q
0.966 0.966 tNET RR 1 R14C28[0][A] rx_1/count_3_s0/CLK
0.966 0.000 tHld 1 R14C28[0][A] rx_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.966, 100.000%
Arrival Data Path Delay cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.966, 100.000%

Path11

Path Summary:

Slack 0.710
Data Arrival Time 1.676
Data Required Time 0.966
From rx_1/count_1_s0
To rx_1/count_1_s0
Launch Clk clkbaudx2:[R]
Latch Clk clkbaudx2:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkbaudx2
0.000 0.000 tCL RR 33 R15C17[1][A] clkdiv_2/clk_out_s0/Q
0.966 0.966 tNET RR 1 R14C26[0][A] rx_1/count_1_s0/CLK
1.299 0.333 tC2Q RR 4 R14C26[0][A] rx_1/count_1_s0/Q
1.304 0.005 tNET RR 1 R14C26[0][A] rx_1/n144_s8/I3
1.676 0.372 tINS RF 1 R14C26[0][A] rx_1/n144_s8/F
1.676 0.000 tNET FF 1 R14C26[0][A] rx_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkbaudx2
0.000 0.000 tCL RR 33 R15C17[1][A] clkdiv_2/clk_out_s0/Q
0.966 0.966 tNET RR 1 R14C26[0][A] rx_1/count_1_s0/CLK
0.966 0.000 tHld 1 R14C26[0][A] rx_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.966, 100.000%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.966, 100.000%

Path12

Path Summary:

Slack 0.710
Data Arrival Time 2.287
Data Required Time 1.577
From clkdiv_4/count_5_s0
To clkdiv_4/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C25[0][A] clkdiv_4/count_5_s0/CLK
1.910 0.333 tC2Q RR 6 R14C25[0][A] clkdiv_4/count_5_s0/Q
1.915 0.005 tNET RR 1 R14C25[0][A] clkdiv_4/n56_s2/I2
2.287 0.372 tINS RF 1 R14C25[0][A] clkdiv_4/n56_s2/F
2.287 0.000 tNET FF 1 R14C25[0][A] clkdiv_4/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C25[0][A] clkdiv_4/count_5_s0/CLK
1.577 0.000 tHld 1 R14C25[0][A] clkdiv_4/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path13

Path Summary:

Slack 0.710
Data Arrival Time 2.287
Data Required Time 1.577
From clkdiv_3/count_3_s0
To clkdiv_3/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C17[0][A] clkdiv_3/count_3_s0/CLK
1.910 0.333 tC2Q RR 4 R16C17[0][A] clkdiv_3/count_3_s0/Q
1.915 0.005 tNET RR 1 R16C17[0][A] clkdiv_3/n58_s2/I2
2.287 0.372 tINS RF 1 R16C17[0][A] clkdiv_3/n58_s2/F
2.287 0.000 tNET FF 1 R16C17[0][A] clkdiv_3/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C17[0][A] clkdiv_3/count_3_s0/CLK
1.577 0.000 tHld 1 R16C17[0][A] clkdiv_3/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path14

Path Summary:

Slack 0.710
Data Arrival Time 2.287
Data Required Time 1.577
From clkdiv_3/count_4_s0
To clkdiv_3/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C19[1][A] clkdiv_3/count_4_s0/CLK
1.910 0.333 tC2Q RR 9 R16C19[1][A] clkdiv_3/count_4_s0/Q
1.915 0.005 tNET RR 1 R16C19[1][A] clkdiv_3/n57_s2/I0
2.287 0.372 tINS RF 1 R16C19[1][A] clkdiv_3/n57_s2/F
2.287 0.000 tNET FF 1 R16C19[1][A] clkdiv_3/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C19[1][A] clkdiv_3/count_4_s0/CLK
1.577 0.000 tHld 1 R16C19[1][A] clkdiv_3/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path15

Path Summary:

Slack 0.710
Data Arrival Time 2.287
Data Required Time 1.577
From clkdiv_2/count_5_s0
To clkdiv_2/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C15[0][A] clkdiv_2/count_5_s0/CLK
1.910 0.333 tC2Q RR 4 R15C15[0][A] clkdiv_2/count_5_s0/Q
1.915 0.005 tNET RR 1 R15C15[0][A] clkdiv_2/n56_s2/I2
2.287 0.372 tINS RF 1 R15C15[0][A] clkdiv_2/n56_s2/F
2.287 0.000 tNET FF 1 R15C15[0][A] clkdiv_2/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R15C15[0][A] clkdiv_2/count_5_s0/CLK
1.577 0.000 tHld 1 R15C15[0][A] clkdiv_2/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path16

Path Summary:

Slack 0.710
Data Arrival Time 2.287
Data Required Time 1.577
From clkdiv_1/count_2_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C17[0][A] clkdiv_1/count_2_s0/CLK
1.910 0.333 tC2Q RR 6 R14C17[0][A] clkdiv_1/count_2_s0/Q
1.915 0.005 tNET RR 1 R14C17[0][A] clkdiv_1/n59_s4/I0
2.287 0.372 tINS RF 1 R14C17[0][A] clkdiv_1/n59_s4/F
2.287 0.000 tNET FF 1 R14C17[0][A] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C17[0][A] clkdiv_1/count_2_s0/CLK
1.577 0.000 tHld 1 R14C17[0][A] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path17

Path Summary:

Slack 0.711
Data Arrival Time 2.288
Data Required Time 1.577
From clkdiv_4/count_9_s0
To clkdiv_4/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C24[1][A] clkdiv_4/count_9_s0/CLK
1.910 0.333 tC2Q RR 5 R14C24[1][A] clkdiv_4/count_9_s0/Q
1.916 0.006 tNET RR 1 R14C24[1][A] clkdiv_4/n52_s2/I2
2.288 0.372 tINS RF 1 R14C24[1][A] clkdiv_4/n52_s2/F
2.288 0.000 tNET FF 1 R14C24[1][A] clkdiv_4/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C24[1][A] clkdiv_4/count_9_s0/CLK
1.577 0.000 tHld 1 R14C24[1][A] clkdiv_4/count_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path18

Path Summary:

Slack 0.711
Data Arrival Time 2.288
Data Required Time 1.577
From clkdiv_4/count_16_s0
To clkdiv_4/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C23[0][A] clkdiv_4/count_16_s0/CLK
1.910 0.333 tC2Q RR 6 R14C23[0][A] clkdiv_4/count_16_s0/Q
1.916 0.006 tNET RR 1 R14C23[0][A] clkdiv_4/n45_s3/I2
2.288 0.372 tINS RF 1 R14C23[0][A] clkdiv_4/n45_s3/F
2.288 0.000 tNET FF 1 R14C23[0][A] clkdiv_4/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C23[0][A] clkdiv_4/count_16_s0/CLK
1.577 0.000 tHld 1 R14C23[0][A] clkdiv_4/count_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path19

Path Summary:

Slack 0.711
Data Arrival Time 2.288
Data Required Time 1.577
From clkdiv_3/count_5_s0
To clkdiv_3/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C14[0][A] clkdiv_3/count_5_s0/CLK
1.910 0.333 tC2Q RR 7 R16C14[0][A] clkdiv_3/count_5_s0/Q
1.916 0.006 tNET RR 1 R16C14[0][A] clkdiv_3/n56_s2/I2
2.288 0.372 tINS RF 1 R16C14[0][A] clkdiv_3/n56_s2/F
2.288 0.000 tNET FF 1 R16C14[0][A] clkdiv_3/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C14[0][A] clkdiv_3/count_5_s0/CLK
1.577 0.000 tHld 1 R16C14[0][A] clkdiv_3/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path20

Path Summary:

Slack 0.712
Data Arrival Time 2.012
Data Required Time 1.300
From tx_1/state_1_s3
To tx_1/state_1_s3
Launch Clk clkbaud:[R]
Latch Clk clkbaud:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkbaud
0.000 0.000 tCL RR 21 R14C17[1][A] clkdiv_1/clk_out_s0/Q
1.300 1.300 tNET RR 1 R16C25[0][A] tx_1/state_1_s3/CLK
1.633 0.333 tC2Q RR 7 R16C25[0][A] tx_1/state_1_s3/Q
1.640 0.007 tNET RR 1 R16C25[0][A] tx_1/n26_s4/I1
2.012 0.372 tINS RF 1 R16C25[0][A] tx_1/n26_s4/F
2.012 0.000 tNET FF 1 R16C25[0][A] tx_1/state_1_s3/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clkbaud
0.000 0.000 tCL RR 21 R14C17[1][A] clkdiv_1/clk_out_s0/Q
1.300 1.300 tNET RR 1 R16C25[0][A] tx_1/state_1_s3/CLK
1.300 0.000 tHld 1 R16C25[0][A] tx_1/state_1_s3

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.300, 100.000%
Arrival Data Path Delay cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.300, 100.000%

Path21

Path Summary:

Slack 0.714
Data Arrival Time 2.033
Data Required Time 1.319
From mux7seg_1/col_1_s0
To mux7seg_1/col_1_s0
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R15C23[0][B] clkdiv_4/clk_out_s0/Q
1.319 1.319 tNET RR 1 R15C34[0][A] mux7seg_1/col_1_s0/CLK
1.652 0.333 tC2Q RR 12 R15C34[0][A] mux7seg_1/col_1_s0/Q
1.661 0.008 tNET RR 1 R15C34[0][A] mux7seg_1/n11_s2/I0
2.033 0.372 tINS RF 1 R15C34[0][A] mux7seg_1/n11_s2/F
2.033 0.000 tNET FF 1 R15C34[0][A] mux7seg_1/col_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R15C23[0][B] clkdiv_4/clk_out_s0/Q
1.319 1.319 tNET RR 1 R15C34[0][A] mux7seg_1/col_1_s0/CLK
1.319 0.000 tHld 1 R15C34[0][A] mux7seg_1/col_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 1.319, 100.000%
Arrival Data Path Delay cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712%
Required Clock Path Delay cell: 0.000, 0.000%; route: 1.319, 100.000%

Path22

Path Summary:

Slack 0.892
Data Arrival Time 2.468
Data Required Time 1.577
From clkdiv_1/count_1_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C18[2][A] clkdiv_1/count_1_s0/CLK
1.910 0.333 tC2Q RR 5 R14C18[2][A] clkdiv_1/count_1_s0/Q
1.912 0.002 tNET RR 1 R14C18[2][A] clkdiv_1/n60_s2/I1
2.468 0.556 tINS RR 1 R14C18[2][A] clkdiv_1/n60_s2/F
2.468 0.000 tNET RR 1 R14C18[2][A] clkdiv_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C18[2][A] clkdiv_1/count_1_s0/CLK
1.577 0.000 tHld 1 R14C18[2][A] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path23

Path Summary:

Slack 0.893
Data Arrival Time 2.469
Data Required Time 1.577
From clkdiv_4/count_1_s0
To clkdiv_4/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C25[2][A] clkdiv_4/count_1_s0/CLK
1.910 0.333 tC2Q RR 5 R14C25[2][A] clkdiv_4/count_1_s0/Q
1.913 0.004 tNET RR 1 R14C25[2][A] clkdiv_4/n60_s2/I1
2.469 0.556 tINS RR 1 R14C25[2][A] clkdiv_4/n60_s2/F
2.469 0.000 tNET RR 1 R14C25[2][A] clkdiv_4/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C25[2][A] clkdiv_4/count_1_s0/CLK
1.577 0.000 tHld 1 R14C25[2][A] clkdiv_4/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path24

Path Summary:

Slack 0.893
Data Arrival Time 2.469
Data Required Time 1.577
From clkdiv_4/count_7_s0
To clkdiv_4/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C24[2][A] clkdiv_4/count_7_s0/CLK
1.910 0.333 tC2Q RR 6 R14C24[2][A] clkdiv_4/count_7_s0/Q
1.913 0.004 tNET RR 1 R14C24[2][A] clkdiv_4/n54_s2/I0
2.469 0.556 tINS RR 1 R14C24[2][A] clkdiv_4/n54_s2/F
2.469 0.000 tNET RR 1 R14C24[2][A] clkdiv_4/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R14C24[2][A] clkdiv_4/count_7_s0/CLK
1.577 0.000 tHld 1 R14C24[2][A] clkdiv_4/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Path25

Path Summary:

Slack 0.893
Data Arrival Time 2.469
Data Required Time 1.577
From clkdiv_3/count_8_s0
To clkdiv_3/count_8_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C18[2][A] clkdiv_3/count_8_s0/CLK
1.910 0.333 tC2Q RR 4 R16C18[2][A] clkdiv_3/count_8_s0/Q
1.913 0.004 tNET RR 1 R16C18[2][A] clkdiv_3/n53_s2/I2
2.469 0.556 tINS RR 1 R16C18[2][A] clkdiv_3/n53_s2/F
2.469 0.000 tNET RR 1 R16C18[2][A] clkdiv_3/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOR17[A] clk_ibuf/I
1.392 1.392 tINS RR 54 IOR17[A] clk_ibuf/O
1.577 0.185 tNET RR 1 R16C18[2][A] clkdiv_3/count_8_s0/CLK
1.577 0.000 tHld 1 R16C18[2][A] clkdiv_3/count_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%
Arrival Data Path Delay cell: 0.556, 62.271%; route: 0.004, 0.397%; tC2Q: 0.333, 37.333%
Required Clock Path Delay cell: 1.392, 88.292%; route: 0.185, 11.708%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_7_s0/CLK

MPW2

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_5_s0/CLK

MPW3

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_1_s0/CLK

MPW4

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_2/count_1_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_2/count_1_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_2/count_1_s0/CLK

MPW5

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_3/count_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_3/count_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_3/count_3_s0/CLK

MPW6

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_3/count_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_3/count_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_3/count_4_s0/CLK

MPW7

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_2/count_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_2/count_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_2/count_2_s0/CLK

MPW8

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_3/count_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_3/count_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_3/count_5_s0/CLK

MPW9

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_3/count_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_3/count_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_3/count_6_s0/CLK

MPW10

MPW Summary:

Slack: 16.269
Actual Width: 17.519
Required Width: 1.250
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.094 0.262 tNET FF clkdiv_1/count_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.614 0.185 tNET RR clkdiv_1/count_2_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
54 clk_d 28.769 0.262
35 state[0] 4327.062 3.285
33 clkbaudx2hz 4323.965 1.726
21 clkbaudhz 8658.850 2.194
20 col[0] 6249987.000 1.817
17 n61_21 28.879 1.331
17 n61_15 29.482 0.875
15 state[0] 8662.251 0.858
13 clk160hz 6249987.000 2.358
12 col[1] 6249987.000 1.814

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R14C25 84.72%
R14C28 76.39%
R16C17 69.44%
R14C33 68.06%
R15C17 68.06%
R16C24 68.06%
R16C19 65.28%
R15C25 62.50%
R16C25 62.50%
R14C30 62.50%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clkbaud -source [get_ports {clk}] -master_clock clk27mhz -divide_by 234 [get_nets {clkbaudhz}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk400hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 67500 [get_nets {clk400hz}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk160hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 168750 [get_nets {clk160hz}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clkbaudx2 -source [get_ports {clk}] -master_clock clk27mhz -divide_by 117 [get_nets {clkbaudx2hz}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clk400hz}] -to [get_clocks {clkbaud}]
TC_FALSE_PATH Actived set_false_path -from [get_clocks {clkbaudx2}] -to [get_clocks {clk160hz}]