Timing Messages
Report Title | Timing Analysis Report |
Design File | C:\Gowin\SV_240812_mhut_2001\matrix_key\impl\gwsynthesis\matrix_key.vg |
Physical Constraints File | C:\Gowin\SV_240812_mhut_2001\matrix_key\src\matrix_key.cst |
Timing Constraint File | C:\Gowin\SV_240812_mhut_2001\matrix_key\src\matrix_key.sdc |
Tool Version | V1.9.10.01 (64-bit) |
Part Number | GW1NR-LV9QN88PC6/I5 |
Device | GW1NR-9 |
Device Version | C |
Created Time | Mon Aug 12 11:40:17 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C C6/I5 |
Hold Delay Model | Fast 1.26V 0C C6/I5 |
Numbers of Paths Analyzed | 278 |
Numbers of Endpoints Analyzed | 171 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | clk27mhz | Base | 37.037 | 27.000 | 0.000 | 18.518 | clk | ||
2 | clk50hz | Generated | 1481480.000 | 0.001 | 0.000 | 740740.000 | clk | clk27mhz | clk50hz |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk27mhz | 27.000(MHz) | 128.609(MHz) | 5 | TOP |
2 | clk50hz | 0.001(MHz) | 135.593(MHz) | 2 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk27mhz | Setup | 0.000 | 0 |
clk27mhz | Hold | 0.000 | 0 |
clk50hz | Setup | 0.000 | 0 |
clk50hz | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 29.262 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.375 |
2 | 29.262 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.375 |
3 | 29.351 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.286 |
4 | 29.413 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.224 |
5 | 29.413 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.224 |
6 | 29.413 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.224 |
7 | 29.413 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_9_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.224 |
8 | 29.418 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.219 |
9 | 29.458 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.179 |
10 | 29.477 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.160 |
11 | 29.835 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.802 |
12 | 29.861 | clkdiv_1/count_5_s0/Q | clkdiv_1/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.776 |
13 | 29.862 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_13_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.775 |
14 | 29.862 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_19_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.775 |
15 | 29.928 | clkdiv_1/count_5_s0/Q | clkdiv_1/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.709 |
16 | 30.161 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.476 |
17 | 30.276 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.361 |
18 | 30.302 | clkdiv_1/count_11_s0/Q | clkdiv_1/count_18_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.335 |
19 | 30.713 | clkdiv_1/count_11_s0/Q | clkdiv_1/clk_out_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 5.924 |
20 | 31.079 | clkdiv_1/count_11_s0/Q | clkdiv_1/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 5.558 |
21 | 31.348 | clkdiv_1/count_11_s0/Q | clkdiv_1/count_17_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 5.289 |
22 | 1481472.625 | matrix_key_1/index_2_s0/Q | matrix_key_1/tc_s0/D | clk50hz:[R] | clk50hz:[R] | 1481480.000 | 0.000 | 6.939 |
23 | 1481475.000 | matrix_key_1/index_2_s0/Q | matrix_key_1/col_0_s0/D | clk50hz:[R] | clk50hz:[R] | 1481480.000 | 0.000 | 4.677 |
24 | 1481475.000 | matrix_key_1/index_2_s0/Q | matrix_key_1/col_2_s0/D | clk50hz:[R] | clk50hz:[R] | 1481480.000 | 0.000 | 4.677 |
25 | 1481475.125 | matrix_key_1/index_2_s0/Q | matrix_key_1/col_1_s0/D | clk50hz:[R] | clk50hz:[R] | 1481480.000 | 0.000 | 4.507 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.708 | clkdiv_1/count_8_s0/Q | clkdiv_1/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
2 | 0.708 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
3 | 0.709 | clkdiv_1/count_0_s0/Q | clkdiv_1/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
4 | 0.709 | clkdiv_1/count_9_s0/Q | clkdiv_1/count_9_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
5 | 0.710 | matrix_key_1/index_0_s0/Q | matrix_key_1/index_0_s0/D | clk50hz:[R] | clk50hz:[R] | 0.000 | 0.000 | 0.710 |
6 | 0.710 | matrix_key_1/index_2_s0/Q | matrix_key_1/index_2_s0/D | clk50hz:[R] | clk50hz:[R] | 0.000 | 0.000 | 0.710 |
7 | 0.710 | clkdiv_1/count_4_s0/Q | clkdiv_1/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
8 | 0.710 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
9 | 0.710 | clkdiv_1/count_15_s0/Q | clkdiv_1/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
10 | 0.714 | clkdiv_1/count_19_s0/Q | clkdiv_1/count_19_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.714 |
11 | 0.892 | clkdiv_1/count_2_s0/Q | clkdiv_1/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.892 |
12 | 0.895 | clkdiv_1/count_13_s0/Q | clkdiv_1/count_13_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.895 |
13 | 0.937 | matrix_key_1/tmp_5_s1/Q | matrix_key_1/key_5_s0/D | clk50hz:[R] | clk50hz:[R] | 0.000 | 0.000 | 0.937 |
14 | 0.937 | matrix_key_1/tmp_12_s1/Q | matrix_key_1/key_12_s0/D | clk50hz:[R] | clk50hz:[R] | 0.000 | 0.000 | 0.937 |
15 | 0.937 | matrix_key_1/tmp_13_s1/Q | matrix_key_1/key_13_s0/D | clk50hz:[R] | clk50hz:[R] | 0.000 | 0.000 | 0.937 |
16 | 0.975 | clkdiv_1/count_13_s0/Q | clkdiv_1/clk_out_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.975 |
17 | 0.985 | clkdiv_1/count_19_s0/Q | clkdiv_1/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.985 |
18 | 1.060 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 1.060 |
19 | 1.060 | clkdiv_1/count_3_s0/Q | clkdiv_1/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 1.060 |
20 | 1.061 | clkdiv_1/count_18_s0/Q | clkdiv_1/count_18_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 1.061 |
21 | 1.062 | clkdiv_1/count_5_s0/Q | clkdiv_1/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 1.062 |
22 | 1.062 | clkdiv_1/count_7_s0/Q | clkdiv_1/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 1.062 |
23 | 1.062 | clkdiv_1/count_11_s0/Q | clkdiv_1/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 1.062 |
24 | 1.063 | matrix_key_1/index_1_s0/Q | matrix_key_1/index_1_s0/D | clk50hz:[R] | clk50hz:[R] | 0.000 | 0.000 | 1.063 |
25 | 1.064 | clkdiv_1/count_10_s0/Q | clkdiv_1/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 1.064 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_19_s0 |
2 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_17_s0 |
3 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_13_s0 |
4 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_5_s0 |
5 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_6_s0 |
6 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_14_s0 |
7 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_7_s0 |
8 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_8_s0 |
9 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_18_s0 |
10 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_15_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 29.262 |
Data Arrival Time | 9.707 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.885 | 1.209 | tNET | FF | 1 | R14C34[1][A] | clkdiv_1/n53_s4/I1 |
9.707 | 0.822 | tINS | FF | 1 | R14C34[1][A] | clkdiv_1/n53_s4/F |
9.707 | 0.000 | tNET | FF | 1 | R14C34[1][A] | clkdiv_1/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[1][A] | clkdiv_1/count_8_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C34[1][A] | clkdiv_1/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.979, 53.949%; route: 2.938, 39.837%; tC2Q: 0.458, 6.214% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path2
Path Summary:
Slack | 29.262 |
Data Arrival Time | 9.707 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_11_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.885 | 1.209 | tNET | FF | 1 | R14C34[0][B] | clkdiv_1/n50_s4/I1 |
9.707 | 0.822 | tINS | FF | 1 | R14C34[0][B] | clkdiv_1/n50_s4/F |
9.707 | 0.000 | tNET | FF | 1 | R14C34[0][B] | clkdiv_1/count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[0][B] | clkdiv_1/count_11_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C34[0][B] | clkdiv_1/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.979, 53.949%; route: 2.938, 39.837%; tC2Q: 0.458, 6.214% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path3
Path Summary:
Slack | 29.351 |
Data Arrival Time | 9.618 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_4_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.519 | 0.843 | tNET | FF | 1 | R14C32[1][A] | clkdiv_1/n57_s4/I1 |
9.618 | 1.099 | tINS | FF | 1 | R14C32[1][A] | clkdiv_1/n57_s4/F |
9.618 | 0.000 | tNET | FF | 1 | R14C32[1][A] | clkdiv_1/count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C32[1][A] | clkdiv_1/count_4_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C32[1][A] | clkdiv_1/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.256, 58.412%; route: 2.572, 35.297%; tC2Q: 0.458, 6.290% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path4
Path Summary:
Slack | 29.413 |
Data Arrival Time | 9.556 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.524 | 0.848 | tNET | FF | 1 | R15C34[0][A] | clkdiv_1/n61_s11/I0 |
9.556 | 1.032 | tINS | FF | 1 | R15C34[0][A] | clkdiv_1/n61_s11/F |
9.556 | 0.000 | tNET | FF | 1 | R15C34[0][A] | clkdiv_1/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C34[0][A] | clkdiv_1/count_0_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C34[0][A] | clkdiv_1/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.189, 57.990%; route: 2.576, 35.666%; tC2Q: 0.458, 6.345% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path5
Path Summary:
Slack | 29.413 |
Data Arrival Time | 9.556 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_5_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.524 | 0.848 | tNET | FF | 1 | R15C32[0][B] | clkdiv_1/n56_s4/I1 |
9.556 | 1.032 | tINS | FF | 1 | R15C32[0][B] | clkdiv_1/n56_s4/F |
9.556 | 0.000 | tNET | FF | 1 | R15C32[0][B] | clkdiv_1/count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C32[0][B] | clkdiv_1/count_5_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C32[0][B] | clkdiv_1/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.189, 57.990%; route: 2.576, 35.666%; tC2Q: 0.458, 6.345% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path6
Path Summary:
Slack | 29.413 |
Data Arrival Time | 9.556 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.524 | 0.848 | tNET | FF | 1 | R15C34[1][A] | clkdiv_1/n55_s5/I1 |
9.556 | 1.032 | tINS | FF | 1 | R15C34[1][A] | clkdiv_1/n55_s5/F |
9.556 | 0.000 | tNET | FF | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C34[1][A] | clkdiv_1/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.189, 57.990%; route: 2.576, 35.666%; tC2Q: 0.458, 6.345% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path7
Path Summary:
Slack | 29.413 |
Data Arrival Time | 9.556 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_9_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.524 | 0.848 | tNET | FF | 1 | R15C32[0][A] | clkdiv_1/n52_s5/I1 |
9.556 | 1.032 | tINS | FF | 1 | R15C32[0][A] | clkdiv_1/n52_s5/F |
9.556 | 0.000 | tNET | FF | 1 | R15C32[0][A] | clkdiv_1/count_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C32[0][A] | clkdiv_1/count_9_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C32[0][A] | clkdiv_1/count_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.189, 57.990%; route: 2.576, 35.666%; tC2Q: 0.458, 6.345% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path8
Path Summary:
Slack | 29.418 |
Data Arrival Time | 9.551 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.519 | 0.843 | tNET | FF | 1 | R14C32[0][B] | clkdiv_1/n60_s3/I1 |
9.551 | 1.032 | tINS | FF | 1 | R14C32[0][B] | clkdiv_1/n60_s3/F |
9.551 | 0.000 | tNET | FF | 1 | R14C32[0][B] | clkdiv_1/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C32[0][B] | clkdiv_1/count_1_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C32[0][B] | clkdiv_1/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.189, 58.026%; route: 2.572, 35.625%; tC2Q: 0.458, 6.349% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path9
Path Summary:
Slack | 29.458 |
Data Arrival Time | 9.511 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.885 | 1.209 | tNET | FF | 1 | R14C34[2][A] | clkdiv_1/n59_s4/I1 |
9.511 | 0.626 | tINS | FF | 1 | R14C34[2][A] | clkdiv_1/n59_s4/F |
9.511 | 0.000 | tNET | FF | 1 | R14C34[2][A] | clkdiv_1/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[2][A] | clkdiv_1/count_2_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C34[2][A] | clkdiv_1/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.783, 52.692%; route: 2.938, 40.924%; tC2Q: 0.458, 6.384% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path10
Path Summary:
Slack | 29.477 |
Data Arrival Time | 9.492 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.866 | 1.190 | tNET | FF | 1 | R14C34[1][B] | clkdiv_1/n58_s4/I1 |
9.492 | 0.626 | tINS | FF | 1 | R14C34[1][B] | clkdiv_1/n58_s4/F |
9.492 | 0.000 | tNET | FF | 1 | R14C34[1][B] | clkdiv_1/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[1][B] | clkdiv_1/count_3_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C34[1][B] | clkdiv_1/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.783, 52.836%; route: 2.919, 40.762%; tC2Q: 0.458, 6.401% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path11
Path Summary:
Slack | 29.835 |
Data Arrival Time | 9.134 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_7_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.508 | 0.832 | tNET | FF | 1 | R15C34[1][B] | clkdiv_1/n54_s5/I1 |
9.134 | 0.626 | tINS | FF | 1 | R15C34[1][B] | clkdiv_1/n54_s5/F |
9.134 | 0.000 | tNET | FF | 1 | R15C34[1][B] | clkdiv_1/count_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C34[1][B] | clkdiv_1/count_7_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C34[1][B] | clkdiv_1/count_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.783, 55.617%; route: 2.561, 37.644%; tC2Q: 0.458, 6.738% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path12
Path Summary:
Slack | 29.861 |
Data Arrival Time | 9.108 |
Data Required Time | 38.969 |
From | clkdiv_1/count_5_s0 |
To | clkdiv_1/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C32[0][B] | clkdiv_1/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C32[0][B] | clkdiv_1/count_5_s0/Q |
3.617 | 0.827 | tNET | FF | 1 | R14C33[0][B] | clkdiv_1/n52_s4/I0 |
4.716 | 1.099 | tINS | FF | 4 | R14C33[0][B] | clkdiv_1/n52_s4/F |
5.530 | 0.814 | tNET | FF | 1 | R16C33[0][A] | clkdiv_1/n49_s3/I3 |
6.562 | 1.032 | tINS | FF | 3 | R16C33[0][A] | clkdiv_1/n49_s3/F |
6.579 | 0.016 | tNET | FF | 1 | R16C33[2][A] | clkdiv_1/n45_s3/I3 |
7.205 | 0.626 | tINS | FF | 1 | R16C33[2][A] | clkdiv_1/n45_s3/F |
8.009 | 0.804 | tNET | FF | 1 | R16C32[1][A] | clkdiv_1/n45_s4/I0 |
9.108 | 1.099 | tINS | FF | 1 | R16C32[1][A] | clkdiv_1/n45_s4/F |
9.108 | 0.000 | tNET | FF | 1 | R16C32[1][A] | clkdiv_1/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R16C32[1][A] | clkdiv_1/count_16_s0/CLK |
38.969 | -0.400 | tSu | 1 | R16C32[1][A] | clkdiv_1/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.856, 56.906%; route: 2.462, 36.330%; tC2Q: 0.458, 6.764% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path13
Path Summary:
Slack | 29.862 |
Data Arrival Time | 9.107 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_13_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.638 | 1.061 | tINS | RR | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.075 | 0.436 | tNET | RR | 1 | R16C34[2][A] | clkdiv_1/n48_s4/I1 |
9.107 | 1.032 | tINS | RF | 1 | R16C34[2][A] | clkdiv_1/n48_s4/F |
9.107 | 0.000 | tNET | FF | 1 | R16C34[2][A] | clkdiv_1/count_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R16C34[2][A] | clkdiv_1/count_13_s0/CLK |
38.969 | -0.400 | tSu | 1 | R16C34[2][A] | clkdiv_1/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.151, 61.273%; route: 2.165, 31.961%; tC2Q: 0.458, 6.765% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path14
Path Summary:
Slack | 29.862 |
Data Arrival Time | 9.107 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_19_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.638 | 1.061 | tINS | RR | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.075 | 0.436 | tNET | RR | 1 | R16C34[0][A] | clkdiv_1/n42_s3/I2 |
9.107 | 1.032 | tINS | RF | 1 | R16C34[0][A] | clkdiv_1/n42_s3/F |
9.107 | 0.000 | tNET | FF | 1 | R16C34[0][A] | clkdiv_1/count_19_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R16C34[0][A] | clkdiv_1/count_19_s0/CLK |
38.969 | -0.400 | tSu | 1 | R16C34[0][A] | clkdiv_1/count_19_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.151, 61.273%; route: 2.165, 31.961%; tC2Q: 0.458, 6.765% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path15
Path Summary:
Slack | 29.928 |
Data Arrival Time | 9.041 |
Data Required Time | 38.969 |
From | clkdiv_1/count_5_s0 |
To | clkdiv_1/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C32[0][B] | clkdiv_1/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C32[0][B] | clkdiv_1/count_5_s0/Q |
3.617 | 0.827 | tNET | FF | 1 | R14C33[0][B] | clkdiv_1/n52_s4/I0 |
4.716 | 1.099 | tINS | FF | 4 | R14C33[0][B] | clkdiv_1/n52_s4/F |
5.530 | 0.814 | tNET | FF | 1 | R16C33[0][A] | clkdiv_1/n49_s3/I3 |
6.562 | 1.032 | tINS | FF | 3 | R16C33[0][A] | clkdiv_1/n49_s3/F |
6.579 | 0.016 | tNET | FF | 1 | R16C33[2][B] | clkdiv_1/n46_s3/I3 |
7.205 | 0.626 | tINS | FF | 1 | R16C33[2][B] | clkdiv_1/n46_s3/F |
8.009 | 0.804 | tNET | FF | 1 | R14C34[0][A] | clkdiv_1/n46_s5/I1 |
9.041 | 1.032 | tINS | FF | 1 | R14C34[0][A] | clkdiv_1/n46_s5/F |
9.041 | 0.000 | tNET | FF | 1 | R14C34[0][A] | clkdiv_1/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[0][A] | clkdiv_1/count_15_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C34[0][A] | clkdiv_1/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.789, 56.476%; route: 2.462, 36.693%; tC2Q: 0.458, 6.832% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path16
Path Summary:
Slack | 30.161 |
Data Arrival Time | 8.808 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_12_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.676 | 1.099 | tINS | RF | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
7.709 | 0.033 | tNET | FF | 1 | R16C33[1][A] | clkdiv_1/n49_s5/I1 |
8.808 | 1.099 | tINS | FF | 1 | R16C33[1][A] | clkdiv_1/n49_s5/F |
8.808 | 0.000 | tNET | FF | 1 | R16C33[1][A] | clkdiv_1/count_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R16C33[1][A] | clkdiv_1/count_12_s0/CLK |
38.969 | -0.400 | tSu | 1 | R16C33[1][A] | clkdiv_1/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.256, 65.720%; route: 1.762, 27.203%; tC2Q: 0.458, 7.077% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path17
Path Summary:
Slack | 30.276 |
Data Arrival Time | 8.693 |
Data Required Time | 38.969 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
4.095 | 1.304 | tNET | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/I0 |
5.127 | 1.032 | tINS | FF | 1 | R15C33[3][B] | clkdiv_1/n61_s8/F |
5.132 | 0.005 | tNET | FF | 1 | R15C33[0][A] | clkdiv_1/n61_s5/I3 |
6.158 | 1.026 | tINS | FR | 1 | R15C33[0][A] | clkdiv_1/n61_s5/F |
6.577 | 0.419 | tNET | RR | 1 | R16C33[1][B] | clkdiv_1/n61_s10/I1 |
7.638 | 1.061 | tINS | RR | 15 | R16C33[1][B] | clkdiv_1/n61_s10/F |
8.067 | 0.429 | tNET | RR | 1 | R15C33[2][B] | clkdiv_1/n51_s5/I1 |
8.693 | 0.626 | tINS | RF | 1 | R15C33[2][B] | clkdiv_1/n51_s5/F |
8.693 | 0.000 | tNET | FF | 1 | R15C33[2][B] | clkdiv_1/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C33[2][B] | clkdiv_1/count_10_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C33[2][B] | clkdiv_1/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.745, 58.878%; route: 2.157, 33.917%; tC2Q: 0.458, 7.206% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path18
Path Summary:
Slack | 30.302 |
Data Arrival Time | 8.667 |
Data Required Time | 38.969 |
From | clkdiv_1/count_11_s0 |
To | clkdiv_1/count_18_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R14C34[0][B] | clkdiv_1/count_11_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R14C34[0][B] | clkdiv_1/count_11_s0/Q |
3.606 | 0.815 | tNET | FF | 1 | R15C33[3][A] | clkdiv_1/n63_s78/I2 |
4.705 | 1.099 | tINS | FF | 3 | R15C33[3][A] | clkdiv_1/n63_s78/F |
5.541 | 0.836 | tNET | FF | 1 | R16C33[3][A] | clkdiv_1/n48_s3/I1 |
6.567 | 1.026 | tINS | FR | 4 | R16C33[3][A] | clkdiv_1/n48_s3/F |
6.995 | 0.429 | tNET | RR | 1 | R16C34[3][A] | clkdiv_1/n43_s3/I1 |
7.620 | 0.625 | tINS | RR | 2 | R16C34[3][A] | clkdiv_1/n43_s3/F |
8.041 | 0.421 | tNET | RR | 1 | R15C34[0][B] | clkdiv_1/n43_s5/I2 |
8.667 | 0.626 | tINS | RF | 1 | R15C34[0][B] | clkdiv_1/n43_s5/F |
8.667 | 0.000 | tNET | FF | 1 | R15C34[0][B] | clkdiv_1/count_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C34[0][B] | clkdiv_1/count_18_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C34[0][B] | clkdiv_1/count_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.376, 53.289%; route: 2.501, 39.477%; tC2Q: 0.458, 7.235% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path19
Path Summary:
Slack | 30.713 |
Data Arrival Time | 8.256 |
Data Required Time | 38.969 |
From | clkdiv_1/count_11_s0 |
To | clkdiv_1/clk_out_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R14C34[0][B] | clkdiv_1/count_11_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R14C34[0][B] | clkdiv_1/count_11_s0/Q |
3.606 | 0.815 | tNET | FF | 1 | R15C33[3][A] | clkdiv_1/n63_s78/I2 |
4.705 | 1.099 | tINS | FF | 3 | R15C33[3][A] | clkdiv_1/n63_s78/F |
5.514 | 0.810 | tNET | FF | 1 | R14C33[2][B] | clkdiv_1/n63_s75/I2 |
6.336 | 0.822 | tINS | FF | 1 | R14C33[2][B] | clkdiv_1/n63_s75/F |
7.157 | 0.821 | tNET | FF | 1 | R14C34[2][B] | clkdiv_1/n63_s83/I1 |
8.256 | 1.099 | tINS | FF | 1 | R14C34[2][B] | clkdiv_1/n63_s83/F |
8.256 | 0.000 | tNET | FF | 1 | R14C34[2][B] | clkdiv_1/clk_out_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C34[2][B] | clkdiv_1/clk_out_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C34[2][B] | clkdiv_1/clk_out_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.020, 50.977%; route: 2.446, 41.287%; tC2Q: 0.458, 7.737% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path20
Path Summary:
Slack | 31.079 |
Data Arrival Time | 7.890 |
Data Required Time | 38.969 |
From | clkdiv_1/count_11_s0 |
To | clkdiv_1/count_14_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R14C34[0][B] | clkdiv_1/count_11_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R14C34[0][B] | clkdiv_1/count_11_s0/Q |
3.606 | 0.815 | tNET | FF | 1 | R15C33[3][A] | clkdiv_1/n63_s78/I2 |
4.705 | 1.099 | tINS | FF | 3 | R15C33[3][A] | clkdiv_1/n63_s78/F |
5.541 | 0.836 | tNET | FF | 1 | R16C33[3][A] | clkdiv_1/n48_s3/I1 |
6.573 | 1.032 | tINS | FF | 4 | R16C33[3][A] | clkdiv_1/n48_s3/F |
7.068 | 0.496 | tNET | FF | 1 | R16C32[0][B] | clkdiv_1/n47_s3/I1 |
7.890 | 0.822 | tINS | FF | 1 | R16C32[0][B] | clkdiv_1/n47_s3/F |
7.890 | 0.000 | tNET | FF | 1 | R16C32[0][B] | clkdiv_1/count_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R16C32[0][B] | clkdiv_1/count_14_s0/CLK |
38.969 | -0.400 | tSu | 1 | R16C32[0][B] | clkdiv_1/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 2.953, 53.128%; route: 2.147, 38.626%; tC2Q: 0.458, 8.246% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path21
Path Summary:
Slack | 31.348 |
Data Arrival Time | 7.621 |
Data Required Time | 38.969 |
From | clkdiv_1/count_11_s0 |
To | clkdiv_1/count_17_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R14C34[0][B] | clkdiv_1/count_11_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R14C34[0][B] | clkdiv_1/count_11_s0/Q |
3.606 | 0.815 | tNET | FF | 1 | R15C33[3][A] | clkdiv_1/n63_s78/I2 |
4.705 | 1.099 | tINS | FF | 3 | R15C33[3][A] | clkdiv_1/n63_s78/F |
5.541 | 0.836 | tNET | FF | 1 | R16C33[3][A] | clkdiv_1/n48_s3/I1 |
6.567 | 1.026 | tINS | FR | 4 | R16C33[3][A] | clkdiv_1/n48_s3/F |
6.995 | 0.429 | tNET | RR | 1 | R16C34[0][B] | clkdiv_1/n44_s4/I0 |
7.621 | 0.626 | tINS | RF | 1 | R16C34[0][B] | clkdiv_1/n44_s4/F |
7.621 | 0.000 | tNET | FF | 1 | R16C34[0][B] | clkdiv_1/count_17_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R16C34[0][B] | clkdiv_1/count_17_s0/CLK |
38.969 | -0.400 | tSu | 1 | R16C34[0][B] | clkdiv_1/count_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 2.751, 52.009%; route: 2.080, 39.326%; tC2Q: 0.458, 8.665% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path22
Path Summary:
Slack | 1481472.625 |
Data Arrival Time | 8.750 |
Data Required Time | 1481481.375 |
From | matrix_key_1/index_2_s0 |
To | matrix_key_1/tc_s0 |
Launch Clk | clk50hz:[R] |
Latch Clk | clk50hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.776 | 1.776 | tNET | RR | 1 | R14C24[1][A] | matrix_key_1/index_2_s0/CLK |
2.235 | 0.458 | tC2Q | RF | 10 | R14C24[1][A] | matrix_key_1/index_2_s0/Q |
3.539 | 1.304 | tNET | FF | 1 | R15C21[0][A] | matrix_key_1/key_15_s2/I2 |
4.638 | 1.099 | tINS | FF | 17 | R15C21[0][A] | matrix_key_1/key_15_s2/F |
8.715 | 4.077 | tNET | FF | 1 | IOT42[A] | matrix_key_1/tc_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1481480.000 | 1481480.000 | active clock edge time | ||||
1481480.000 | 0.000 | clk50hz | ||||
1481480.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1481481.750 | 1.776 | tNET | RR | 1 | IOT42[A] | matrix_key_1/tc_s0/CLK |
1481481.375 | -0.400 | tSu | 1 | IOT42[A] | matrix_key_1/tc_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 1481480.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.776, 100.000% |
Arrival Data Path Delay | cell: 1.099, 15.838%; route: 5.382, 77.557%; tC2Q: 0.458, 6.605% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.776, 100.000% |
Path23
Path Summary:
Slack | 1481475.000 |
Data Arrival Time | 6.375 |
Data Required Time | 1481481.375 |
From | matrix_key_1/index_2_s0 |
To | matrix_key_1/col_0_s0 |
Launch Clk | clk50hz:[R] |
Latch Clk | clk50hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.776 | 1.776 | tNET | RR | 1 | R14C24[1][A] | matrix_key_1/index_2_s0/CLK |
2.235 | 0.458 | tC2Q | RR | 10 | R14C24[1][A] | matrix_key_1/index_2_s0/Q |
2.670 | 0.435 | tNET | RR | 1 | R15C24[2][B] | matrix_key_1/n30_s5/I1 |
3.702 | 1.032 | tINS | RF | 1 | R15C24[2][B] | matrix_key_1/n30_s5/F |
6.453 | 2.752 | tNET | FF | 1 | IOB31[B] | matrix_key_1/col_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1481480.000 | 1481480.000 | active clock edge time | ||||
1481480.000 | 0.000 | clk50hz | ||||
1481480.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1481481.750 | 1.776 | tNET | RR | 1 | IOB31[B] | matrix_key_1/col_0_s0/CLK |
1481481.375 | -0.400 | tSu | 1 | IOB31[B] | matrix_key_1/col_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 1481480.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.776, 100.000% |
Arrival Data Path Delay | cell: 1.032, 22.065%; route: 3.187, 68.136%; tC2Q: 0.458, 9.800% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.776, 100.000% |
Path24
Path Summary:
Slack | 1481475.000 |
Data Arrival Time | 6.375 |
Data Required Time | 1481481.375 |
From | matrix_key_1/index_2_s0 |
To | matrix_key_1/col_2_s0 |
Launch Clk | clk50hz:[R] |
Latch Clk | clk50hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.776 | 1.776 | tNET | RR | 1 | R14C24[1][A] | matrix_key_1/index_2_s0/CLK |
2.235 | 0.458 | tC2Q | RR | 10 | R14C24[1][A] | matrix_key_1/index_2_s0/Q |
2.670 | 0.435 | tNET | RR | 1 | R15C24[3][B] | matrix_key_1/n27_s7/I1 |
3.702 | 1.032 | tINS | RF | 1 | R15C24[3][B] | matrix_key_1/n27_s7/F |
6.453 | 2.752 | tNET | FF | 1 | IOB29[B] | matrix_key_1/col_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1481480.000 | 1481480.000 | active clock edge time | ||||
1481480.000 | 0.000 | clk50hz | ||||
1481480.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1481481.750 | 1.776 | tNET | RR | 1 | IOB29[B] | matrix_key_1/col_2_s0/CLK |
1481481.375 | -0.400 | tSu | 1 | IOB29[B] | matrix_key_1/col_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 1481480.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.776, 100.000% |
Arrival Data Path Delay | cell: 1.032, 22.065%; route: 3.187, 68.136%; tC2Q: 0.458, 9.800% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.776, 100.000% |
Path25
Path Summary:
Slack | 1481475.125 |
Data Arrival Time | 6.250 |
Data Required Time | 1481481.375 |
From | matrix_key_1/index_2_s0 |
To | matrix_key_1/col_1_s0 |
Launch Clk | clk50hz:[R] |
Latch Clk | clk50hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.776 | 1.776 | tNET | RR | 1 | R14C24[1][A] | matrix_key_1/index_2_s0/CLK |
2.235 | 0.458 | tC2Q | RR | 10 | R14C24[1][A] | matrix_key_1/index_2_s0/Q |
2.670 | 0.435 | tNET | RR | 1 | R15C24[3][A] | matrix_key_1/n28_s7/I0 |
3.702 | 1.032 | tINS | RF | 1 | R15C24[3][A] | matrix_key_1/n28_s7/F |
6.283 | 2.581 | tNET | FF | 1 | IOB31[A] | matrix_key_1/col_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1481480.000 | 1481480.000 | active clock edge time | ||||
1481480.000 | 0.000 | clk50hz | ||||
1481480.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1481481.750 | 1.776 | tNET | RR | 1 | IOB31[A] | matrix_key_1/col_1_s0/CLK |
1481481.375 | -0.400 | tSu | 1 | IOB31[A] | matrix_key_1/col_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 1481480.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.776, 100.000% |
Arrival Data Path Delay | cell: 1.032, 22.898%; route: 3.017, 66.932%; tC2Q: 0.458, 10.170% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.776, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_1/count_8_s0 |
To | clkdiv_1/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[1][A] | clkdiv_1/count_8_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R14C34[1][A] | clkdiv_1/count_8_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R14C34[1][A] | clkdiv_1/n53_s4/I3 |
2.284 | 0.372 | tINS | RF | 1 | R14C34[1][A] | clkdiv_1/n53_s4/F |
2.284 | 0.000 | tNET | FF | 1 | R14C34[1][A] | clkdiv_1/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[1][A] | clkdiv_1/count_8_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C34[1][A] | clkdiv_1/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path2
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_1/count_16_s0 |
To | clkdiv_1/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C32[1][A] | clkdiv_1/count_16_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R16C32[1][A] | clkdiv_1/count_16_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R16C32[1][A] | clkdiv_1/n45_s4/I2 |
2.284 | 0.372 | tINS | RF | 1 | R16C32[1][A] | clkdiv_1/n45_s4/F |
2.284 | 0.000 | tNET | FF | 1 | R16C32[1][A] | clkdiv_1/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C32[1][A] | clkdiv_1/count_16_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C32[1][A] | clkdiv_1/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path3
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_0_s0 |
To | clkdiv_1/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C34[0][A] | clkdiv_1/count_0_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R15C34[0][A] | clkdiv_1/count_0_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R15C34[0][A] | clkdiv_1/n61_s11/I2 |
2.285 | 0.372 | tINS | RF | 1 | R15C34[0][A] | clkdiv_1/n61_s11/F |
2.285 | 0.000 | tNET | FF | 1 | R15C34[0][A] | clkdiv_1/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C34[0][A] | clkdiv_1/count_0_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C34[0][A] | clkdiv_1/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path4
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_9_s0 |
To | clkdiv_1/count_9_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C32[0][A] | clkdiv_1/count_9_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R15C32[0][A] | clkdiv_1/count_9_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R15C32[0][A] | clkdiv_1/n52_s5/I2 |
2.285 | 0.372 | tINS | RF | 1 | R15C32[0][A] | clkdiv_1/n52_s5/F |
2.285 | 0.000 | tNET | FF | 1 | R15C32[0][A] | clkdiv_1/count_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C32[0][A] | clkdiv_1/count_9_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C32[0][A] | clkdiv_1/count_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path5
Path Summary:
Slack | 0.710 |
Data Arrival Time | 1.959 |
Data Required Time | 1.249 |
From | matrix_key_1/index_0_s0 |
To | matrix_key_1/index_0_s0 |
Launch Clk | clk50hz:[R] |
Latch Clk | clk50hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C20[1][A] | matrix_key_1/index_0_s0/CLK |
1.582 | 0.333 | tC2Q | RR | 12 | R14C20[1][A] | matrix_key_1/index_0_s0/Q |
1.587 | 0.005 | tNET | RR | 1 | R14C20[1][A] | matrix_key_1/n137_s2/I0 |
1.959 | 0.372 | tINS | RF | 1 | R14C20[1][A] | matrix_key_1/n137_s2/F |
1.959 | 0.000 | tNET | FF | 1 | R14C20[1][A] | matrix_key_1/index_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C20[1][A] | matrix_key_1/index_0_s0/CLK |
1.249 | 0.000 | tHld | 1 | R14C20[1][A] | matrix_key_1/index_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Path6
Path Summary:
Slack | 0.710 |
Data Arrival Time | 1.959 |
Data Required Time | 1.249 |
From | matrix_key_1/index_2_s0 |
To | matrix_key_1/index_2_s0 |
Launch Clk | clk50hz:[R] |
Latch Clk | clk50hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C24[1][A] | matrix_key_1/index_2_s0/CLK |
1.582 | 0.333 | tC2Q | RR | 10 | R14C24[1][A] | matrix_key_1/index_2_s0/Q |
1.587 | 0.005 | tNET | RR | 1 | R14C24[1][A] | matrix_key_1/n135_s0/I2 |
1.959 | 0.372 | tINS | RF | 1 | R14C24[1][A] | matrix_key_1/n135_s0/F |
1.959 | 0.000 | tNET | FF | 1 | R14C24[1][A] | matrix_key_1/index_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C24[1][A] | matrix_key_1/index_2_s0/CLK |
1.249 | 0.000 | tHld | 1 | R14C24[1][A] | matrix_key_1/index_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Path7
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_1/count_4_s0 |
To | clkdiv_1/count_4_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C32[1][A] | clkdiv_1/count_4_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 10 | R14C32[1][A] | clkdiv_1/count_4_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R14C32[1][A] | clkdiv_1/n57_s4/I3 |
2.287 | 0.372 | tINS | RF | 1 | R14C32[1][A] | clkdiv_1/n57_s4/F |
2.287 | 0.000 | tNET | FF | 1 | R14C32[1][A] | clkdiv_1/count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C32[1][A] | clkdiv_1/count_4_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C32[1][A] | clkdiv_1/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path8
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 7 | R15C34[1][A] | clkdiv_1/count_6_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/n55_s5/I3 |
2.287 | 0.372 | tINS | RF | 1 | R15C34[1][A] | clkdiv_1/n55_s5/F |
2.287 | 0.000 | tNET | FF | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C34[1][A] | clkdiv_1/count_6_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C34[1][A] | clkdiv_1/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path9
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_1/count_15_s0 |
To | clkdiv_1/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[0][A] | clkdiv_1/count_15_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R14C34[0][A] | clkdiv_1/count_15_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R14C34[0][A] | clkdiv_1/n46_s5/I2 |
2.287 | 0.372 | tINS | RF | 1 | R14C34[0][A] | clkdiv_1/n46_s5/F |
2.287 | 0.000 | tNET | FF | 1 | R14C34[0][A] | clkdiv_1/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[0][A] | clkdiv_1/count_15_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C34[0][A] | clkdiv_1/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path10
Path Summary:
Slack | 0.714 |
Data Arrival Time | 2.290 |
Data Required Time | 1.577 |
From | clkdiv_1/count_19_s0 |
To | clkdiv_1/count_19_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C34[0][A] | clkdiv_1/count_19_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 21 | R16C34[0][A] | clkdiv_1/count_19_s0/Q |
1.918 | 0.008 | tNET | RR | 1 | R16C34[0][A] | clkdiv_1/n42_s3/I3 |
2.290 | 0.372 | tINS | RF | 1 | R16C34[0][A] | clkdiv_1/n42_s3/F |
2.290 | 0.000 | tNET | FF | 1 | R16C34[0][A] | clkdiv_1/count_19_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C34[0][A] | clkdiv_1/count_19_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C34[0][A] | clkdiv_1/count_19_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.130%; route: 0.008, 1.158%; tC2Q: 0.333, 46.712% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path11
Path Summary:
Slack | 0.892 |
Data Arrival Time | 2.468 |
Data Required Time | 1.577 |
From | clkdiv_1/count_2_s0 |
To | clkdiv_1/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[2][A] | clkdiv_1/count_2_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R14C34[2][A] | clkdiv_1/count_2_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R14C34[2][A] | clkdiv_1/n59_s4/I3 |
2.468 | 0.556 | tINS | RR | 1 | R14C34[2][A] | clkdiv_1/n59_s4/F |
2.468 | 0.000 | tNET | RR | 1 | R14C34[2][A] | clkdiv_1/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[2][A] | clkdiv_1/count_2_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C34[2][A] | clkdiv_1/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path12
Path Summary:
Slack | 0.895 |
Data Arrival Time | 2.472 |
Data Required Time | 1.577 |
From | clkdiv_1/count_13_s0 |
To | clkdiv_1/count_13_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C34[2][A] | clkdiv_1/count_13_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 8 | R16C34[2][A] | clkdiv_1/count_13_s0/Q |
1.916 | 0.006 | tNET | RR | 1 | R16C34[2][A] | clkdiv_1/n48_s4/I2 |
2.472 | 0.556 | tINS | RR | 1 | R16C34[2][A] | clkdiv_1/n48_s4/F |
2.472 | 0.000 | tNET | RR | 1 | R16C34[2][A] | clkdiv_1/count_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C34[2][A] | clkdiv_1/count_13_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C34[2][A] | clkdiv_1/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.556, 62.107%; route: 0.006, 0.659%; tC2Q: 0.333, 37.234% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path13
Path Summary:
Slack | 0.937 |
Data Arrival Time | 2.185 |
Data Required Time | 1.249 |
From | matrix_key_1/tmp_5_s1 |
To | matrix_key_1/key_5_s0 |
Launch Clk | clk50hz:[R] |
Latch Clk | clk50hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C21[2][A] | matrix_key_1/tmp_5_s1/CLK |
1.582 | 0.333 | tC2Q | RF | 1 | R14C21[2][A] | matrix_key_1/tmp_5_s1/Q |
1.813 | 0.231 | tNET | FF | 1 | R14C22[0][A] | matrix_key_1/n112_s3/I0 |
2.185 | 0.372 | tINS | FF | 1 | R14C22[0][A] | matrix_key_1/n112_s3/F |
2.185 | 0.000 | tNET | FF | 1 | R14C22[0][A] | matrix_key_1/key_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C22[0][A] | matrix_key_1/key_5_s0/CLK |
1.249 | 0.000 | tHld | 1 | R14C22[0][A] | matrix_key_1/key_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Arrival Data Path Delay | cell: 0.372, 39.719%; route: 0.231, 24.691%; tC2Q: 0.333, 35.590% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Path14
Path Summary:
Slack | 0.937 |
Data Arrival Time | 2.185 |
Data Required Time | 1.249 |
From | matrix_key_1/tmp_12_s1 |
To | matrix_key_1/key_12_s0 |
Launch Clk | clk50hz:[R] |
Latch Clk | clk50hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C22[2][A] | matrix_key_1/tmp_12_s1/CLK |
1.582 | 0.333 | tC2Q | RF | 1 | R14C22[2][A] | matrix_key_1/tmp_12_s1/Q |
1.813 | 0.231 | tNET | FF | 1 | R14C23[0][B] | matrix_key_1/n105_s3/I0 |
2.185 | 0.372 | tINS | FF | 1 | R14C23[0][B] | matrix_key_1/n105_s3/F |
2.185 | 0.000 | tNET | FF | 1 | R14C23[0][B] | matrix_key_1/key_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C23[0][B] | matrix_key_1/key_12_s0/CLK |
1.249 | 0.000 | tHld | 1 | R14C23[0][B] | matrix_key_1/key_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Arrival Data Path Delay | cell: 0.372, 39.719%; route: 0.231, 24.691%; tC2Q: 0.333, 35.590% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Path15
Path Summary:
Slack | 0.937 |
Data Arrival Time | 2.185 |
Data Required Time | 1.249 |
From | matrix_key_1/tmp_13_s1 |
To | matrix_key_1/key_13_s0 |
Launch Clk | clk50hz:[R] |
Latch Clk | clk50hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C24[2][A] | matrix_key_1/tmp_13_s1/CLK |
1.582 | 0.333 | tC2Q | RF | 1 | R14C24[2][A] | matrix_key_1/tmp_13_s1/Q |
1.813 | 0.231 | tNET | FF | 1 | R14C25[0][A] | matrix_key_1/n104_s3/I0 |
2.185 | 0.372 | tINS | FF | 1 | R14C25[0][A] | matrix_key_1/n104_s3/F |
2.185 | 0.000 | tNET | FF | 1 | R14C25[0][A] | matrix_key_1/key_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C25[0][A] | matrix_key_1/key_13_s0/CLK |
1.249 | 0.000 | tHld | 1 | R14C25[0][A] | matrix_key_1/key_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Arrival Data Path Delay | cell: 0.372, 39.719%; route: 0.231, 24.691%; tC2Q: 0.333, 35.590% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Path16
Path Summary:
Slack | 0.975 |
Data Arrival Time | 2.552 |
Data Required Time | 1.577 |
From | clkdiv_1/count_13_s0 |
To | clkdiv_1/clk_out_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C34[2][A] | clkdiv_1/count_13_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 8 | R16C34[2][A] | clkdiv_1/count_13_s0/Q |
2.180 | 0.270 | tNET | RR | 1 | R14C34[2][B] | clkdiv_1/n63_s83/I0 |
2.552 | 0.372 | tINS | RF | 1 | R14C34[2][B] | clkdiv_1/n63_s83/F |
2.552 | 0.000 | tNET | FF | 1 | R14C34[2][B] | clkdiv_1/clk_out_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[2][B] | clkdiv_1/clk_out_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C34[2][B] | clkdiv_1/clk_out_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 38.154%; route: 0.270, 27.657%; tC2Q: 0.333, 34.189% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path17
Path Summary:
Slack | 0.985 |
Data Arrival Time | 2.561 |
Data Required Time | 1.577 |
From | clkdiv_1/count_19_s0 |
To | clkdiv_1/count_14_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C34[0][A] | clkdiv_1/count_19_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 21 | R16C34[0][A] | clkdiv_1/count_19_s0/Q |
2.189 | 0.280 | tNET | RR | 1 | R16C32[0][B] | clkdiv_1/n47_s3/I3 |
2.561 | 0.372 | tINS | RF | 1 | R16C32[0][B] | clkdiv_1/n47_s3/F |
2.561 | 0.000 | tNET | FF | 1 | R16C32[0][B] | clkdiv_1/count_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C32[0][B] | clkdiv_1/count_14_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C32[0][B] | clkdiv_1/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 37.772%; route: 0.280, 28.381%; tC2Q: 0.333, 33.846% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path18
Path Summary:
Slack | 1.060 |
Data Arrival Time | 2.636 |
Data Required Time | 1.577 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C32[0][B] | clkdiv_1/count_1_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R14C32[0][B] | clkdiv_1/count_1_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R14C32[0][B] | clkdiv_1/n60_s3/I2 |
2.636 | 0.724 | tINS | RR | 1 | R14C32[0][B] | clkdiv_1/n60_s3/F |
2.636 | 0.000 | tNET | RR | 1 | R14C32[0][B] | clkdiv_1/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C32[0][B] | clkdiv_1/count_1_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C32[0][B] | clkdiv_1/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.724, 68.322%; route: 0.002, 0.223%; tC2Q: 0.333, 31.456% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path19
Path Summary:
Slack | 1.060 |
Data Arrival Time | 2.636 |
Data Required Time | 1.577 |
From | clkdiv_1/count_3_s0 |
To | clkdiv_1/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[1][B] | clkdiv_1/count_3_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 2 | R14C34[1][B] | clkdiv_1/count_3_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R14C34[1][B] | clkdiv_1/n58_s4/I3 |
2.636 | 0.724 | tINS | RR | 1 | R14C34[1][B] | clkdiv_1/n58_s4/F |
2.636 | 0.000 | tNET | RR | 1 | R14C34[1][B] | clkdiv_1/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[1][B] | clkdiv_1/count_3_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C34[1][B] | clkdiv_1/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.724, 68.322%; route: 0.002, 0.223%; tC2Q: 0.333, 31.456% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path20
Path Summary:
Slack | 1.061 |
Data Arrival Time | 2.637 |
Data Required Time | 1.577 |
From | clkdiv_1/count_18_s0 |
To | clkdiv_1/count_18_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C34[0][B] | clkdiv_1/count_18_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R15C34[0][B] | clkdiv_1/count_18_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R15C34[0][B] | clkdiv_1/n43_s5/I1 |
2.637 | 0.724 | tINS | RR | 1 | R15C34[0][B] | clkdiv_1/n43_s5/F |
2.637 | 0.000 | tNET | RR | 1 | R15C34[0][B] | clkdiv_1/count_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C34[0][B] | clkdiv_1/count_18_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C34[0][B] | clkdiv_1/count_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.724, 68.246%; route: 0.004, 0.334%; tC2Q: 0.333, 31.421% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path21
Path Summary:
Slack | 1.062 |
Data Arrival Time | 2.639 |
Data Required Time | 1.577 |
From | clkdiv_1/count_5_s0 |
To | clkdiv_1/count_5_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C32[0][B] | clkdiv_1/count_5_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 7 | R15C32[0][B] | clkdiv_1/count_5_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R15C32[0][B] | clkdiv_1/n56_s4/I2 |
2.639 | 0.724 | tINS | RR | 1 | R15C32[0][B] | clkdiv_1/n56_s4/F |
2.639 | 0.000 | tNET | RR | 1 | R15C32[0][B] | clkdiv_1/count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C32[0][B] | clkdiv_1/count_5_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C32[0][B] | clkdiv_1/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.724, 68.170%; route: 0.005, 0.445%; tC2Q: 0.333, 31.386% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path22
Path Summary:
Slack | 1.062 |
Data Arrival Time | 2.639 |
Data Required Time | 1.577 |
From | clkdiv_1/count_7_s0 |
To | clkdiv_1/count_7_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C34[1][B] | clkdiv_1/count_7_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R15C34[1][B] | clkdiv_1/count_7_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R15C34[1][B] | clkdiv_1/n54_s5/I3 |
2.639 | 0.724 | tINS | RR | 1 | R15C34[1][B] | clkdiv_1/n54_s5/F |
2.639 | 0.000 | tNET | RR | 1 | R15C34[1][B] | clkdiv_1/count_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C34[1][B] | clkdiv_1/count_7_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C34[1][B] | clkdiv_1/count_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.724, 68.170%; route: 0.005, 0.445%; tC2Q: 0.333, 31.386% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path23
Path Summary:
Slack | 1.062 |
Data Arrival Time | 2.639 |
Data Required Time | 1.577 |
From | clkdiv_1/count_11_s0 |
To | clkdiv_1/count_11_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[0][B] | clkdiv_1/count_11_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R14C34[0][B] | clkdiv_1/count_11_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R14C34[0][B] | clkdiv_1/n50_s4/I3 |
2.639 | 0.724 | tINS | RR | 1 | R14C34[0][B] | clkdiv_1/n50_s4/F |
2.639 | 0.000 | tNET | RR | 1 | R14C34[0][B] | clkdiv_1/count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C34[0][B] | clkdiv_1/count_11_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C34[0][B] | clkdiv_1/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.724, 68.170%; route: 0.005, 0.445%; tC2Q: 0.333, 31.386% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path24
Path Summary:
Slack | 1.063 |
Data Arrival Time | 2.312 |
Data Required Time | 1.249 |
From | matrix_key_1/index_1_s0 |
To | matrix_key_1/index_1_s0 |
Launch Clk | clk50hz:[R] |
Latch Clk | clk50hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C24[1][B] | matrix_key_1/index_1_s0/CLK |
1.582 | 0.333 | tC2Q | RR | 11 | R14C24[1][B] | matrix_key_1/index_1_s0/Q |
1.588 | 0.006 | tNET | RR | 1 | R14C24[1][B] | matrix_key_1/n136_s0/I1 |
2.312 | 0.724 | tINS | RR | 1 | R14C24[1][B] | matrix_key_1/n136_s0/F |
2.312 | 0.000 | tNET | RR | 1 | R14C24[1][B] | matrix_key_1/index_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk50hz | ||||
0.000 | 0.000 | tCL | RR | 40 | R14C34[2][B] | clkdiv_1/clk_out_s0/Q |
1.249 | 1.249 | tNET | RR | 1 | R14C24[1][B] | matrix_key_1/index_1_s0/CLK |
1.249 | 0.000 | tHld | 1 | R14C24[1][B] | matrix_key_1/index_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Arrival Data Path Delay | cell: 0.724, 68.094%; route: 0.006, 0.555%; tC2Q: 0.333, 31.351% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.249, 100.000% |
Path25
Path Summary:
Slack | 1.064 |
Data Arrival Time | 2.641 |
Data Required Time | 1.577 |
From | clkdiv_1/count_10_s0 |
To | clkdiv_1/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C33[2][B] | clkdiv_1/count_10_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R15C33[2][B] | clkdiv_1/count_10_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R15C33[2][B] | clkdiv_1/n51_s5/I3 |
2.641 | 0.726 | tINS | RR | 1 | R15C33[2][B] | clkdiv_1/n51_s5/F |
2.641 | 0.000 | tNET | RR | 1 | R15C33[2][B] | clkdiv_1/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 21 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C33[2][B] | clkdiv_1/count_10_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C33[2][B] | clkdiv_1/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.726, 68.230%; route: 0.005, 0.444%; tC2Q: 0.333, 31.327% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_19_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_19_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_19_s0/CLK |
MPW2
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_17_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_17_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_17_s0/CLK |
MPW3
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_13_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_13_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_13_s0/CLK |
MPW4
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_5_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_5_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_5_s0/CLK |
MPW5
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_6_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_6_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_6_s0/CLK |
MPW6
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_14_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_14_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_14_s0/CLK |
MPW7
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_7_s0/CLK |
MPW8
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_8_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_8_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_8_s0/CLK |
MPW9
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_18_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_18_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_18_s0/CLK |
MPW10
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_15_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_15_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_15_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
40 | clk50hz | 1481472.625 | 2.375 |
21 | clk_d | 29.262 | 0.262 |
21 | count[19] | 33.804 | 1.342 |
17 | key_15_5 | 1481472.625 | 4.077 |
15 | n61_16 | 29.262 | 1.209 |
12 | index[0] | 1481473.250 | 1.004 |
11 | index[1] | 1481473.125 | 1.308 |
10 | count[4] | 30.726 | 0.842 |
10 | index[2] | 1481472.625 | 1.304 |
9 | n57_7 | 29.363 | 0.825 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R14C22 | 83.33% |
R14C34 | 81.94% |
R14C23 | 75.00% |
R15C24 | 70.83% |
R14C24 | 66.67% |
R15C23 | 62.50% |
R15C34 | 59.72% |
R16C34 | 58.33% |
R14C21 | 55.56% |
R15C22 | 54.17% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk50hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 40000 [get_nets {clk50hz}] |