Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\SV_240812_mhut_2001\pwm_servo\src\clkdiv.sv C:\Gowin\SV_240812_mhut_2001\pwm_servo\src\pwm.sv C:\Gowin\SV_240812_mhut_2001\pwm_servo\src\test_pwm_servo.sv |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.10.01 (64-bit) |
Part Number | GW1NR-LV9QN88PC6/I5 |
Device | GW1NR-9 |
Device Version | C |
Created Time | Mon Aug 12 11:45:38 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | test_pwm_servo |
Synthesis Process | Running parser: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.062s, Peak memory usage = 131.789MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 131.789MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 131.789MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 131.789MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 131.789MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 131.789MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 131.789MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 131.789MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 131.789MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 131.789MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 131.789MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.25s, Elapsed time = 0h 0m 0.272s, Peak memory usage = 160.414MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 160.414MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 160.414MB |
Total Time and Memory Usage | CPU time = 0h 0m 0.341s, Elapsed time = 0h 0m 0.372s, Peak memory usage = 160.414MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 15 |
I/O Buf | 15 |
    IBUF | 6 |
    OBUF | 9 |
Register | 33 |
    DFFE | 2 |
    DFFPE | 2 |
    DFFC | 26 |
    DFFCE | 3 |
LUT | 64 |
    LUT2 | 14 |
    LUT3 | 13 |
    LUT4 | 37 |
ALU | 4 |
    ALU | 4 |
INV | 1 |
    INV | 1 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 69(65 LUT, 4 ALU) / 8640 | <1% |
Register | 33 / 6693 | <1% |
  --Register as Latch | 0 / 6693 | 0% |
  --Register as FF | 33 / 6693 | <1% |
BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
2 | clkdiv_1/clk100khz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_1/clk_out_s0/Q |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.000(MHz) | 125.073(MHz) | 4 | TOP |
2 | clkdiv_1/clk100khz | 50.000(MHz) | 107.906(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 10.616 |
Data Arrival Time | 9.680 |
Data Required Time | 20.296 |
From | compare_1_s1 |
To | pwm_1/line_s0 |
Launch Clk | clk[R] |
Latch Clk | clkdiv_1/clk100khz[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 15 | clk_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | compare_1_s1/CLK |
1.184 | 0.458 | tC2Q | RF | 1 | compare_1_s1/Q |
2.144 | 0.960 | tNET | FF | 2 | pwm_1/n40_s42/I1 |
3.189 | 1.045 | tINS | FF | 1 | pwm_1/n40_s42/COUT |
3.189 | 0.000 | tNET | FF | 2 | pwm_1/n40_s43/CIN |
3.246 | 0.057 | tINS | FF | 1 | pwm_1/n40_s43/COUT |
3.246 | 0.000 | tNET | FF | 2 | pwm_1/n40_s44/CIN |
3.303 | 0.057 | tINS | FF | 1 | pwm_1/n40_s44/COUT |
3.303 | 0.000 | tNET | FF | 2 | pwm_1/n40_s45/CIN |
3.360 | 0.057 | tINS | FF | 1 | pwm_1/n40_s45/COUT |
4.320 | 0.960 | tNET | FF | 1 | pwm_1/n61_s5/I3 |
4.946 | 0.626 | tINS | FF | 1 | pwm_1/n61_s5/F |
5.906 | 0.960 | tNET | FF | 1 | pwm_1/n61_s2/I2 |
6.728 | 0.822 | tINS | FF | 1 | pwm_1/n61_s2/F |
7.688 | 0.960 | tNET | FF | 1 | pwm_1/n61_s7/I0 |
8.720 | 1.032 | tINS | FF | 1 | pwm_1/n61_s7/F |
9.680 | 0.960 | tNET | FF | 1 | pwm_1/line_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clkdiv_1/clk100khz | |||
20.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
20.726 | 0.726 | tNET | RR | 1 | pwm_1/line_s0/CLK |
20.696 | -0.030 | tUnc | pwm_1/line_s0 | ||
20.296 | -0.400 | tSu | 1 | pwm_1/line_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 6 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 3.696, 41.276%; route: 4.800, 53.605%; tC2Q: 0.458, 5.119% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:Slack | 12.005 |
Data Arrival Time | 8.321 |
Data Required Time | 20.326 |
From | pwm_1/count_0_s0 |
To | pwm_1/tc_s0 |
Launch Clk | clkdiv_1/clk100khz[R] |
Latch Clk | clkdiv_1/clk100khz[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clkdiv_1/clk100khz | |||
0.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
0.726 | 0.726 | tNET | RR | 1 | pwm_1/count_0_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 6 | pwm_1/count_0_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | pwm_1/n35_s3/I1 |
3.243 | 1.099 | tINS | FF | 9 | pwm_1/n35_s3/F |
4.203 | 0.960 | tNET | FF | 1 | pwm_1/n43_s49/I1 |
5.302 | 1.099 | tINS | FF | 1 | pwm_1/n43_s49/F |
6.262 | 0.960 | tNET | FF | 1 | pwm_1/n43_s51/I1 |
7.361 | 1.099 | tINS | FF | 1 | pwm_1/n43_s51/F |
8.321 | 0.960 | tNET | FF | 1 | pwm_1/tc_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clkdiv_1/clk100khz | |||
20.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
20.726 | 0.726 | tNET | RR | 1 | pwm_1/tc_s0/CLK |
20.326 | -0.400 | tSu | 1 | pwm_1/tc_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:Slack | 12.005 |
Data Arrival Time | 8.321 |
Data Required Time | 20.326 |
From | pwm_1/count_0_s0 |
To | pwm_1/count_10_s0 |
Launch Clk | clkdiv_1/clk100khz[R] |
Latch Clk | clkdiv_1/clk100khz[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clkdiv_1/clk100khz | |||
0.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
0.726 | 0.726 | tNET | RR | 1 | pwm_1/count_0_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 6 | pwm_1/count_0_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | pwm_1/n35_s3/I1 |
3.243 | 1.099 | tINS | FF | 9 | pwm_1/n35_s3/F |
4.203 | 0.960 | tNET | FF | 1 | pwm_1/n30_s3/I1 |
5.302 | 1.099 | tINS | FF | 2 | pwm_1/n30_s3/F |
6.262 | 0.960 | tNET | FF | 1 | pwm_1/n29_s2/I1 |
7.361 | 1.099 | tINS | FF | 1 | pwm_1/n29_s2/F |
8.321 | 0.960 | tNET | FF | 1 | pwm_1/count_10_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clkdiv_1/clk100khz | |||
20.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
20.726 | 0.726 | tNET | RR | 1 | pwm_1/count_10_s0/CLK |
20.326 | -0.400 | tSu | 1 | pwm_1/count_10_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:Slack | 12.005 |
Data Arrival Time | 8.321 |
Data Required Time | 20.326 |
From | pwm_1/count_0_s0 |
To | pwm_1/count_14_s0 |
Launch Clk | clkdiv_1/clk100khz[R] |
Latch Clk | clkdiv_1/clk100khz[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clkdiv_1/clk100khz | |||
0.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
0.726 | 0.726 | tNET | RR | 1 | pwm_1/count_0_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 6 | pwm_1/count_0_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | pwm_1/n35_s3/I1 |
3.243 | 1.099 | tINS | FF | 9 | pwm_1/n35_s3/F |
4.203 | 0.960 | tNET | FF | 1 | pwm_1/n26_s3/I1 |
5.302 | 1.099 | tINS | FF | 3 | pwm_1/n26_s3/F |
6.262 | 0.960 | tNET | FF | 1 | pwm_1/n25_s2/I1 |
7.361 | 1.099 | tINS | FF | 1 | pwm_1/n25_s2/F |
8.321 | 0.960 | tNET | FF | 1 | pwm_1/count_14_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clkdiv_1/clk100khz | |||
20.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
20.726 | 0.726 | tNET | RR | 1 | pwm_1/count_14_s0/CLK |
20.326 | -0.400 | tSu | 1 | pwm_1/count_14_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:Slack | 12.005 |
Data Arrival Time | 8.321 |
Data Required Time | 20.326 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/clk_out_s0 |
Launch Clk | clk[R] |
Latch Clk | clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | clk | |||
0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
0.000 | 0.000 | tINS | RR | 15 | clk_ibuf/O |
0.726 | 0.726 | tNET | RR | 1 | clkdiv_1/count_1_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 6 | clkdiv_1/count_1_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | clkdiv_1/n63_s83/I1 |
3.243 | 1.099 | tINS | FF | 1 | clkdiv_1/n63_s83/F |
4.203 | 0.960 | tNET | FF | 1 | clkdiv_1/n63_s80/I1 |
5.302 | 1.099 | tINS | FF | 1 | clkdiv_1/n63_s80/F |
6.262 | 0.960 | tNET | FF | 1 | clkdiv_1/n63_s89/I1 |
7.361 | 1.099 | tINS | FF | 1 | clkdiv_1/n63_s89/F |
8.321 | 0.960 | tNET | FF | 1 | clkdiv_1/clk_out_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | clk | |||
20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
20.000 | 0.000 | tINS | RR | 15 | clk_ibuf/O |
20.726 | 0.726 | tNET | RR | 1 | clkdiv_1/clk_out_s0/CLK |
20.326 | -0.400 | tSu | 1 | clkdiv_1/clk_out_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 4 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 3.297, 43.408%; route: 3.840, 50.558%; tC2Q: 0.458, 6.034% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |