Pin Messages

Report Title Pin Report
Design File C:\Gowin\SV_240812_mhut_2001\matrix_key\impl\gwsynthesis\matrix_key.vg
Physical Constraints File C:\Gowin\SV_240812_mhut_2001\matrix_key\src\matrix_key.cst
Timing Constraints File C:\Gowin\SV_240812_mhut_2001\matrix_key\src\matrix_key.sdc
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Aug 12 11:40:17 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Pin Details

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk 52/1 Y in IOR17[A] LVCMOS33 NA NONE ON NONE NA NA OFF NA 3.3
nrst 73/1 Y in IOT39[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
row[0] 25/2 Y in IOB8[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
row[1] 26/2 Y in IOB8[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
row[2] 27/2 Y in IOB11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
row[3] 28/2 Y in IOB11[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
col[0] 38/2 Y out IOB31[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
col[1] 37/2 Y out IOB31[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
col[2] 36/2 Y out IOB29[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
col[3] 39/2 Y out IOB33[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[0] 42/2 Y out IOB41[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[1] 41/2 Y out IOB41[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[2] 35/2 Y out IOB29[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[3] 40/2 Y out IOB33[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[4] 34/2 Y out IOB23[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[5] 33/2 Y out IOB23[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[6] 30/2 Y out IOB13[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[7] 29/2 Y out IOB13[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
dig[0] 74/1 Y out IOT38[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
dig[1] 75/1 Y out IOT38[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
dig[2] 76/1 Y out IOT37[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
dig[3] 77/1 Y out IOT37[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
ready 69/1 Y out IOT42[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
3/3 - in IOT2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
88/3 - in IOT5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
87/3 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
86/3 - in IOT8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
85/3 - in IOT8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
84/3 - in IOT10[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
83/3 - in IOT10[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
82/3 - in IOT11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
81/3 - in IOT11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
80/3 - in IOT12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
79/3 - in IOT12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
77/1 dig[3] out IOT37[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
76/1 dig[2] out IOT37[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
75/1 dig[1] out IOT38[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
74/1 dig[0] out IOT38[B] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
73/1 nrst in IOT39[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
72/1 - in IOT39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
71/1 - in IOT41[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
70/1 - in IOT41[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
69/1 ready out IOT42[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
68/1 - in IOT42[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
17/2 - in IOB2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
18/2 - in IOB2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
19/2 - in IOB4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
20/2 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
25/2 row[0] in IOB8[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
26/2 row[1] in IOB8[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
27/2 row[2] in IOB11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
28/2 row[3] in IOB11[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
29/2 seg[7] out IOB13[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
30/2 seg[6] out IOB13[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
31/2 - in IOB15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
32/2 - in IOB15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
33/2 seg[5] out IOB23[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
34/2 seg[4] out IOB23[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
35/2 seg[2] out IOB29[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
36/2 col[2] out IOB29[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
37/2 col[1] out IOB31[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
38/2 col[0] out IOB31[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
39/2 col[3] out IOB33[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
40/2 seg[3] out IOB33[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
41/2 seg[1] out IOB41[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
42/2 seg[0] out IOB41[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
47/2 - in IOB43[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
4/3 - in IOL5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
5/3 - in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
6/3 - in IOL11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
7/3 - in IOL12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
8/3 - out IOL13[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.8
9/3 - in IOL13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
10/3 - in IOL15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
11/3 - in IOL16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
13/3 - in IOL21[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/3 - in IOL22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/3 - in IOL25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
16/3 - in IOL26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
63/1 - in IOR5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
62/1 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
61/1 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
60/1 - in IOR12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
59/1 - in IOR12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
57/1 - in IOR13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
56/1 - in IOR14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
55/1 - in IOR14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
54/1 - in IOR15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
53/1 - in IOR15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
52/1 clk in IOR17[A] LVCMOS33 NA NONE ON NONE NA NA OFF NA 3.3
51/1 - in IOR17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
50/1 - in IOR22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
49/1 - in IOR24[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
48/1 - in IOR24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3