Synthesis Messages
Report Title | GowinSynthesis Report |
Design File | C:\Gowin\SV_240812_mhut_2001\leg4\src\alu.sv C:\Gowin\SV_240812_mhut_2001\leg4\src\clkdiv.sv C:\Gowin\SV_240812_mhut_2001\leg4\src\debounce.sv C:\Gowin\SV_240812_mhut_2001\leg4\src\drv7seg.sv C:\Gowin\SV_240812_mhut_2001\leg4\src\leg4.sv C:\Gowin\SV_240812_mhut_2001\leg4\src\leg4rom.sv C:\Gowin\SV_240812_mhut_2001\leg4\src\leg4sys.sv C:\Gowin\SV_240812_mhut_2001\leg4\src\mux7seg.sv C:\Gowin\SV_240812_mhut_2001\leg4\src\pc.sv C:\Gowin\SV_240812_mhut_2001\leg4\src\toggle.sv |
GowinSynthesis Constraints File | --- |
Tool Version | V1.9.10.01 (64-bit) |
Part Number | GW1NR-LV9QN88PC6/I5 |
Device | GW1NR-9 |
Device Version | C |
Created Time | Mon Aug 12 11:38:23 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
Top Level Module | leg4sys |
Synthesis Process | Running parser: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.073s, Peak memory usage = 132.492MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 132.926MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 132.996MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 133.078MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 133.277MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 133.395MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 133.441MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 133.527MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 133.621MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 133.625MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 133.625MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 163.961MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.15s, Peak memory usage = 163.961MB Generate output files: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 163.961MB |
Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 163.961MB |
Resource
Resource Usage Summary
Resource | Usage |
I/O Port | 30 |
I/O Buf | 30 |
    IBUF | 9 |
    OBUF | 21 |
Register | 138 |
    DFFE | 13 |
    DFFP | 4 |
    DFFC | 113 |
    DFFCE | 8 |
LUT | 351 |
    LUT2 | 49 |
    LUT3 | 132 |
    LUT4 | 170 |
ALU | 4 |
    ALU | 4 |
INV | 7 |
    INV | 7 |
Resource Utilization Summary
Resource | Usage | Utilization |
Logic | 362(358 LUT, 4 ALU) / 8640 | 5% |
Register | 138 / 6693 | 3% |
  --Register as Latch | 0 / 6693 | 0% |
  --Register as FF | 138 / 6693 | 3% |
BSRAM | 0 / 26 | 0% |
Timing
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
---|---|---|---|---|---|---|---|---|---|
1 | clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
2 | clkdiv_1/clk400hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_1/clk_out_s0/Q | ||
3 | leg4_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | leg4_clk_s5/O | ||
4 | clkdiv_5/clk160hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_5/clk_out_s0/Q |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 50.000(MHz) | 99.460(MHz) | 5 | TOP |
2 | clkdiv_1/clk400hz | 50.000(MHz) | 257.909(MHz) | 2 | TOP |
3 | leg4_clk | 50.000(MHz) | 63.872(MHz) | 8 | TOP |
4 | clkdiv_5/clk160hz | 50.000(MHz) | 170.377(MHz) | 3 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:Slack | 4.344 |
Data Arrival Time | 15.982 |
Data Required Time | 20.326 |
From | leg4_1/inst1/adr_2_s0 |
To | leg4_1/out_2_s0 |
Launch Clk | leg4_clk[R] |
Latch Clk | leg4_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | leg4_clk | |||
0.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
0.726 | 0.726 | tNET | RR | 1 | leg4_1/inst1/adr_2_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 29 | leg4_1/inst1/adr_2_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | drv7seg_1/seg_5_s32/I1 |
3.243 | 1.099 | tINS | FF | 4 | drv7seg_1/seg_5_s32/F |
4.203 | 0.960 | tNET | FF | 1 | leg4_rom_1/rom_out_1_s/I1 |
5.302 | 1.099 | tINS | FF | 4 | leg4_rom_1/rom_out_1_s/F |
6.262 | 0.960 | tNET | FF | 2 | leg4_1/inst2/n8_s/I1 |
7.307 | 1.045 | tINS | FF | 1 | leg4_1/inst2/n8_s/COUT |
7.307 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n7_s/CIN |
7.870 | 0.563 | tINS | FF | 1 | leg4_1/inst2/n7_s/SUM |
8.830 | 0.960 | tNET | FF | 1 | leg4_1/inst2/n17_s21/I1 |
9.929 | 1.099 | tINS | FF | 1 | leg4_1/inst2/n17_s21/F |
10.889 | 0.960 | tNET | FF | 1 | leg4_1/inst2/n17_s19/I0 |
11.038 | 0.149 | tINS | FF | 1 | leg4_1/inst2/n17_s19/O |
11.998 | 0.960 | tNET | FF | 1 | leg4_1/inst2/data_Z_2_s0/I0 |
13.030 | 1.032 | tINS | FF | 1 | leg4_1/inst2/data_Z_2_s0/F |
13.990 | 0.960 | tNET | FF | 1 | leg4_1/inst2/data_Z_2_s/I0 |
15.022 | 1.032 | tINS | FF | 2 | leg4_1/inst2/data_Z_2_s/F |
15.982 | 0.960 | tNET | FF | 1 | leg4_1/out_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | leg4_clk | |||
20.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
20.726 | 0.726 | tNET | RR | 1 | leg4_1/out_2_s0/CLK |
20.326 | -0.400 | tSu | 1 | leg4_1/out_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 7.118, 46.656%; route: 7.680, 50.340%; tC2Q: 0.458, 3.004% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 2
Path Summary:Slack | 4.344 |
Data Arrival Time | 15.982 |
Data Required Time | 20.326 |
From | leg4_1/inst1/adr_2_s0 |
To | leg4_1/a_2_s0 |
Launch Clk | leg4_clk[R] |
Latch Clk | leg4_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | leg4_clk | |||
0.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
0.726 | 0.726 | tNET | RR | 1 | leg4_1/inst1/adr_2_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 29 | leg4_1/inst1/adr_2_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | drv7seg_1/seg_5_s32/I1 |
3.243 | 1.099 | tINS | FF | 4 | drv7seg_1/seg_5_s32/F |
4.203 | 0.960 | tNET | FF | 1 | leg4_rom_1/rom_out_1_s/I1 |
5.302 | 1.099 | tINS | FF | 4 | leg4_rom_1/rom_out_1_s/F |
6.262 | 0.960 | tNET | FF | 2 | leg4_1/inst2/n8_s/I1 |
7.307 | 1.045 | tINS | FF | 1 | leg4_1/inst2/n8_s/COUT |
7.307 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n7_s/CIN |
7.870 | 0.563 | tINS | FF | 1 | leg4_1/inst2/n7_s/SUM |
8.830 | 0.960 | tNET | FF | 1 | leg4_1/inst2/n17_s21/I1 |
9.929 | 1.099 | tINS | FF | 1 | leg4_1/inst2/n17_s21/F |
10.889 | 0.960 | tNET | FF | 1 | leg4_1/inst2/n17_s19/I0 |
11.038 | 0.149 | tINS | FF | 1 | leg4_1/inst2/n17_s19/O |
11.998 | 0.960 | tNET | FF | 1 | leg4_1/inst2/data_Z_2_s0/I0 |
13.030 | 1.032 | tINS | FF | 1 | leg4_1/inst2/data_Z_2_s0/F |
13.990 | 0.960 | tNET | FF | 1 | leg4_1/inst2/data_Z_2_s/I0 |
15.022 | 1.032 | tINS | FF | 2 | leg4_1/inst2/data_Z_2_s/F |
15.982 | 0.960 | tNET | FF | 1 | leg4_1/a_2_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | leg4_clk | |||
20.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
20.726 | 0.726 | tNET | RR | 1 | leg4_1/a_2_s0/CLK |
20.326 | -0.400 | tSu | 1 | leg4_1/a_2_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 7.118, 46.656%; route: 7.680, 50.340%; tC2Q: 0.458, 3.004% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 3
Path Summary:Slack | 4.354 |
Data Arrival Time | 15.972 |
Data Required Time | 20.326 |
From | leg4_1/inst1/adr_2_s0 |
To | leg4_1/a_3_s0 |
Launch Clk | leg4_clk[R] |
Latch Clk | leg4_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | leg4_clk | |||
0.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
0.726 | 0.726 | tNET | RR | 1 | leg4_1/inst1/adr_2_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 29 | leg4_1/inst1/adr_2_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | drv7seg_1/seg_5_s32/I1 |
3.243 | 1.099 | tINS | FF | 4 | drv7seg_1/seg_5_s32/F |
4.203 | 0.960 | tNET | FF | 1 | leg4_rom_1/rom_out_1_s/I1 |
5.302 | 1.099 | tINS | FF | 4 | leg4_rom_1/rom_out_1_s/F |
6.262 | 0.960 | tNET | FF | 2 | leg4_1/inst2/n8_s/I1 |
7.307 | 1.045 | tINS | FF | 1 | leg4_1/inst2/n8_s/COUT |
7.307 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n7_s/CIN |
7.364 | 0.057 | tINS | FF | 1 | leg4_1/inst2/n7_s/COUT |
7.364 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n6_s/CIN |
7.927 | 0.563 | tINS | FF | 1 | leg4_1/inst2/n6_s/SUM |
8.887 | 0.960 | tNET | FF | 1 | leg4_1/inst2/n16_s24/I0 |
9.919 | 1.032 | tINS | FF | 1 | leg4_1/inst2/n16_s24/F |
10.879 | 0.960 | tNET | FF | 1 | leg4_1/inst2/n16_s20/I0 |
11.028 | 0.149 | tINS | FF | 1 | leg4_1/inst2/n16_s20/O |
11.988 | 0.960 | tNET | FF | 1 | leg4_1/inst2/data_Z_3_s0/I0 |
13.020 | 1.032 | tINS | FF | 1 | leg4_1/inst2/data_Z_3_s0/F |
13.980 | 0.960 | tNET | FF | 1 | leg4_1/inst2/data_Z_3_s/I0 |
15.012 | 1.032 | tINS | FF | 2 | leg4_1/inst2/data_Z_3_s/F |
15.972 | 0.960 | tNET | FF | 1 | leg4_1/a_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | leg4_clk | |||
20.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
20.726 | 0.726 | tNET | RR | 1 | leg4_1/a_3_s0/CLK |
20.326 | -0.400 | tSu | 1 | leg4_1/a_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 7.108, 46.621%; route: 7.680, 50.373%; tC2Q: 0.458, 3.006% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 4
Path Summary:Slack | 4.354 |
Data Arrival Time | 15.972 |
Data Required Time | 20.326 |
From | leg4_1/inst1/adr_2_s0 |
To | leg4_1/out_3_s0 |
Launch Clk | leg4_clk[R] |
Latch Clk | leg4_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | leg4_clk | |||
0.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
0.726 | 0.726 | tNET | RR | 1 | leg4_1/inst1/adr_2_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 29 | leg4_1/inst1/adr_2_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | drv7seg_1/seg_5_s32/I1 |
3.243 | 1.099 | tINS | FF | 4 | drv7seg_1/seg_5_s32/F |
4.203 | 0.960 | tNET | FF | 1 | leg4_rom_1/rom_out_1_s/I1 |
5.302 | 1.099 | tINS | FF | 4 | leg4_rom_1/rom_out_1_s/F |
6.262 | 0.960 | tNET | FF | 2 | leg4_1/inst2/n8_s/I1 |
7.307 | 1.045 | tINS | FF | 1 | leg4_1/inst2/n8_s/COUT |
7.307 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n7_s/CIN |
7.364 | 0.057 | tINS | FF | 1 | leg4_1/inst2/n7_s/COUT |
7.364 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n6_s/CIN |
7.927 | 0.563 | tINS | FF | 1 | leg4_1/inst2/n6_s/SUM |
8.887 | 0.960 | tNET | FF | 1 | leg4_1/inst2/n16_s24/I0 |
9.919 | 1.032 | tINS | FF | 1 | leg4_1/inst2/n16_s24/F |
10.879 | 0.960 | tNET | FF | 1 | leg4_1/inst2/n16_s20/I0 |
11.028 | 0.149 | tINS | FF | 1 | leg4_1/inst2/n16_s20/O |
11.988 | 0.960 | tNET | FF | 1 | leg4_1/inst2/data_Z_3_s0/I0 |
13.020 | 1.032 | tINS | FF | 1 | leg4_1/inst2/data_Z_3_s0/F |
13.980 | 0.960 | tNET | FF | 1 | leg4_1/inst2/data_Z_3_s/I0 |
15.012 | 1.032 | tINS | FF | 2 | leg4_1/inst2/data_Z_3_s/F |
15.972 | 0.960 | tNET | FF | 1 | leg4_1/out_3_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | leg4_clk | |||
20.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
20.726 | 0.726 | tNET | RR | 1 | leg4_1/out_3_s0/CLK |
20.326 | -0.400 | tSu | 1 | leg4_1/out_3_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 8 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 7.108, 46.621%; route: 7.680, 50.373%; tC2Q: 0.458, 3.006% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Path 5
Path Summary:Slack | 5.249 |
Data Arrival Time | 15.077 |
Data Required Time | 20.326 |
From | leg4_1/inst1/adr_2_s0 |
To | leg4_1/out_1_s0 |
Launch Clk | leg4_clk[R] |
Latch Clk | leg4_clk[R] |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
0.000 | 0.000 | leg4_clk | |||
0.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
0.726 | 0.726 | tNET | RR | 1 | leg4_1/inst1/adr_2_s0/CLK |
1.184 | 0.458 | tC2Q | RF | 29 | leg4_1/inst1/adr_2_s0/Q |
2.144 | 0.960 | tNET | FF | 1 | drv7seg_1/seg_5_s32/I1 |
3.243 | 1.099 | tINS | FF | 4 | drv7seg_1/seg_5_s32/F |
4.203 | 0.960 | tNET | FF | 1 | leg4_rom_1/rom_out_1_s/I1 |
5.302 | 1.099 | tINS | FF | 4 | leg4_rom_1/rom_out_1_s/F |
6.262 | 0.960 | tNET | FF | 2 | leg4_1/inst2/n8_s/I1 |
6.965 | 0.703 | tINS | FF | 1 | leg4_1/inst2/n8_s/SUM |
7.925 | 0.960 | tNET | FF | 1 | leg4_1/inst2/n18_s21/I1 |
9.024 | 1.099 | tINS | FF | 1 | leg4_1/inst2/n18_s21/F |
9.984 | 0.960 | tNET | FF | 1 | leg4_1/inst2/n18_s19/I0 |
10.133 | 0.149 | tINS | FF | 1 | leg4_1/inst2/n18_s19/O |
11.093 | 0.960 | tNET | FF | 1 | leg4_1/inst2/data_Z_1_s0/I0 |
12.125 | 1.032 | tINS | FF | 1 | leg4_1/inst2/data_Z_1_s0/F |
13.085 | 0.960 | tNET | FF | 1 | leg4_1/inst2/data_Z_1_s/I0 |
14.117 | 1.032 | tINS | FF | 2 | leg4_1/inst2/data_Z_1_s/F |
15.077 | 0.960 | tNET | FF | 1 | leg4_1/out_1_s0/D |
AT | DELAY | TYPE | RF | FANOUT | NODE |
---|---|---|---|---|---|
20.000 | 0.000 | leg4_clk | |||
20.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
20.726 | 0.726 | tNET | RR | 1 | leg4_1/out_1_s0/CLK |
20.326 | -0.400 | tSu | 1 | leg4_1/out_1_s0 |
Clock Skew: | 0.000 |
Setup Relationship: | 20.000 |
Logic Level: | 7 |
Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |
Arrival Data Path Delay: | cell: 6.213, 43.292%; route: 7.680, 53.514%; tC2Q: 0.458, 3.194% |
Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.726, 100.000% |