Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v
C:\Gowin\Gowin_V1.9.10_x64\IDE\data\ipcores\gw_jtag.v
C:\Gowin\SystemVerilog\SV_240705\stopwatch\impl\gao\gw_gao_top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.10 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Fri Jul 5 13:35:45 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module gw_gao
Synthesis Process Running parser:
    CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.278s, Peak memory usage = 105.777MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 105.777MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 105.777MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 105.777MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 105.777MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 105.777MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 105.777MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 105.777MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 105.777MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 105.777MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 105.777MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 105.777MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 122.465MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.039s, Peak memory usage = 122.465MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 122.465MB
Total Time and Memory Usage CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 122.465MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 9
I/O Buf 9
    IBUF 8
    OBUF 1
Register 286
    DFF 15
    DFFE 1
    DFFR 1
    DFFP 3
    DFFPE 33
    DFFC 25
    DFFCE 208
LUT 427
    LUT2 61
    LUT3 107
    LUT4 259
MUX 1
    MUX16 1
ALU 15
    ALU 15
INV 4
    INV 4
BSRAM 2
    SDPB 2
Black Box 1
    GW_JTAG 1

Resource Utilization Summary

Resource Usage Utilization
Logic 454(439 LUT, 15 ALU) / 8640 6%
Register 286 / 6693 5%
  --Register as Latch 0 / 6693 0%
  --Register as FF 286 / 6693 5%
BSRAM 2 / 26 8%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk400hz Base 20.000 50.0 0.000 10.000 clk400hz_ibuf/I

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk400hz 50.000(MHz) 102.983(MHz) 5 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 10.290
Data Arrival Time 10.036
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Launch Clk clk400hz[R]
Latch Clk clk400hz[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk400hz
0.000 0.000 tCL RR 1 clk400hz_ibuf/I
0.000 0.000 tINS RR 77 clk400hz_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.184 0.458 tC2Q RF 4 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s12/I0
3.176 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n248_s12/F
4.136 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s6/I1
5.235 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n248_s6/F
6.195 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s4/I1
7.294 1.099 tINS FF 12 u_la0_top/u_ao_mem_ctrl/n248_s4/F
8.254 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n258_s1/I2
9.076 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n258_s1/F
10.036 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk400hz
20.000 0.000 tCL RR 1 clk400hz_ibuf/I
20.000 0.000 tINS RR 77 clk400hz_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_1_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.052, 43.522%; route: 4.800, 51.555%; tC2Q: 0.458, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:
Slack 10.290
Data Arrival Time 10.036
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Launch Clk clk400hz[R]
Latch Clk clk400hz[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk400hz
0.000 0.000 tCL RR 1 clk400hz_ibuf/I
0.000 0.000 tINS RR 77 clk400hz_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.184 0.458 tC2Q RF 4 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s12/I0
3.176 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n248_s12/F
4.136 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s6/I1
5.235 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n248_s6/F
6.195 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s4/I1
7.294 1.099 tINS FF 12 u_la0_top/u_ao_mem_ctrl/n248_s4/F
8.254 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n256_s1/I2
9.076 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n256_s1/F
10.036 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk400hz
20.000 0.000 tCL RR 1 clk400hz_ibuf/I
20.000 0.000 tINS RR 77 clk400hz_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_3_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.052, 43.522%; route: 4.800, 51.555%; tC2Q: 0.458, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:
Slack 10.290
Data Arrival Time 10.036
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Launch Clk clk400hz[R]
Latch Clk clk400hz[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk400hz
0.000 0.000 tCL RR 1 clk400hz_ibuf/I
0.000 0.000 tINS RR 77 clk400hz_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.184 0.458 tC2Q RF 4 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s12/I0
3.176 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n248_s12/F
4.136 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s6/I1
5.235 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n248_s6/F
6.195 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s4/I1
7.294 1.099 tINS FF 12 u_la0_top/u_ao_mem_ctrl/n248_s4/F
8.254 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n253_s1/I2
9.076 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n253_s1/F
10.036 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk400hz
20.000 0.000 tCL RR 1 clk400hz_ibuf/I
20.000 0.000 tINS RR 77 clk400hz_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_6_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.052, 43.522%; route: 4.800, 51.555%; tC2Q: 0.458, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:
Slack 10.290
Data Arrival Time 10.036
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Launch Clk clk400hz[R]
Latch Clk clk400hz[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk400hz
0.000 0.000 tCL RR 1 clk400hz_ibuf/I
0.000 0.000 tINS RR 77 clk400hz_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.184 0.458 tC2Q RF 4 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s12/I0
3.176 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n248_s12/F
4.136 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s6/I1
5.235 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n248_s6/F
6.195 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s4/I1
7.294 1.099 tINS FF 12 u_la0_top/u_ao_mem_ctrl/n248_s4/F
8.254 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n252_s1/I2
9.076 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n252_s1/F
10.036 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk400hz
20.000 0.000 tCL RR 1 clk400hz_ibuf/I
20.000 0.000 tINS RR 77 clk400hz_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_7_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.052, 43.522%; route: 4.800, 51.555%; tC2Q: 0.458, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:
Slack 10.290
Data Arrival Time 10.036
Data Required Time 20.326
From u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1
To u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Launch Clk clk400hz[R]
Latch Clk clk400hz[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk400hz
0.000 0.000 tCL RR 1 clk400hz_ibuf/I
0.000 0.000 tINS RR 77 clk400hz_ibuf/O
0.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/CLK
1.184 0.458 tC2Q RF 4 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_10_s1/Q
2.144 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s12/I0
3.176 1.032 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n248_s12/F
4.136 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s6/I1
5.235 1.099 tINS FF 2 u_la0_top/u_ao_mem_ctrl/n248_s6/F
6.195 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n248_s4/I1
7.294 1.099 tINS FF 12 u_la0_top/u_ao_mem_ctrl/n248_s4/F
8.254 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/n250_s1/I2
9.076 0.822 tINS FF 1 u_la0_top/u_ao_mem_ctrl/n250_s1/F
10.036 0.960 tNET FF 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk400hz
20.000 0.000 tCL RR 1 clk400hz_ibuf/I
20.000 0.000 tINS RR 77 clk400hz_ibuf/O
20.726 0.726 tNET RR 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1/CLK
20.326 -0.400 tSu 1 u_la0_top/u_ao_mem_ctrl/capture_mem_addr_9_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.052, 43.522%; route: 4.800, 51.555%; tC2Q: 0.458, 4.923%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%