Synthesis Messages

Report Title	GowinSynthesis Report
Design File	C:\Gowin\SV_240812_mhut_2001\add4bit\src\add4bit.sv C:\Gowin\SV_240812_mhut_2001\add4bit\src\clkdiv.sv C:\Gowin\SV_240812_mhut_2001\add4bit\src\drv7seg.sv C:\Gowin\SV_240812_mhut_2001\add4bit\src\mux7seg.sv C:\Gowin\SV_240812_mhut_2001\add4bit\src\test_add4bit.sv
GowinSynthesis Constraints File	---
Tool Version	V1.9.10.01 (64-bit)
Part Number	GW1NR-LV9QN88PC6/I5
Device	GW1NR-9
Device Version	C
Created Time	Mon Aug 12 11:36:32 2024
Legal Announcement	Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module	test_add4bit
Synthesis Process	Running parser:     CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.061s, Peak memory usage = 335.316MB Running netlist conversion:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization:     Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 335.316MB     Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 335.316MB     Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 335.316MB Running inference:     Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 335.316MB     Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 335.316MB     Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 335.316MB     Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 335.316MB Running technical mapping:     Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 335.316MB     Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 335.316MB     Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 335.316MB     Tech-Mapping Phase 3: CPU time = 0h 0m 0.687s, Elapsed time = 0h 0m 0.757s, Peak memory usage = 335.316MB     Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 335.316MB Generate output files:     CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 335.316MB
Total Time and Memory Usage	CPU time = 0h 0m 0.778s, Elapsed time = 0h 0m 0.844s, Peak memory usage = 335.316MB

Resource

Resource Usage Summary

Resource	Usage
I/O Port	21
I/O Buf	21
IBUF	9
OBUF	12
Register	40
DFF	7
DFFS	4
DFFR	29
LUT	66
LUT2	14
LUT3	4
LUT4	48
ALU	25
ALU	25
INV	4
INV	4

Resource Utilization Summary

Resource	Usage	Utilization
Logic	95(70 LUT, 25 ALU) / 8640	2%
Register	40 / 6693	<1%
--Register as Latch	0 / 6693	0%
--Register as FF	40 / 6693	<1%
BSRAM	0 / 26	0%

Timing

Clock Summary:

NO.	Clock Name	Type	Period	Frequency(MHz)	Rise	Fall	Source	Master	Object
1	clk	Base	20.000	50.0	0.000	10.000			clk_ibuf/I
2	clkdiv_1/clk_160hz	Base	20.000	50.0	0.000	10.000			clkdiv_1/clk_out_s1/Q

Max Frequency Summary:

NO.	Clock Name	Constraint	Actual Fmax	Logic Level	Entity
1	clk	50.000(MHz)	107.254(MHz)	5	TOP
2	clkdiv_1/clk_160hz	50.000(MHz)	138.020(MHz)	4	TOP

Detail Timing Paths Information

Path 1

Path Summary:

Slack	10.676
Data Arrival Time	10.006
Data Required Time	20.683
From	clkdiv_1/count_2_s0
To	clkdiv_1/clk_out_s1
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	27	clk_ibuf/O
0.726	0.726	tNET	RR	1	clkdiv_1/count_2_s0/CLK
1.184	0.458	tC2Q	RF	3	clkdiv_1/count_2_s0/Q
2.144	0.960	tNET	FF	1	clkdiv_1/clk_out_s11/I1
3.243	1.099	tINS	FF	1	clkdiv_1/clk_out_s11/F
4.203	0.960	tNET	FF	1	clkdiv_1/clk_out_s8/I1
5.302	1.099	tINS	FF	1	clkdiv_1/clk_out_s8/F
6.262	0.960	tNET	FF	1	clkdiv_1/clk_out_s4/I0
7.294	1.032	tINS	FF	1	clkdiv_1/clk_out_s4/F
8.254	0.960	tNET	FF	1	clkdiv_1/clk_out_s3/I0
9.280	1.026	tINS	FR	1	clkdiv_1/clk_out_s3/F
10.006	0.726	tNET	RR	1	clkdiv_1/clk_out_s1/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	27	clk_ibuf/O
20.726	0.726	tNET	RR	1	clkdiv_1/clk_out_s1/CLK
20.683	-0.043	tSu		1	clkdiv_1/clk_out_s1

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.256, 45.860%; route: 4.566, 49.201%; tC2Q: 0.458, 4.939%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:

Slack	10.676
Data Arrival Time	10.006
Data Required Time	20.683
From	clkdiv_1/count_0_s0
To	clkdiv_1/count_25_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	27	clk_ibuf/O
0.726	0.726	tNET	RR	1	clkdiv_1/count_0_s0/CLK
1.184	0.458	tC2Q	RF	4	clkdiv_1/count_0_s0/Q
2.144	0.960	tNET	FF	1	clkdiv_1/n7_s87/I1
3.243	1.099	tINS	FF	1	clkdiv_1/n7_s87/F
4.203	0.960	tNET	FF	1	clkdiv_1/n7_s83/I1
5.302	1.099	tINS	FF	1	clkdiv_1/n7_s83/F
6.262	0.960	tNET	FF	1	clkdiv_1/n7_s79/I0
7.294	1.032	tINS	FF	1	clkdiv_1/n7_s79/F
8.254	0.960	tNET	FF	1	clkdiv_1/n7_s78/I0
9.280	1.026	tINS	FR	26	clkdiv_1/n7_s78/F
10.006	0.726	tNET	RR	1	clkdiv_1/count_25_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	27	clk_ibuf/O
20.726	0.726	tNET	RR	1	clkdiv_1/count_25_s0/CLK
20.683	-0.043	tSu		1	clkdiv_1/count_25_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.256, 45.860%; route: 4.566, 49.201%; tC2Q: 0.458, 4.939%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:

Slack	10.676
Data Arrival Time	10.006
Data Required Time	20.683
From	clkdiv_1/count_0_s0
To	clkdiv_1/count_0_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	27	clk_ibuf/O
0.726	0.726	tNET	RR	1	clkdiv_1/count_0_s0/CLK
1.184	0.458	tC2Q	RF	4	clkdiv_1/count_0_s0/Q
2.144	0.960	tNET	FF	1	clkdiv_1/n7_s87/I1
3.243	1.099	tINS	FF	1	clkdiv_1/n7_s87/F
4.203	0.960	tNET	FF	1	clkdiv_1/n7_s83/I1
5.302	1.099	tINS	FF	1	clkdiv_1/n7_s83/F
6.262	0.960	tNET	FF	1	clkdiv_1/n7_s79/I0
7.294	1.032	tINS	FF	1	clkdiv_1/n7_s79/F
8.254	0.960	tNET	FF	1	clkdiv_1/n7_s78/I0
9.280	1.026	tINS	FR	26	clkdiv_1/n7_s78/F
10.006	0.726	tNET	RR	1	clkdiv_1/count_0_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	27	clk_ibuf/O
20.726	0.726	tNET	RR	1	clkdiv_1/count_0_s0/CLK
20.683	-0.043	tSu		1	clkdiv_1/count_0_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.256, 45.860%; route: 4.566, 49.201%; tC2Q: 0.458, 4.939%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:

Slack	10.676
Data Arrival Time	10.006
Data Required Time	20.683
From	clkdiv_1/count_0_s0
To	clkdiv_1/count_1_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	27	clk_ibuf/O
0.726	0.726	tNET	RR	1	clkdiv_1/count_0_s0/CLK
1.184	0.458	tC2Q	RF	4	clkdiv_1/count_0_s0/Q
2.144	0.960	tNET	FF	1	clkdiv_1/n7_s87/I1
3.243	1.099	tINS	FF	1	clkdiv_1/n7_s87/F
4.203	0.960	tNET	FF	1	clkdiv_1/n7_s83/I1
5.302	1.099	tINS	FF	1	clkdiv_1/n7_s83/F
6.262	0.960	tNET	FF	1	clkdiv_1/n7_s79/I0
7.294	1.032	tINS	FF	1	clkdiv_1/n7_s79/F
8.254	0.960	tNET	FF	1	clkdiv_1/n7_s78/I0
9.280	1.026	tINS	FR	26	clkdiv_1/n7_s78/F
10.006	0.726	tNET	RR	1	clkdiv_1/count_1_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	27	clk_ibuf/O
20.726	0.726	tNET	RR	1	clkdiv_1/count_1_s0/CLK
20.683	-0.043	tSu		1	clkdiv_1/count_1_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.256, 45.860%; route: 4.566, 49.201%; tC2Q: 0.458, 4.939%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:

Slack	10.676
Data Arrival Time	10.006
Data Required Time	20.683
From	clkdiv_1/count_0_s0
To	clkdiv_1/count_2_s0
Launch Clk	clk[R]
Latch Clk	clk[R]

Data Arrival Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
0.000	0.000				clk
0.000	0.000	tCL	RR	1	clk_ibuf/I
0.000	0.000	tINS	RR	27	clk_ibuf/O
0.726	0.726	tNET	RR	1	clkdiv_1/count_0_s0/CLK
1.184	0.458	tC2Q	RF	4	clkdiv_1/count_0_s0/Q
2.144	0.960	tNET	FF	1	clkdiv_1/n7_s87/I1
3.243	1.099	tINS	FF	1	clkdiv_1/n7_s87/F
4.203	0.960	tNET	FF	1	clkdiv_1/n7_s83/I1
5.302	1.099	tINS	FF	1	clkdiv_1/n7_s83/F
6.262	0.960	tNET	FF	1	clkdiv_1/n7_s79/I0
7.294	1.032	tINS	FF	1	clkdiv_1/n7_s79/F
8.254	0.960	tNET	FF	1	clkdiv_1/n7_s78/I0
9.280	1.026	tINS	FR	26	clkdiv_1/n7_s78/F
10.006	0.726	tNET	RR	1	clkdiv_1/count_2_s0/RESET

Data Required Path:

AT	DELAY	TYPE	RF	FANOUT	NODE
20.000	0.000				clk
20.000	0.000	tCL	RR	1	clk_ibuf/I
20.000	0.000	tINS	RR	27	clk_ibuf/O
20.726	0.726	tNET	RR	1	clkdiv_1/count_2_s0/CLK
20.683	-0.043	tSu		1	clkdiv_1/count_2_s0

Path Statistics:

Clock Skew:	0.000
Setup Relationship:	20.000
Logic Level:	5
Arrival Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay:	cell: 4.256, 45.860%; route: 4.566, 49.201%; tC2Q: 0.458, 4.939%
Required Clock Path Delay:	cell: 0.000, 0.000%; route: 0.726, 100.000%