Timing Messages
Report Title | Timing Analysis Report |
Design File | C:\Gowin\SV_240812_mhut_2001\leg4\impl\gwsynthesis\leg4.vg |
Physical Constraints File | C:\Gowin\SV_240812_mhut_2001\leg4\src\leg4.cst |
Timing Constraint File | C:\Gowin\SV_240812_mhut_2001\leg4\src\leg4.sdc |
Tool Version | V1.9.10.01 (64-bit) |
Part Number | GW1NR-LV9QN88PC6/I5 |
Device | GW1NR-9 |
Device Version | C |
Created Time | Mon Aug 12 11:38:28 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.14V 85C C6/I5 |
Hold Delay Model | Fast 1.26V 0C C6/I5 |
Numbers of Paths Analyzed | 598 |
Numbers of Endpoints Analyzed | 305 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | clk27mhz | Base | 37.037 | 27.000 | 0.000 | 18.518 | clk | ||
2 | clk1khz | Generated | 999998.938 | 0.001 | 0.000 | 499999.469 | clk | clk27mhz | clk1khz |
3 | clk400hz | Generated | 2499997.500 | 0.000 | 0.000 | 1249998.750 | clk | clk27mhz | clk400hz |
4 | clk1hz | Generated | 99999896.000 | 0.000 | 0.000 | 49999948.000 | clk | clk27mhz | clk1hz |
5 | clk160hz | Generated | 6249993.500 | 0.000 | 0.000 | 3124996.750 | clk | clk27mhz | clk160hz |
6 | clk10hz | Generated | 99999896.000 | 0.000 | 0.000 | 49999948.000 | clk | clk27mhz | clk10hz |
7 | leg4_clk | Generated | 999998.938 | 0.001 | 0.000 | 499999.469 | clk1khz | clk1khz | leg4_clk |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk27mhz | 27.000(MHz) | 112.992(MHz) | 5 | TOP |
2 | clk400hz | 0.000(MHz) | 200.000(MHz) | 2 | TOP |
3 | clk160hz | 0.000(MHz) | 117.647(MHz) | 3 | TOP |
4 | leg4_clk | 0.001(MHz) | 72.072(MHz) | 8 | TOP |
No timing paths to get frequency of clk1khz!
No timing paths to get frequency of clk1hz!
No timing paths to get frequency of clk10hz!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk27mhz | Setup | 0.000 | 0 |
clk27mhz | Hold | 0.000 | 0 |
clk1khz | Setup | 0.000 | 0 |
clk1khz | Hold | 0.000 | 0 |
clk400hz | Setup | 0.000 | 0 |
clk400hz | Hold | 0.000 | 0 |
clk1hz | Setup | 0.000 | 0 |
clk1hz | Hold | 0.000 | 0 |
clk160hz | Setup | 0.000 | 0 |
clk160hz | Hold | 0.000 | 0 |
clk10hz | Setup | 0.000 | 0 |
clk10hz | Hold | 0.000 | 0 |
leg4_clk | Setup | 0.000 | 0 |
leg4_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 28.187 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_21_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.450 |
2 | 28.239 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.398 |
3 | 28.240 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_22_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.397 |
4 | 28.240 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_24_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.397 |
5 | 28.251 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.386 |
6 | 28.254 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_13_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.383 |
7 | 28.318 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_9_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.319 |
8 | 28.391 | clkdiv_2/count_2_s0/Q | clkdiv_2/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.246 |
9 | 28.457 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.180 |
10 | 28.466 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.171 |
11 | 28.466 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.171 |
12 | 28.466 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.171 |
13 | 28.503 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.134 |
14 | 28.503 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.134 |
15 | 28.503 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.134 |
16 | 28.504 | clkdiv_3/count_11_s0/Q | clkdiv_3/count_18_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.133 |
17 | 28.659 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.978 |
18 | 28.662 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.975 |
19 | 28.662 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.975 |
20 | 28.676 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.961 |
21 | 28.712 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.925 |
22 | 28.719 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.918 |
23 | 28.729 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.908 |
24 | 28.729 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.908 |
25 | 28.785 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_20_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.852 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.708 | clkdiv_5/count_17_s0/Q | clkdiv_5/count_17_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
2 | 0.708 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
3 | 0.708 | clkdiv_3/count_11_s0/Q | clkdiv_3/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
4 | 0.708 | clkdiv_2/count_0_s0/Q | clkdiv_2/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
5 | 0.708 | clkdiv_1/count_8_s0/Q | clkdiv_1/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.708 |
6 | 0.709 | clkdiv_4/count_6_s0/Q | clkdiv_4/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
7 | 0.709 | clkdiv_4/count_10_s0/Q | clkdiv_4/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
8 | 0.709 | clkdiv_4/count_14_s0/Q | clkdiv_4/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
9 | 0.709 | clkdiv_3/count_24_s0/Q | clkdiv_3/count_24_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
10 | 0.709 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.709 |
11 | 0.710 | clkdiv_4/count_2_s0/Q | clkdiv_4/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
12 | 0.710 | clkdiv_4/count_4_s0/Q | clkdiv_4/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
13 | 0.710 | clkdiv_3/count_5_s0/Q | clkdiv_3/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
14 | 0.710 | clkdiv_3/count_13_s0/Q | clkdiv_3/count_13_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
15 | 0.710 | clkdiv_3/count_18_s0/Q | clkdiv_3/count_18_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
16 | 0.710 | clkdiv_2/count_17_s0/Q | clkdiv_2/count_17_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.710 |
17 | 0.711 | clkdiv_5/count_5_s0/Q | clkdiv_5/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.711 |
18 | 0.711 | clkdiv_3/count_8_s0/Q | clkdiv_3/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.711 |
19 | 0.711 | clkdiv_2/count_7_s0/Q | clkdiv_2/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.711 |
20 | 0.711 | clkdiv_1/count_4_s0/Q | clkdiv_1/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.711 |
21 | 0.712 | mux7seg_1/col_0_s0/Q | mux7seg_1/col_0_s0/D | clk160hz:[R] | clk160hz:[R] | 0.000 | 0.000 | 0.712 |
22 | 0.715 | leg4_1/inst1/adr_0_s0/Q | leg4_1/inst1/adr_0_s0/D | leg4_clk:[R] | leg4_clk:[R] | 0.000 | 0.000 | 0.715 |
23 | 0.892 | clkdiv_4/count_1_s0/Q | clkdiv_4/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.892 |
24 | 0.892 | clkdiv_3/count_15_s0/Q | clkdiv_3/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.892 |
25 | 0.892 | clkdiv_3/count_16_s0/Q | clkdiv_3/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.892 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_16_s0 |
2 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_14_s0 |
3 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_10_s0 |
4 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_1/count_2_s0 |
5 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_2/count_9_s0 |
6 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_3/count_3_s0 |
7 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_3/count_4_s0 |
8 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_2/count_10_s0 |
9 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_3/count_5_s0 |
10 | 16.269 | 17.519 | 1.250 | Low Pulse Width | clk27mhz | clkdiv_3/count_6_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 28.187 |
Data Arrival Time | 10.782 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_21_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.683 | 1.343 | tNET | FF | 1 | R13C18[2][B] | clkdiv_3/n40_s2/I3 |
10.782 | 1.099 | tINS | FF | 1 | R13C18[2][B] | clkdiv_3/n40_s2/F |
10.782 | 0.000 | tNET | FF | 1 | R13C18[2][B] | clkdiv_3/count_21_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C18[2][B] | clkdiv_3/count_21_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C18[2][B] | clkdiv_3/count_21_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.081, 48.295%; route: 3.911, 46.281%; tC2Q: 0.458, 5.424% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path2
Path Summary:
Slack | 28.239 |
Data Arrival Time | 10.730 |
Data Required Time | 38.969 |
From | clkdiv_4/count_5_s0 |
To | clkdiv_4/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C27[0][B] | clkdiv_4/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C27[0][B] | clkdiv_4/count_5_s0/Q |
3.618 | 0.828 | tNET | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/I1 |
4.650 | 1.032 | tINS | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/F |
6.270 | 1.620 | tNET | FF | 1 | R14C26[3][B] | clkdiv_4/n61_s4/I1 |
7.331 | 1.061 | tINS | FR | 1 | R14C26[3][B] | clkdiv_4/n61_s4/F |
7.750 | 0.419 | tNET | RR | 1 | R14C27[2][B] | clkdiv_4/n61_s9/I0 |
8.782 | 1.032 | tINS | RF | 15 | R14C27[2][B] | clkdiv_4/n61_s9/F |
9.631 | 0.849 | tNET | FF | 1 | R13C27[1][B] | clkdiv_4/n58_s2/I2 |
10.730 | 1.099 | tINS | FF | 1 | R13C27[1][B] | clkdiv_4/n58_s2/F |
10.730 | 0.000 | tNET | FF | 1 | R13C27[1][B] | clkdiv_4/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C27[1][B] | clkdiv_4/count_3_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C27[1][B] | clkdiv_4/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.224, 50.300%; route: 3.715, 44.242%; tC2Q: 0.458, 5.458% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path3
Path Summary:
Slack | 28.240 |
Data Arrival Time | 10.729 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_22_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.697 | 1.357 | tNET | FF | 1 | R13C18[2][A] | clkdiv_3/n39_s2/I2 |
10.729 | 1.032 | tINS | FF | 1 | R13C18[2][A] | clkdiv_3/n39_s2/F |
10.729 | 0.000 | tNET | FF | 1 | R13C18[2][A] | clkdiv_3/count_22_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C18[2][A] | clkdiv_3/count_22_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C18[2][A] | clkdiv_3/count_22_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.014, 47.804%; route: 3.925, 46.738%; tC2Q: 0.458, 5.458% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path4
Path Summary:
Slack | 28.240 |
Data Arrival Time | 10.729 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_24_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.697 | 1.357 | tNET | FF | 1 | R13C18[1][A] | clkdiv_3/n37_s2/I3 |
10.729 | 1.032 | tINS | FF | 1 | R13C18[1][A] | clkdiv_3/n37_s2/F |
10.729 | 0.000 | tNET | FF | 1 | R13C18[1][A] | clkdiv_3/count_24_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C18[1][A] | clkdiv_3/count_24_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C18[1][A] | clkdiv_3/count_24_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.014, 47.804%; route: 3.925, 46.738%; tC2Q: 0.458, 5.458% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path5
Path Summary:
Slack | 28.251 |
Data Arrival Time | 10.718 |
Data Required Time | 38.969 |
From | clkdiv_4/count_5_s0 |
To | clkdiv_4/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C27[0][B] | clkdiv_4/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C27[0][B] | clkdiv_4/count_5_s0/Q |
3.618 | 0.828 | tNET | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/I1 |
4.650 | 1.032 | tINS | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/F |
6.270 | 1.620 | tNET | FF | 1 | R14C26[3][B] | clkdiv_4/n61_s4/I1 |
7.331 | 1.061 | tINS | FR | 1 | R14C26[3][B] | clkdiv_4/n61_s4/F |
7.750 | 0.419 | tNET | RR | 1 | R14C27[2][B] | clkdiv_4/n61_s9/I0 |
8.782 | 1.032 | tINS | RF | 15 | R14C27[2][B] | clkdiv_4/n61_s9/F |
9.619 | 0.837 | tNET | FF | 1 | R13C26[2][A] | clkdiv_4/n53_s2/I3 |
10.718 | 1.099 | tINS | FF | 1 | R13C26[2][A] | clkdiv_4/n53_s2/F |
10.718 | 0.000 | tNET | FF | 1 | R13C26[2][A] | clkdiv_4/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C26[2][A] | clkdiv_4/count_8_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C26[2][A] | clkdiv_4/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.224, 50.368%; route: 3.704, 44.167%; tC2Q: 0.458, 5.465% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path6
Path Summary:
Slack | 28.254 |
Data Arrival Time | 10.715 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_13_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.683 | 1.343 | tNET | FF | 1 | R13C19[0][A] | clkdiv_3/n48_s2/I2 |
10.715 | 1.032 | tINS | FF | 1 | R13C19[0][A] | clkdiv_3/n48_s2/F |
10.715 | 0.000 | tNET | FF | 1 | R13C19[0][A] | clkdiv_3/count_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C19[0][A] | clkdiv_3/count_13_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C19[0][A] | clkdiv_3/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.014, 47.882%; route: 3.911, 46.651%; tC2Q: 0.458, 5.467% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path7
Path Summary:
Slack | 28.318 |
Data Arrival Time | 10.651 |
Data Required Time | 38.969 |
From | clkdiv_4/count_5_s0 |
To | clkdiv_4/count_9_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C27[0][B] | clkdiv_4/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C27[0][B] | clkdiv_4/count_5_s0/Q |
3.618 | 0.828 | tNET | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/I1 |
4.650 | 1.032 | tINS | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/F |
6.270 | 1.620 | tNET | FF | 1 | R14C26[3][B] | clkdiv_4/n61_s4/I1 |
7.331 | 1.061 | tINS | FR | 1 | R14C26[3][B] | clkdiv_4/n61_s4/F |
7.750 | 0.419 | tNET | RR | 1 | R14C27[2][B] | clkdiv_4/n61_s9/I0 |
8.782 | 1.032 | tINS | RF | 15 | R14C27[2][B] | clkdiv_4/n61_s9/F |
9.619 | 0.837 | tNET | FF | 1 | R15C26[1][B] | clkdiv_4/n52_s2/I3 |
10.651 | 1.032 | tINS | FF | 1 | R15C26[1][B] | clkdiv_4/n52_s2/F |
10.651 | 0.000 | tNET | FF | 1 | R15C26[1][B] | clkdiv_4/count_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C26[1][B] | clkdiv_4/count_9_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C26[1][B] | clkdiv_4/count_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.157, 49.968%; route: 3.704, 44.523%; tC2Q: 0.458, 5.509% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path8
Path Summary:
Slack | 28.391 |
Data Arrival Time | 10.578 |
Data Required Time | 38.969 |
From | clkdiv_2/count_2_s0 |
To | clkdiv_2/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C23[2][A] | clkdiv_2/count_2_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 3 | R13C23[2][A] | clkdiv_2/count_2_s0/Q |
3.609 | 0.819 | tNET | FF | 1 | R16C23[1][B] | clkdiv_2/n57_s4/I2 |
4.641 | 1.032 | tINS | FF | 9 | R16C23[1][B] | clkdiv_2/n57_s4/F |
5.968 | 1.327 | tNET | FF | 1 | R13C21[3][A] | clkdiv_2/n48_s4/I2 |
7.067 | 1.099 | tINS | FF | 9 | R13C21[3][A] | clkdiv_2/n48_s4/F |
7.903 | 0.837 | tNET | FF | 1 | R14C22[2][B] | clkdiv_2/n45_s5/I0 |
8.935 | 1.032 | tINS | FF | 1 | R14C22[2][B] | clkdiv_2/n45_s5/F |
9.756 | 0.821 | tNET | FF | 1 | R16C22[0][A] | clkdiv_2/n45_s2/I2 |
10.578 | 0.822 | tINS | FF | 1 | R16C22[0][A] | clkdiv_2/n45_s2/F |
10.578 | 0.000 | tNET | FF | 1 | R16C22[0][A] | clkdiv_2/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R16C22[0][A] | clkdiv_2/count_16_s0/CLK |
38.969 | -0.400 | tSu | 1 | R16C22[0][A] | clkdiv_2/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.985, 48.324%; route: 3.803, 46.118%; tC2Q: 0.458, 5.558% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path9
Path Summary:
Slack | 28.457 |
Data Arrival Time | 10.512 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.690 | 1.350 | tNET | FF | 1 | R13C18[0][A] | clkdiv_3/n53_s2/I2 |
10.512 | 0.822 | tINS | FF | 1 | R13C18[0][A] | clkdiv_3/n53_s2/F |
10.512 | 0.000 | tNET | FF | 1 | R13C18[0][A] | clkdiv_3/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C18[0][A] | clkdiv_3/count_8_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C18[0][A] | clkdiv_3/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.804, 46.504%; route: 3.918, 47.893%; tC2Q: 0.458, 5.603% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path10
Path Summary:
Slack | 28.466 |
Data Arrival Time | 10.503 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.681 | 1.341 | tNET | FF | 1 | R13C19[1][B] | clkdiv_3/n51_s2/I3 |
10.503 | 0.822 | tINS | FF | 1 | R13C19[1][B] | clkdiv_3/n51_s2/F |
10.503 | 0.000 | tNET | FF | 1 | R13C19[1][B] | clkdiv_3/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C19[1][B] | clkdiv_3/count_10_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C19[1][B] | clkdiv_3/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.804, 46.555%; route: 3.909, 47.836%; tC2Q: 0.458, 5.609% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path11
Path Summary:
Slack | 28.466 |
Data Arrival Time | 10.503 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_11_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.681 | 1.341 | tNET | FF | 1 | R13C19[1][A] | clkdiv_3/n50_s2/I2 |
10.503 | 0.822 | tINS | FF | 1 | R13C19[1][A] | clkdiv_3/n50_s2/F |
10.503 | 0.000 | tNET | FF | 1 | R13C19[1][A] | clkdiv_3/count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C19[1][A] | clkdiv_3/count_11_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C19[1][A] | clkdiv_3/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.804, 46.555%; route: 3.909, 47.836%; tC2Q: 0.458, 5.609% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path12
Path Summary:
Slack | 28.466 |
Data Arrival Time | 10.503 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_12_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.681 | 1.341 | tNET | FF | 1 | R13C19[0][B] | clkdiv_3/n49_s2/I3 |
10.503 | 0.822 | tINS | FF | 1 | R13C19[0][B] | clkdiv_3/n49_s2/F |
10.503 | 0.000 | tNET | FF | 1 | R13C19[0][B] | clkdiv_3/count_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C19[0][B] | clkdiv_3/count_12_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C19[0][B] | clkdiv_3/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.804, 46.555%; route: 3.909, 47.836%; tC2Q: 0.458, 5.609% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path13
Path Summary:
Slack | 28.503 |
Data Arrival Time | 10.466 |
Data Required Time | 38.969 |
From | clkdiv_4/count_5_s0 |
To | clkdiv_4/count_7_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C27[0][B] | clkdiv_4/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C27[0][B] | clkdiv_4/count_5_s0/Q |
3.618 | 0.828 | tNET | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/I1 |
4.650 | 1.032 | tINS | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/F |
6.270 | 1.620 | tNET | FF | 1 | R14C26[3][B] | clkdiv_4/n61_s4/I1 |
7.331 | 1.061 | tINS | FR | 1 | R14C26[3][B] | clkdiv_4/n61_s4/F |
7.750 | 0.419 | tNET | RR | 1 | R14C27[2][B] | clkdiv_4/n61_s9/I0 |
8.782 | 1.032 | tINS | RF | 15 | R14C27[2][B] | clkdiv_4/n61_s9/F |
9.644 | 0.862 | tNET | FF | 1 | R13C26[2][B] | clkdiv_4/n54_s2/I2 |
10.466 | 0.822 | tINS | FF | 1 | R13C26[2][B] | clkdiv_4/n54_s2/F |
10.466 | 0.000 | tNET | FF | 1 | R13C26[2][B] | clkdiv_4/count_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C26[2][B] | clkdiv_4/count_7_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C26[2][B] | clkdiv_4/count_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.947, 48.523%; route: 3.729, 45.843%; tC2Q: 0.458, 5.635% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path14
Path Summary:
Slack | 28.503 |
Data Arrival Time | 10.466 |
Data Required Time | 38.969 |
From | clkdiv_4/count_5_s0 |
To | clkdiv_4/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C27[0][B] | clkdiv_4/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C27[0][B] | clkdiv_4/count_5_s0/Q |
3.618 | 0.828 | tNET | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/I1 |
4.650 | 1.032 | tINS | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/F |
6.270 | 1.620 | tNET | FF | 1 | R14C26[3][B] | clkdiv_4/n61_s4/I1 |
7.331 | 1.061 | tINS | FR | 1 | R14C26[3][B] | clkdiv_4/n61_s4/F |
7.750 | 0.419 | tNET | RR | 1 | R14C27[2][B] | clkdiv_4/n61_s9/I0 |
8.782 | 1.032 | tINS | RF | 15 | R14C27[2][B] | clkdiv_4/n61_s9/F |
9.644 | 0.862 | tNET | FF | 1 | R13C26[1][A] | clkdiv_4/n51_s2/I2 |
10.466 | 0.822 | tINS | FF | 1 | R13C26[1][A] | clkdiv_4/n51_s2/F |
10.466 | 0.000 | tNET | FF | 1 | R13C26[1][A] | clkdiv_4/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C26[1][A] | clkdiv_4/count_10_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C26[1][A] | clkdiv_4/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.947, 48.523%; route: 3.729, 45.843%; tC2Q: 0.458, 5.635% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path15
Path Summary:
Slack | 28.503 |
Data Arrival Time | 10.466 |
Data Required Time | 38.969 |
From | clkdiv_4/count_5_s0 |
To | clkdiv_4/count_11_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C27[0][B] | clkdiv_4/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C27[0][B] | clkdiv_4/count_5_s0/Q |
3.618 | 0.828 | tNET | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/I1 |
4.650 | 1.032 | tINS | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/F |
6.270 | 1.620 | tNET | FF | 1 | R14C26[3][B] | clkdiv_4/n61_s4/I1 |
7.331 | 1.061 | tINS | FR | 1 | R14C26[3][B] | clkdiv_4/n61_s4/F |
7.750 | 0.419 | tNET | RR | 1 | R14C27[2][B] | clkdiv_4/n61_s9/I0 |
8.782 | 1.032 | tINS | RF | 15 | R14C27[2][B] | clkdiv_4/n61_s9/F |
9.644 | 0.862 | tNET | FF | 1 | R13C26[0][B] | clkdiv_4/n50_s2/I3 |
10.466 | 0.822 | tINS | FF | 1 | R13C26[0][B] | clkdiv_4/n50_s2/F |
10.466 | 0.000 | tNET | FF | 1 | R13C26[0][B] | clkdiv_4/count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C26[0][B] | clkdiv_4/count_11_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C26[0][B] | clkdiv_4/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.947, 48.523%; route: 3.729, 45.843%; tC2Q: 0.458, 5.635% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path16
Path Summary:
Slack | 28.504 |
Data Arrival Time | 10.465 |
Data Required Time | 38.969 |
From | clkdiv_3/count_11_s0 |
To | clkdiv_3/count_18_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C19[1][A] | clkdiv_3/count_11_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C19[1][A] | clkdiv_3/count_11_s0/Q |
3.951 | 1.160 | tNET | FF | 1 | R14C19[0][A] | clkdiv_3/n42_s5/I1 |
5.050 | 1.099 | tINS | FF | 2 | R14C19[0][A] | clkdiv_3/n42_s5/F |
5.545 | 0.496 | tNET | FF | 1 | R14C20[2][B] | clkdiv_3/n42_s3/I2 |
6.171 | 0.626 | tINS | FF | 5 | R14C20[2][B] | clkdiv_3/n42_s3/F |
7.017 | 0.846 | tNET | FF | 1 | R14C18[3][A] | clkdiv_3/n44_s3/I1 |
8.116 | 1.099 | tINS | FF | 3 | R14C18[3][A] | clkdiv_3/n44_s3/F |
9.433 | 1.316 | tNET | FF | 1 | R16C20[0][A] | clkdiv_3/n43_s2/I1 |
10.465 | 1.032 | tINS | FF | 1 | R16C20[0][A] | clkdiv_3/n43_s2/F |
10.465 | 0.000 | tNET | FF | 1 | R16C20[0][A] | clkdiv_3/count_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R16C20[0][A] | clkdiv_3/count_18_s0/CLK |
38.969 | -0.400 | tSu | 1 | R16C20[0][A] | clkdiv_3/count_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.856, 47.412%; route: 3.819, 46.952%; tC2Q: 0.458, 5.636% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path17
Path Summary:
Slack | 28.659 |
Data Arrival Time | 10.309 |
Data Required Time | 38.969 |
From | clkdiv_4/count_5_s0 |
To | clkdiv_4/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C27[0][B] | clkdiv_4/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C27[0][B] | clkdiv_4/count_5_s0/Q |
3.618 | 0.828 | tNET | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/I1 |
4.650 | 1.032 | tINS | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/F |
6.270 | 1.620 | tNET | FF | 1 | R14C26[3][B] | clkdiv_4/n61_s4/I1 |
7.331 | 1.061 | tINS | FR | 1 | R14C26[3][B] | clkdiv_4/n61_s4/F |
7.750 | 0.419 | tNET | RR | 1 | R14C27[2][B] | clkdiv_4/n61_s9/I0 |
8.776 | 1.026 | tINS | RR | 15 | R14C27[2][B] | clkdiv_4/n61_s9/F |
9.210 | 0.434 | tNET | RR | 1 | R13C27[2][B] | clkdiv_4/n61_s2/I1 |
10.309 | 1.099 | tINS | RF | 1 | R13C27[2][B] | clkdiv_4/n61_s2/F |
10.309 | 0.000 | tNET | FF | 1 | R13C27[2][B] | clkdiv_4/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C27[2][B] | clkdiv_4/count_0_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C27[2][B] | clkdiv_4/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.218, 52.874%; route: 3.301, 41.381%; tC2Q: 0.458, 5.745% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path18
Path Summary:
Slack | 28.662 |
Data Arrival Time | 10.307 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_14_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.681 | 1.341 | tNET | FF | 1 | R13C19[2][B] | clkdiv_3/n47_s4/I3 |
10.307 | 0.626 | tINS | FF | 1 | R13C19[2][B] | clkdiv_3/n47_s4/F |
10.307 | 0.000 | tNET | FF | 1 | R13C19[2][B] | clkdiv_3/count_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C19[2][B] | clkdiv_3/count_14_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C19[2][B] | clkdiv_3/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.608, 45.242%; route: 3.909, 49.011%; tC2Q: 0.458, 5.747% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path19
Path Summary:
Slack | 28.662 |
Data Arrival Time | 10.307 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.208 | 0.868 | tNET | FF | 1 | R13C20[2][B] | clkdiv_3/n61_s2/I1 |
10.307 | 1.099 | tINS | FF | 1 | R13C20[2][B] | clkdiv_3/n61_s2/F |
10.307 | 0.000 | tNET | FF | 1 | R13C20[2][B] | clkdiv_3/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C20[2][B] | clkdiv_3/count_0_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C20[2][B] | clkdiv_3/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.081, 51.174%; route: 3.435, 43.078%; tC2Q: 0.458, 5.747% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path20
Path Summary:
Slack | 28.676 |
Data Arrival Time | 10.293 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_5_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.194 | 0.854 | tNET | FF | 1 | R15C20[0][A] | clkdiv_3/n56_s4/I3 |
10.293 | 1.099 | tINS | FF | 1 | R15C20[0][A] | clkdiv_3/n56_s4/F |
10.293 | 0.000 | tNET | FF | 1 | R15C20[0][A] | clkdiv_3/count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C20[0][A] | clkdiv_3/count_5_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C20[0][A] | clkdiv_3/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.081, 51.262%; route: 3.422, 42.981%; tC2Q: 0.458, 5.757% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path21
Path Summary:
Slack | 28.712 |
Data Arrival Time | 10.257 |
Data Required Time | 38.969 |
From | clkdiv_4/count_5_s0 |
To | clkdiv_4/count_12_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C27[0][B] | clkdiv_4/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C27[0][B] | clkdiv_4/count_5_s0/Q |
3.618 | 0.828 | tNET | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/I1 |
4.650 | 1.032 | tINS | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/F |
6.270 | 1.620 | tNET | FF | 1 | R14C26[3][B] | clkdiv_4/n61_s4/I1 |
7.331 | 1.061 | tINS | FR | 1 | R14C26[3][B] | clkdiv_4/n61_s4/F |
7.750 | 0.419 | tNET | RR | 1 | R14C27[2][B] | clkdiv_4/n61_s9/I0 |
8.782 | 1.032 | tINS | RF | 15 | R14C27[2][B] | clkdiv_4/n61_s9/F |
9.631 | 0.849 | tNET | FF | 1 | R15C26[0][B] | clkdiv_4/n49_s2/I2 |
10.257 | 0.626 | tINS | FF | 1 | R15C26[0][B] | clkdiv_4/n49_s2/F |
10.257 | 0.000 | tNET | FF | 1 | R15C26[0][B] | clkdiv_4/count_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R15C26[0][B] | clkdiv_4/count_12_s0/CLK |
38.969 | -0.400 | tSu | 1 | R15C26[0][B] | clkdiv_4/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.751, 47.333%; route: 3.715, 46.883%; tC2Q: 0.458, 5.784% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path22
Path Summary:
Slack | 28.719 |
Data Arrival Time | 10.250 |
Data Required Time | 38.969 |
From | clkdiv_4/count_5_s0 |
To | clkdiv_4/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R13C27[0][B] | clkdiv_4/count_5_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R13C27[0][B] | clkdiv_4/count_5_s0/Q |
3.618 | 0.828 | tNET | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/I1 |
4.650 | 1.032 | tINS | FF | 1 | R13C26[3][A] | clkdiv_4/n61_s6/F |
6.270 | 1.620 | tNET | FF | 1 | R14C26[3][B] | clkdiv_4/n61_s4/I1 |
7.331 | 1.061 | tINS | FR | 1 | R14C26[3][B] | clkdiv_4/n61_s4/F |
7.750 | 0.419 | tNET | RR | 1 | R14C27[2][B] | clkdiv_4/n61_s9/I0 |
8.776 | 1.026 | tINS | RR | 15 | R14C27[2][B] | clkdiv_4/n61_s9/F |
9.218 | 0.442 | tNET | RR | 1 | R13C27[2][A] | clkdiv_4/n60_s2/I2 |
10.250 | 1.032 | tINS | RF | 1 | R13C27[2][A] | clkdiv_4/n60_s2/F |
10.250 | 0.000 | tNET | FF | 1 | R13C27[2][A] | clkdiv_4/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C27[2][A] | clkdiv_4/count_1_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C27[2][A] | clkdiv_4/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.151, 52.422%; route: 3.309, 41.790%; tC2Q: 0.458, 5.788% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path23
Path Summary:
Slack | 28.729 |
Data Arrival Time | 10.240 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.208 | 0.868 | tNET | FF | 1 | R13C20[1][B] | clkdiv_3/n58_s2/I3 |
10.240 | 1.032 | tINS | FF | 1 | R13C20[1][B] | clkdiv_3/n58_s2/F |
10.240 | 0.000 | tNET | FF | 1 | R13C20[1][B] | clkdiv_3/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C20[1][B] | clkdiv_3/count_3_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C20[1][B] | clkdiv_3/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.014, 50.761%; route: 3.435, 43.443%; tC2Q: 0.458, 5.796% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path24
Path Summary:
Slack | 28.729 |
Data Arrival Time | 10.240 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_4_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.208 | 0.868 | tNET | FF | 1 | R13C20[1][A] | clkdiv_3/n57_s2/I2 |
10.240 | 1.032 | tINS | FF | 1 | R13C20[1][A] | clkdiv_3/n57_s2/F |
10.240 | 0.000 | tNET | FF | 1 | R13C20[1][A] | clkdiv_3/count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R13C20[1][A] | clkdiv_3/count_4_s0/CLK |
38.969 | -0.400 | tSu | 1 | R13C20[1][A] | clkdiv_3/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 4.014, 50.761%; route: 3.435, 43.443%; tC2Q: 0.458, 5.796% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Path25
Path Summary:
Slack | 28.785 |
Data Arrival Time | 10.184 |
Data Required Time | 38.969 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_20_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
2.332 | 0.244 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
2.790 | 0.458 | tC2Q | RF | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
4.113 | 1.322 | tNET | FF | 1 | R13C20[0][A] | clkdiv_3/n57_s3/I0 |
5.212 | 1.099 | tINS | FF | 7 | R13C20[0][A] | clkdiv_3/n57_s3/F |
6.038 | 0.826 | tNET | FF | 1 | R15C20[1][B] | clkdiv_3/n61_s4/I1 |
7.099 | 1.061 | tINS | FR | 1 | R15C20[1][B] | clkdiv_3/n61_s4/F |
7.518 | 0.419 | tNET | RR | 1 | R16C20[2][A] | clkdiv_3/n61_s3/I0 |
8.340 | 0.822 | tINS | RF | 25 | R16C20[2][A] | clkdiv_3/n61_s3/F |
9.362 | 1.022 | tNET | FF | 1 | R14C18[2][B] | clkdiv_3/n41_s2/I3 |
10.184 | 0.822 | tINS | FF | 1 | R14C18[2][B] | clkdiv_3/n41_s2/F |
10.184 | 0.000 | tNET | FF | 1 | R14C18[2][B] | clkdiv_3/count_20_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
39.369 | 0.244 | tNET | RR | 1 | R14C18[2][B] | clkdiv_3/count_20_s0/CLK |
38.969 | -0.400 | tSu | 1 | R14C18[2][B] | clkdiv_3/count_20_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Arrival Data Path Delay | cell: 3.804, 48.446%; route: 3.590, 45.717%; tC2Q: 0.458, 5.837% |
Required Clock Path Delay | cell: 2.088, 89.539%; route: 0.244, 10.461% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_5/count_17_s0 |
To | clkdiv_5/count_17_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C35[1][A] | clkdiv_5/count_17_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R16C35[1][A] | clkdiv_5/count_17_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R16C35[1][A] | clkdiv_5/n44_s2/I2 |
2.284 | 0.372 | tINS | RF | 1 | R16C35[1][A] | clkdiv_5/n44_s2/F |
2.284 | 0.000 | tNET | FF | 1 | R16C35[1][A] | clkdiv_5/count_17_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C35[1][A] | clkdiv_5/count_17_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C35[1][A] | clkdiv_5/count_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path2
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_3/count_1_s0 |
To | clkdiv_3/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R17C20[0][A] | clkdiv_3/count_1_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/n60_s2/I0 |
2.284 | 0.372 | tINS | RF | 1 | R17C20[0][A] | clkdiv_3/n60_s2/F |
2.284 | 0.000 | tNET | FF | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R17C20[0][A] | clkdiv_3/count_1_s0/CLK |
1.577 | 0.000 | tHld | 1 | R17C20[0][A] | clkdiv_3/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path3
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_3/count_11_s0 |
To | clkdiv_3/count_11_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C19[1][A] | clkdiv_3/count_11_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C19[1][A] | clkdiv_3/count_11_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R13C19[1][A] | clkdiv_3/n50_s2/I0 |
2.284 | 0.372 | tINS | RF | 1 | R13C19[1][A] | clkdiv_3/n50_s2/F |
2.284 | 0.000 | tNET | FF | 1 | R13C19[1][A] | clkdiv_3/count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C19[1][A] | clkdiv_3/count_11_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C19[1][A] | clkdiv_3/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path4
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_2/count_0_s0 |
To | clkdiv_2/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C22[1][A] | clkdiv_2/count_0_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R16C22[1][A] | clkdiv_2/count_0_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R16C22[1][A] | clkdiv_2/n61_s14/I2 |
2.284 | 0.372 | tINS | RF | 1 | R16C22[1][A] | clkdiv_2/n61_s14/F |
2.284 | 0.000 | tNET | FF | 1 | R16C22[1][A] | clkdiv_2/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C22[1][A] | clkdiv_2/count_0_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C22[1][A] | clkdiv_2/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path5
Path Summary:
Slack | 0.708 |
Data Arrival Time | 2.284 |
Data Required Time | 1.577 |
From | clkdiv_1/count_8_s0 |
To | clkdiv_1/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C24[1][A] | clkdiv_1/count_8_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C24[1][A] | clkdiv_1/count_8_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R13C24[1][A] | clkdiv_1/n53_s4/I0 |
2.284 | 0.372 | tINS | RF | 1 | R13C24[1][A] | clkdiv_1/n53_s4/F |
2.284 | 0.000 | tNET | FF | 1 | R13C24[1][A] | clkdiv_1/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C24[1][A] | clkdiv_1/count_8_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C24[1][A] | clkdiv_1/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.565%; route: 0.002, 0.334%; tC2Q: 0.333, 47.101% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path6
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_4/count_6_s0 |
To | clkdiv_4/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C27[0][A] | clkdiv_4/count_6_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R13C27[0][A] | clkdiv_4/count_6_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C27[0][A] | clkdiv_4/n55_s2/I2 |
2.285 | 0.372 | tINS | RF | 1 | R13C27[0][A] | clkdiv_4/n55_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C27[0][A] | clkdiv_4/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C27[0][A] | clkdiv_4/count_6_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C27[0][A] | clkdiv_4/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path7
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_4/count_10_s0 |
To | clkdiv_4/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C26[1][A] | clkdiv_4/count_10_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R13C26[1][A] | clkdiv_4/count_10_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C26[1][A] | clkdiv_4/n51_s2/I0 |
2.285 | 0.372 | tINS | RF | 1 | R13C26[1][A] | clkdiv_4/n51_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C26[1][A] | clkdiv_4/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C26[1][A] | clkdiv_4/count_10_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C26[1][A] | clkdiv_4/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path8
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_4/count_14_s0 |
To | clkdiv_4/count_14_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C27[1][A] | clkdiv_4/count_14_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R14C27[1][A] | clkdiv_4/count_14_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R14C27[1][A] | clkdiv_4/n47_s2/I2 |
2.285 | 0.372 | tINS | RF | 1 | R14C27[1][A] | clkdiv_4/n47_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R14C27[1][A] | clkdiv_4/count_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C27[1][A] | clkdiv_4/count_14_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C27[1][A] | clkdiv_4/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path9
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_3/count_24_s0 |
To | clkdiv_3/count_24_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C18[1][A] | clkdiv_3/count_24_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C18[1][A] | clkdiv_3/count_24_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C18[1][A] | clkdiv_3/n37_s2/I2 |
2.285 | 0.372 | tINS | RF | 1 | R13C18[1][A] | clkdiv_3/n37_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C18[1][A] | clkdiv_3/count_24_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C18[1][A] | clkdiv_3/count_24_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C18[1][A] | clkdiv_3/count_24_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path10
Path Summary:
Slack | 0.709 |
Data Arrival Time | 2.285 |
Data Required Time | 1.577 |
From | clkdiv_1/count_6_s0 |
To | clkdiv_1/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C25[0][A] | clkdiv_1/count_6_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R13C25[0][A] | clkdiv_1/count_6_s0/Q |
1.913 | 0.004 | tNET | RR | 1 | R13C25[0][A] | clkdiv_1/n55_s2/I0 |
2.285 | 0.372 | tINS | RF | 1 | R13C25[0][A] | clkdiv_1/n55_s2/F |
2.285 | 0.000 | tNET | FF | 1 | R13C25[0][A] | clkdiv_1/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C25[0][A] | clkdiv_1/count_6_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C25[0][A] | clkdiv_1/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.478%; route: 0.004, 0.500%; tC2Q: 0.333, 47.023% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path11
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_4/count_2_s0 |
To | clkdiv_4/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C27[0][A] | clkdiv_4/count_2_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R14C27[0][A] | clkdiv_4/count_2_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R14C27[0][A] | clkdiv_4/n59_s4/I0 |
2.287 | 0.372 | tINS | RF | 1 | R14C27[0][A] | clkdiv_4/n59_s4/F |
2.287 | 0.000 | tNET | FF | 1 | R14C27[0][A] | clkdiv_4/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C27[0][A] | clkdiv_4/count_2_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C27[0][A] | clkdiv_4/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path12
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_4/count_4_s0 |
To | clkdiv_4/count_4_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C27[1][A] | clkdiv_4/count_4_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R13C27[1][A] | clkdiv_4/count_4_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R13C27[1][A] | clkdiv_4/n57_s2/I0 |
2.287 | 0.372 | tINS | RF | 1 | R13C27[1][A] | clkdiv_4/n57_s2/F |
2.287 | 0.000 | tNET | FF | 1 | R13C27[1][A] | clkdiv_4/count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C27[1][A] | clkdiv_4/count_4_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C27[1][A] | clkdiv_4/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path13
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_3/count_5_s0 |
To | clkdiv_3/count_5_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C20[0][A] | clkdiv_3/count_5_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 6 | R15C20[0][A] | clkdiv_3/count_5_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R15C20[0][A] | clkdiv_3/n56_s4/I0 |
2.287 | 0.372 | tINS | RF | 1 | R15C20[0][A] | clkdiv_3/n56_s4/F |
2.287 | 0.000 | tNET | FF | 1 | R15C20[0][A] | clkdiv_3/count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C20[0][A] | clkdiv_3/count_5_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C20[0][A] | clkdiv_3/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path14
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_3/count_13_s0 |
To | clkdiv_3/count_13_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C19[0][A] | clkdiv_3/count_13_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R13C19[0][A] | clkdiv_3/count_13_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R13C19[0][A] | clkdiv_3/n48_s2/I0 |
2.287 | 0.372 | tINS | RF | 1 | R13C19[0][A] | clkdiv_3/n48_s2/F |
2.287 | 0.000 | tNET | FF | 1 | R13C19[0][A] | clkdiv_3/count_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C19[0][A] | clkdiv_3/count_13_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C19[0][A] | clkdiv_3/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path15
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_3/count_18_s0 |
To | clkdiv_3/count_18_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C20[0][A] | clkdiv_3/count_18_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R16C20[0][A] | clkdiv_3/count_18_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R16C20[0][A] | clkdiv_3/n43_s2/I2 |
2.287 | 0.372 | tINS | RF | 1 | R16C20[0][A] | clkdiv_3/n43_s2/F |
2.287 | 0.000 | tNET | FF | 1 | R16C20[0][A] | clkdiv_3/count_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R16C20[0][A] | clkdiv_3/count_18_s0/CLK |
1.577 | 0.000 | tHld | 1 | R16C20[0][A] | clkdiv_3/count_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path16
Path Summary:
Slack | 0.710 |
Data Arrival Time | 2.287 |
Data Required Time | 1.577 |
From | clkdiv_2/count_17_s0 |
To | clkdiv_2/count_17_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C23[0][A] | clkdiv_2/count_17_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 5 | R14C23[0][A] | clkdiv_2/count_17_s0/Q |
1.915 | 0.005 | tNET | RR | 1 | R14C23[0][A] | clkdiv_2/n44_s7/I3 |
2.287 | 0.372 | tINS | RF | 1 | R14C23[0][A] | clkdiv_2/n44_s7/F |
2.287 | 0.000 | tNET | FF | 1 | R14C23[0][A] | clkdiv_2/count_17_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C23[0][A] | clkdiv_2/count_17_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C23[0][A] | clkdiv_2/count_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.390%; route: 0.005, 0.665%; tC2Q: 0.333, 46.945% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path17
Path Summary:
Slack | 0.711 |
Data Arrival Time | 2.288 |
Data Required Time | 1.577 |
From | clkdiv_5/count_5_s0 |
To | clkdiv_5/count_5_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C35[0][A] | clkdiv_5/count_5_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 6 | R13C35[0][A] | clkdiv_5/count_5_s0/Q |
1.916 | 0.006 | tNET | RR | 1 | R13C35[0][A] | clkdiv_5/n56_s2/I3 |
2.288 | 0.372 | tINS | RF | 1 | R13C35[0][A] | clkdiv_5/n56_s2/F |
2.288 | 0.000 | tNET | FF | 1 | R13C35[0][A] | clkdiv_5/count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C35[0][A] | clkdiv_5/count_5_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C35[0][A] | clkdiv_5/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path18
Path Summary:
Slack | 0.711 |
Data Arrival Time | 2.288 |
Data Required Time | 1.577 |
From | clkdiv_3/count_8_s0 |
To | clkdiv_3/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C18[0][A] | clkdiv_3/count_8_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 9 | R13C18[0][A] | clkdiv_3/count_8_s0/Q |
1.916 | 0.006 | tNET | RR | 1 | R13C18[0][A] | clkdiv_3/n53_s2/I0 |
2.288 | 0.372 | tINS | RF | 1 | R13C18[0][A] | clkdiv_3/n53_s2/F |
2.288 | 0.000 | tNET | FF | 1 | R13C18[0][A] | clkdiv_3/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C18[0][A] | clkdiv_3/count_8_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C18[0][A] | clkdiv_3/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path19
Path Summary:
Slack | 0.711 |
Data Arrival Time | 2.288 |
Data Required Time | 1.577 |
From | clkdiv_2/count_7_s0 |
To | clkdiv_2/count_7_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C23[1][A] | clkdiv_2/count_7_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 7 | R15C23[1][A] | clkdiv_2/count_7_s0/Q |
1.916 | 0.006 | tNET | RR | 1 | R15C23[1][A] | clkdiv_2/n54_s7/I2 |
2.288 | 0.372 | tINS | RF | 1 | R15C23[1][A] | clkdiv_2/n54_s7/F |
2.288 | 0.000 | tNET | FF | 1 | R15C23[1][A] | clkdiv_2/count_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R15C23[1][A] | clkdiv_2/count_7_s0/CLK |
1.577 | 0.000 | tHld | 1 | R15C23[1][A] | clkdiv_2/count_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path20
Path Summary:
Slack | 0.711 |
Data Arrival Time | 2.288 |
Data Required Time | 1.577 |
From | clkdiv_1/count_4_s0 |
To | clkdiv_1/count_4_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/count_4_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 7 | R13C25[1][A] | clkdiv_1/count_4_s0/Q |
1.916 | 0.006 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/n57_s2/I0 |
2.288 | 0.372 | tINS | RF | 1 | R13C25[1][A] | clkdiv_1/n57_s2/F |
2.288 | 0.000 | tNET | FF | 1 | R13C25[1][A] | clkdiv_1/count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C25[1][A] | clkdiv_1/count_4_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C25[1][A] | clkdiv_1/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.372, 52.303%; route: 0.006, 0.830%; tC2Q: 0.333, 46.867% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path21
Path Summary:
Slack | 0.712 |
Data Arrival Time | 1.990 |
Data Required Time | 1.277 |
From | mux7seg_1/col_0_s0 |
To | mux7seg_1/col_0_s0 |
Launch Clk | clk160hz:[R] |
Latch Clk | clk160hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk160hz | ||||
0.000 | 0.000 | tCL | RR | 14 | R15C35[1][B] | clkdiv_5/clk_out_s0/Q |
1.277 | 1.277 | tNET | RR | 1 | R15C32[0][A] | mux7seg_1/col_0_s0/CLK |
1.611 | 0.333 | tC2Q | RR | 17 | R15C32[0][A] | mux7seg_1/col_0_s0/Q |
1.618 | 0.007 | tNET | RR | 1 | R15C32[0][A] | mux7seg_1/n12_s4/I0 |
1.990 | 0.372 | tINS | RF | 1 | R15C32[0][A] | mux7seg_1/n12_s4/F |
1.990 | 0.000 | tNET | FF | 1 | R15C32[0][A] | mux7seg_1/col_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk160hz | ||||
0.000 | 0.000 | tCL | RR | 14 | R15C35[1][B] | clkdiv_5/clk_out_s0/Q |
1.277 | 1.277 | tNET | RR | 1 | R15C32[0][A] | mux7seg_1/col_0_s0/CLK |
1.277 | 0.000 | tHld | 1 | R15C32[0][A] | mux7seg_1/col_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.277, 100.000% |
Arrival Data Path Delay | cell: 0.372, 52.217%; route: 0.007, 0.994%; tC2Q: 0.333, 46.789% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.277, 100.000% |
Path22
Path Summary:
Slack | 0.715 |
Data Arrival Time | 1.949 |
Data Required Time | 1.235 |
From | leg4_1/inst1/adr_0_s0 |
To | leg4_1/inst1/adr_0_s0 |
Launch Clk | leg4_clk:[R] |
Latch Clk | leg4_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | leg4_clk | ||||
0.000 | 0.000 | tCL | RR | 17 | R17C25[3][A] | leg4_clk_s5/O |
1.235 | 1.235 | tNET | RR | 1 | R17C33[0][A] | leg4_1/inst1/adr_0_s0/CLK |
1.568 | 0.333 | tC2Q | RR | 31 | R17C33[0][A] | leg4_1/inst1/adr_0_s0/Q |
1.577 | 0.009 | tNET | RR | 1 | R17C33[0][A] | leg4_1/inst1/n15_s1/I0 |
1.949 | 0.372 | tINS | RF | 1 | R17C33[0][A] | leg4_1/inst1/n15_s1/F |
1.949 | 0.000 | tNET | FF | 1 | R17C33[0][A] | leg4_1/inst1/adr_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | leg4_clk | ||||
0.000 | 0.000 | tCL | RR | 17 | R17C25[3][A] | leg4_clk_s5/O |
1.235 | 1.235 | tNET | RR | 1 | R17C33[0][A] | leg4_1/inst1/adr_0_s0/CLK |
1.235 | 0.000 | tHld | 1 | R17C33[0][A] | leg4_1/inst1/adr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.235, 100.000% |
Arrival Data Path Delay | cell: 0.372, 52.044%; route: 0.009, 1.321%; tC2Q: 0.333, 46.635% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.235, 100.000% |
Path23
Path Summary:
Slack | 0.892 |
Data Arrival Time | 2.468 |
Data Required Time | 1.577 |
From | clkdiv_4/count_1_s0 |
To | clkdiv_4/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C27[2][A] | clkdiv_4/count_1_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 4 | R13C27[2][A] | clkdiv_4/count_1_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R13C27[2][A] | clkdiv_4/n60_s2/I0 |
2.468 | 0.556 | tINS | RR | 1 | R13C27[2][A] | clkdiv_4/n60_s2/F |
2.468 | 0.000 | tNET | RR | 1 | R13C27[2][A] | clkdiv_4/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R13C27[2][A] | clkdiv_4/count_1_s0/CLK |
1.577 | 0.000 | tHld | 1 | R13C27[2][A] | clkdiv_4/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path24
Path Summary:
Slack | 0.892 |
Data Arrival Time | 2.468 |
Data Required Time | 1.577 |
From | clkdiv_3/count_15_s0 |
To | clkdiv_3/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C19[2][A] | clkdiv_3/count_15_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 3 | R14C19[2][A] | clkdiv_3/count_15_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R14C19[2][A] | clkdiv_3/n46_s2/I2 |
2.468 | 0.556 | tINS | RR | 1 | R14C19[2][A] | clkdiv_3/n46_s2/F |
2.468 | 0.000 | tNET | RR | 1 | R14C19[2][A] | clkdiv_3/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C19[2][A] | clkdiv_3/count_15_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C19[2][A] | clkdiv_3/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Path25
Path Summary:
Slack | 0.892 |
Data Arrival Time | 2.468 |
Data Required Time | 1.577 |
From | clkdiv_3/count_16_s0 |
To | clkdiv_3/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C20[2][A] | clkdiv_3/count_16_s0/CLK |
1.910 | 0.333 | tC2Q | RR | 2 | R14C20[2][A] | clkdiv_3/count_16_s0/Q |
1.912 | 0.002 | tNET | RR | 1 | R14C20[2][A] | clkdiv_3/n45_s2/I2 |
2.468 | 0.556 | tINS | RR | 1 | R14C20[2][A] | clkdiv_3/n45_s2/F |
2.468 | 0.000 | tNET | RR | 1 | R14C20[2][A] | clkdiv_3/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOR17[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 102 | IOR17[A] | clk_ibuf/O |
1.577 | 0.185 | tNET | RR | 1 | R14C20[2][A] | clkdiv_3/count_16_s0/CLK |
1.577 | 0.000 | tHld | 1 | R14C20[2][A] | clkdiv_3/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Arrival Data Path Delay | cell: 0.556, 62.353%; route: 0.002, 0.265%; tC2Q: 0.333, 37.382% |
Required Clock Path Delay | cell: 1.392, 88.292%; route: 0.185, 11.708% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_16_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_16_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_16_s0/CLK |
MPW2
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_14_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_14_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_14_s0/CLK |
MPW3
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_10_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_10_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_10_s0/CLK |
MPW4
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_1/count_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_1/count_2_s0/CLK |
MPW5
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_2/count_9_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_2/count_9_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_2/count_9_s0/CLK |
MPW6
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_3/count_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_3/count_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_3/count_3_s0/CLK |
MPW7
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_3/count_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_3/count_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_3/count_4_s0/CLK |
MPW8
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_2/count_10_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_2/count_10_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_2/count_10_s0/CLK |
MPW9
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_3/count_5_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_3/count_5_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_3/count_5_s0/CLK |
MPW10
MPW Summary:
Slack: | 16.269 |
Actual Width: | 17.519 |
Required Width: | 1.250 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_3/count_6_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.094 | 0.262 | tNET | FF | clkdiv_3/count_6_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.614 | 0.185 | tNET | RR | clkdiv_3/count_6_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
102 | clk_d | 28.187 | 0.262 |
31 | address[0] | 999985.812 | 2.151 |
29 | address[2] | 999985.000 | 1.830 |
27 | address[1] | 999985.438 | 2.007 |
25 | address[3] | 999986.312 | 1.654 |
25 | n61_7 | 28.187 | 1.357 |
19 | n61_7 | 32.768 | 0.867 |
19 | n61_8 | 29.717 | 1.223 |
19 | col[1] | 6249985.000 | 1.515 |
18 | n61_8 | 30.020 | 0.892 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R13C35 | 81.94% |
R13C27 | 79.17% |
R13C25 | 77.78% |
R16C32 | 75.00% |
R13C18 | 75.00% |
R13C19 | 70.83% |
R14C35 | 66.67% |
R15C20 | 62.50% |
R13C23 | 61.11% |
R13C26 | 61.11% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk1khz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 27000 [get_nets {clk1khz}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk400hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 67500 [get_nets {clk400hz}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk1hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 2700000 [get_nets {clk1hz}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk160hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 168750 [get_nets {clk160hz}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk10hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 2700000 [get_nets {clk10hz}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name leg4_clk -source [get_nets {clk1khz}] -master_clock clk1khz -divide_by 1 [get_nets {leg4_clk}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -exclusive -group [get_clocks {clk1khz}] -group [get_clocks {clk10hz}] -group [get_clocks {clk1hz}] |
TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk160hz}] -group [get_clocks {leg4_clk}] |