Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\SV_240812_mhut_2001\organ\src\clkdiv.sv
C:\Gowin\SV_240812_mhut_2001\organ\src\debounce.sv
C:\Gowin\SV_240812_mhut_2001\organ\src\dec16to4.sv
C:\Gowin\SV_240812_mhut_2001\organ\src\decdiv.sv
C:\Gowin\SV_240812_mhut_2001\organ\src\drv7seg.sv
C:\Gowin\SV_240812_mhut_2001\organ\src\matrix_key.sv
C:\Gowin\SV_240812_mhut_2001\organ\src\mux7seg.sv
C:\Gowin\SV_240812_mhut_2001\organ\src\organ.sv
C:\Gowin\SV_240812_mhut_2001\organ\src\toggle.sv
GowinSynthesis Constraints File ---
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Aug 12 11:43:03 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module organ
Synthesis Process Running parser:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.068s, Peak memory usage = 132.402MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 132.402MB
    Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 132.402MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 132.402MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 132.402MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 132.402MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 132.402MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 132.402MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 132.402MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 132.402MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 132.402MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.509s, Peak memory usage = 160.457MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.042s, Peak memory usage = 160.457MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 160.457MB
Total Time and Memory Usage CPU time = 0h 0m 0.621s, Elapsed time = 0h 0m 0.668s, Peak memory usage = 160.457MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 24
I/O Buf 24
    IBUF 6
    OBUF 18
Register 80
    DFFE 5
    DFFPE 16
    DFFC 43
    DFFCE 16
LUT 148
    LUT2 26
    LUT3 33
    LUT4 89
ALU 32
    ALU 32
INV 18
    INV 18

Resource Utilization Summary

Resource Usage Utilization
Logic 198(166 LUT, 32 ALU) / 8640 3%
Register 80 / 6693 2%
  --Register as Latch 0 / 6693 0%
  --Register as FF 80 / 6693 2%
BSRAM 0 / 26 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
2 clkdiv_1/clk50hz Base 20.000 50.0 0.000 10.000 clkdiv_1/clk_out_s0/Q

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 99.460(MHz) 5 TOP
2 clkdiv_1/clk50hz 50.000(MHz) 257.909(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -0.086
Data Arrival Time 20.382
Data Required Time 20.296
From inst2/key_13_s0
To inst5/count_0_s0
Launch Clk clkdiv_1/clk50hz[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clkdiv_1/clk50hz
0.000 0.000 tCL RR 40 clkdiv_1/clk_out_s0/Q
0.726 0.726 tNET RR 1 inst2/key_13_s0/CLK
1.184 0.458 tC2Q RF 3 inst2/key_13_s0/Q
2.144 0.960 tNET FF 1 inst3/sw_3_s3/I1
3.243 1.099 tINS FF 5 inst3/sw_3_s3/F
4.203 0.960 tNET FF 1 inst3/sw_3_s0/I1
5.302 1.099 tINS FF 2 inst3/sw_3_s0/F
6.262 0.960 tNET FF 1 inst3/seg_d_0_s/I1
7.361 1.099 tINS FF 4 inst3/seg_d_0_s/F
8.321 0.960 tNET FF 1 inst3/sw_0_s1/I3
8.947 0.626 tINS FF 1 inst3/sw_0_s1/F
9.907 0.960 tNET FF 1 inst3/sw_0_s/I2
10.729 0.822 tINS FF 23 inst3/sw_0_s/F
11.689 0.960 tNET FF 1 inst4/count_0_s16/I0
12.721 1.032 tINS FF 1 inst4/count_0_s16/F
13.681 0.960 tNET FF 2 inst5/n7_s61/I1
14.726 1.045 tINS FF 1 inst5/n7_s61/COUT
14.726 0.000 tNET FF 2 inst5/n7_s62/CIN
14.783 0.057 tINS FF 1 inst5/n7_s62/COUT
14.783 0.000 tNET FF 2 inst5/n7_s63/CIN
14.840 0.057 tINS FF 1 inst5/n7_s63/COUT
14.840 0.000 tNET FF 2 inst5/n7_s64/CIN
14.897 0.057 tINS FF 1 inst5/n7_s64/COUT
14.897 0.000 tNET FF 2 inst5/n7_s65/CIN
14.954 0.057 tINS FF 1 inst5/n7_s65/COUT
14.954 0.000 tNET FF 2 inst5/n7_s66/CIN
15.011 0.057 tINS FF 1 inst5/n7_s66/COUT
15.011 0.000 tNET FF 2 inst5/n7_s67/CIN
15.068 0.057 tINS FF 1 inst5/n7_s67/COUT
15.068 0.000 tNET FF 2 inst5/n7_s68/CIN
15.125 0.057 tINS FF 1 inst5/n7_s68/COUT
15.125 0.000 tNET FF 2 inst5/n7_s69/CIN
15.182 0.057 tINS FF 1 inst5/n7_s69/COUT
15.182 0.000 tNET FF 2 inst5/n7_s70/CIN
15.239 0.057 tINS FF 1 inst5/n7_s70/COUT
15.239 0.000 tNET FF 2 inst5/n7_s71/CIN
15.296 0.057 tINS FF 1 inst5/n7_s71/COUT
15.296 0.000 tNET FF 2 inst5/n7_s72/CIN
15.353 0.057 tINS FF 1 inst5/n7_s72/COUT
15.353 0.000 tNET FF 2 inst5/n7_s73/CIN
15.410 0.057 tINS FF 1 inst5/n7_s73/COUT
15.410 0.000 tNET FF 2 inst5/n7_s74/CIN
15.467 0.057 tINS FF 1 inst5/n7_s74/COUT
15.467 0.000 tNET FF 2 inst5/n7_s75/CIN
15.524 0.057 tINS FF 1 inst5/n7_s75/COUT
15.524 0.000 tNET FF 2 inst5/n7_s76/CIN
15.581 0.057 tINS FF 1 inst5/n7_s76/COUT
16.541 0.960 tNET FF 1 inst5/n61_s6/I2
17.363 0.822 tINS FF 18 inst5/n61_s6/F
18.323 0.960 tNET FF 1 inst5/n61_s2/I1
19.422 1.099 tINS FF 1 inst5/n61_s2/F
20.382 0.960 tNET FF 1 inst5/count_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 40 clk_ibuf/O
20.726 0.726 tNET RR 1 inst5/count_0_s0/CLK
20.696 -0.030 tUnc inst5/count_0_s0
20.296 -0.400 tSu 1 inst5/count_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 9.598, 48.829%; route: 9.600, 48.839%; tC2Q: 0.458, 2.332%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:
Slack -0.086
Data Arrival Time 20.382
Data Required Time 20.296
From inst2/key_13_s0
To inst5/count_17_s0
Launch Clk clkdiv_1/clk50hz[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clkdiv_1/clk50hz
0.000 0.000 tCL RR 40 clkdiv_1/clk_out_s0/Q
0.726 0.726 tNET RR 1 inst2/key_13_s0/CLK
1.184 0.458 tC2Q RF 3 inst2/key_13_s0/Q
2.144 0.960 tNET FF 1 inst3/sw_3_s3/I1
3.243 1.099 tINS FF 5 inst3/sw_3_s3/F
4.203 0.960 tNET FF 1 inst3/sw_3_s0/I1
5.302 1.099 tINS FF 2 inst3/sw_3_s0/F
6.262 0.960 tNET FF 1 inst3/seg_d_0_s/I1
7.361 1.099 tINS FF 4 inst3/seg_d_0_s/F
8.321 0.960 tNET FF 1 inst3/sw_0_s1/I3
8.947 0.626 tINS FF 1 inst3/sw_0_s1/F
9.907 0.960 tNET FF 1 inst3/sw_0_s/I2
10.729 0.822 tINS FF 23 inst3/sw_0_s/F
11.689 0.960 tNET FF 1 inst4/count_0_s16/I0
12.721 1.032 tINS FF 1 inst4/count_0_s16/F
13.681 0.960 tNET FF 2 inst5/n7_s61/I1
14.726 1.045 tINS FF 1 inst5/n7_s61/COUT
14.726 0.000 tNET FF 2 inst5/n7_s62/CIN
14.783 0.057 tINS FF 1 inst5/n7_s62/COUT
14.783 0.000 tNET FF 2 inst5/n7_s63/CIN
14.840 0.057 tINS FF 1 inst5/n7_s63/COUT
14.840 0.000 tNET FF 2 inst5/n7_s64/CIN
14.897 0.057 tINS FF 1 inst5/n7_s64/COUT
14.897 0.000 tNET FF 2 inst5/n7_s65/CIN
14.954 0.057 tINS FF 1 inst5/n7_s65/COUT
14.954 0.000 tNET FF 2 inst5/n7_s66/CIN
15.011 0.057 tINS FF 1 inst5/n7_s66/COUT
15.011 0.000 tNET FF 2 inst5/n7_s67/CIN
15.068 0.057 tINS FF 1 inst5/n7_s67/COUT
15.068 0.000 tNET FF 2 inst5/n7_s68/CIN
15.125 0.057 tINS FF 1 inst5/n7_s68/COUT
15.125 0.000 tNET FF 2 inst5/n7_s69/CIN
15.182 0.057 tINS FF 1 inst5/n7_s69/COUT
15.182 0.000 tNET FF 2 inst5/n7_s70/CIN
15.239 0.057 tINS FF 1 inst5/n7_s70/COUT
15.239 0.000 tNET FF 2 inst5/n7_s71/CIN
15.296 0.057 tINS FF 1 inst5/n7_s71/COUT
15.296 0.000 tNET FF 2 inst5/n7_s72/CIN
15.353 0.057 tINS FF 1 inst5/n7_s72/COUT
15.353 0.000 tNET FF 2 inst5/n7_s73/CIN
15.410 0.057 tINS FF 1 inst5/n7_s73/COUT
15.410 0.000 tNET FF 2 inst5/n7_s74/CIN
15.467 0.057 tINS FF 1 inst5/n7_s74/COUT
15.467 0.000 tNET FF 2 inst5/n7_s75/CIN
15.524 0.057 tINS FF 1 inst5/n7_s75/COUT
15.524 0.000 tNET FF 2 inst5/n7_s76/CIN
15.581 0.057 tINS FF 1 inst5/n7_s76/COUT
16.541 0.960 tNET FF 1 inst5/n61_s6/I2
17.363 0.822 tINS FF 18 inst5/n61_s6/F
18.323 0.960 tNET FF 1 inst5/n44_s2/I1
19.422 1.099 tINS FF 1 inst5/n44_s2/F
20.382 0.960 tNET FF 1 inst5/count_17_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 40 clk_ibuf/O
20.726 0.726 tNET RR 1 inst5/count_17_s0/CLK
20.696 -0.030 tUnc inst5/count_17_s0
20.296 -0.400 tSu 1 inst5/count_17_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 9.598, 48.829%; route: 9.600, 48.839%; tC2Q: 0.458, 2.332%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:
Slack 0.191
Data Arrival Time 20.105
Data Required Time 20.296
From inst2/key_13_s0
To inst5/count_1_s0
Launch Clk clkdiv_1/clk50hz[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clkdiv_1/clk50hz
0.000 0.000 tCL RR 40 clkdiv_1/clk_out_s0/Q
0.726 0.726 tNET RR 1 inst2/key_13_s0/CLK
1.184 0.458 tC2Q RF 3 inst2/key_13_s0/Q
2.144 0.960 tNET FF 1 inst3/sw_3_s3/I1
3.243 1.099 tINS FF 5 inst3/sw_3_s3/F
4.203 0.960 tNET FF 1 inst3/sw_3_s0/I1
5.302 1.099 tINS FF 2 inst3/sw_3_s0/F
6.262 0.960 tNET FF 1 inst3/seg_d_0_s/I1
7.361 1.099 tINS FF 4 inst3/seg_d_0_s/F
8.321 0.960 tNET FF 1 inst3/sw_0_s1/I3
8.947 0.626 tINS FF 1 inst3/sw_0_s1/F
9.907 0.960 tNET FF 1 inst3/sw_0_s/I2
10.729 0.822 tINS FF 23 inst3/sw_0_s/F
11.689 0.960 tNET FF 1 inst4/count_0_s16/I0
12.721 1.032 tINS FF 1 inst4/count_0_s16/F
13.681 0.960 tNET FF 2 inst5/n7_s61/I1
14.726 1.045 tINS FF 1 inst5/n7_s61/COUT
14.726 0.000 tNET FF 2 inst5/n7_s62/CIN
14.783 0.057 tINS FF 1 inst5/n7_s62/COUT
14.783 0.000 tNET FF 2 inst5/n7_s63/CIN
14.840 0.057 tINS FF 1 inst5/n7_s63/COUT
14.840 0.000 tNET FF 2 inst5/n7_s64/CIN
14.897 0.057 tINS FF 1 inst5/n7_s64/COUT
14.897 0.000 tNET FF 2 inst5/n7_s65/CIN
14.954 0.057 tINS FF 1 inst5/n7_s65/COUT
14.954 0.000 tNET FF 2 inst5/n7_s66/CIN
15.011 0.057 tINS FF 1 inst5/n7_s66/COUT
15.011 0.000 tNET FF 2 inst5/n7_s67/CIN
15.068 0.057 tINS FF 1 inst5/n7_s67/COUT
15.068 0.000 tNET FF 2 inst5/n7_s68/CIN
15.125 0.057 tINS FF 1 inst5/n7_s68/COUT
15.125 0.000 tNET FF 2 inst5/n7_s69/CIN
15.182 0.057 tINS FF 1 inst5/n7_s69/COUT
15.182 0.000 tNET FF 2 inst5/n7_s70/CIN
15.239 0.057 tINS FF 1 inst5/n7_s70/COUT
15.239 0.000 tNET FF 2 inst5/n7_s71/CIN
15.296 0.057 tINS FF 1 inst5/n7_s71/COUT
15.296 0.000 tNET FF 2 inst5/n7_s72/CIN
15.353 0.057 tINS FF 1 inst5/n7_s72/COUT
15.353 0.000 tNET FF 2 inst5/n7_s73/CIN
15.410 0.057 tINS FF 1 inst5/n7_s73/COUT
15.410 0.000 tNET FF 2 inst5/n7_s74/CIN
15.467 0.057 tINS FF 1 inst5/n7_s74/COUT
15.467 0.000 tNET FF 2 inst5/n7_s75/CIN
15.524 0.057 tINS FF 1 inst5/n7_s75/COUT
15.524 0.000 tNET FF 2 inst5/n7_s76/CIN
15.581 0.057 tINS FF 1 inst5/n7_s76/COUT
16.541 0.960 tNET FF 1 inst5/n61_s6/I2
17.363 0.822 tINS FF 18 inst5/n61_s6/F
18.323 0.960 tNET FF 1 inst5/n60_s2/I2
19.145 0.822 tINS FF 1 inst5/n60_s2/F
20.105 0.960 tNET FF 1 inst5/count_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 40 clk_ibuf/O
20.726 0.726 tNET RR 1 inst5/count_1_s0/CLK
20.696 -0.030 tUnc inst5/count_1_s0
20.296 -0.400 tSu 1 inst5/count_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 9.321, 48.098%; route: 9.600, 49.537%; tC2Q: 0.458, 2.365%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:
Slack 0.191
Data Arrival Time 20.105
Data Required Time 20.296
From inst2/key_13_s0
To inst5/count_3_s0
Launch Clk clkdiv_1/clk50hz[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clkdiv_1/clk50hz
0.000 0.000 tCL RR 40 clkdiv_1/clk_out_s0/Q
0.726 0.726 tNET RR 1 inst2/key_13_s0/CLK
1.184 0.458 tC2Q RF 3 inst2/key_13_s0/Q
2.144 0.960 tNET FF 1 inst3/sw_3_s3/I1
3.243 1.099 tINS FF 5 inst3/sw_3_s3/F
4.203 0.960 tNET FF 1 inst3/sw_3_s0/I1
5.302 1.099 tINS FF 2 inst3/sw_3_s0/F
6.262 0.960 tNET FF 1 inst3/seg_d_0_s/I1
7.361 1.099 tINS FF 4 inst3/seg_d_0_s/F
8.321 0.960 tNET FF 1 inst3/sw_0_s1/I3
8.947 0.626 tINS FF 1 inst3/sw_0_s1/F
9.907 0.960 tNET FF 1 inst3/sw_0_s/I2
10.729 0.822 tINS FF 23 inst3/sw_0_s/F
11.689 0.960 tNET FF 1 inst4/count_0_s16/I0
12.721 1.032 tINS FF 1 inst4/count_0_s16/F
13.681 0.960 tNET FF 2 inst5/n7_s61/I1
14.726 1.045 tINS FF 1 inst5/n7_s61/COUT
14.726 0.000 tNET FF 2 inst5/n7_s62/CIN
14.783 0.057 tINS FF 1 inst5/n7_s62/COUT
14.783 0.000 tNET FF 2 inst5/n7_s63/CIN
14.840 0.057 tINS FF 1 inst5/n7_s63/COUT
14.840 0.000 tNET FF 2 inst5/n7_s64/CIN
14.897 0.057 tINS FF 1 inst5/n7_s64/COUT
14.897 0.000 tNET FF 2 inst5/n7_s65/CIN
14.954 0.057 tINS FF 1 inst5/n7_s65/COUT
14.954 0.000 tNET FF 2 inst5/n7_s66/CIN
15.011 0.057 tINS FF 1 inst5/n7_s66/COUT
15.011 0.000 tNET FF 2 inst5/n7_s67/CIN
15.068 0.057 tINS FF 1 inst5/n7_s67/COUT
15.068 0.000 tNET FF 2 inst5/n7_s68/CIN
15.125 0.057 tINS FF 1 inst5/n7_s68/COUT
15.125 0.000 tNET FF 2 inst5/n7_s69/CIN
15.182 0.057 tINS FF 1 inst5/n7_s69/COUT
15.182 0.000 tNET FF 2 inst5/n7_s70/CIN
15.239 0.057 tINS FF 1 inst5/n7_s70/COUT
15.239 0.000 tNET FF 2 inst5/n7_s71/CIN
15.296 0.057 tINS FF 1 inst5/n7_s71/COUT
15.296 0.000 tNET FF 2 inst5/n7_s72/CIN
15.353 0.057 tINS FF 1 inst5/n7_s72/COUT
15.353 0.000 tNET FF 2 inst5/n7_s73/CIN
15.410 0.057 tINS FF 1 inst5/n7_s73/COUT
15.410 0.000 tNET FF 2 inst5/n7_s74/CIN
15.467 0.057 tINS FF 1 inst5/n7_s74/COUT
15.467 0.000 tNET FF 2 inst5/n7_s75/CIN
15.524 0.057 tINS FF 1 inst5/n7_s75/COUT
15.524 0.000 tNET FF 2 inst5/n7_s76/CIN
15.581 0.057 tINS FF 1 inst5/n7_s76/COUT
16.541 0.960 tNET FF 1 inst5/n61_s6/I2
17.363 0.822 tINS FF 18 inst5/n61_s6/F
18.323 0.960 tNET FF 1 inst5/n58_s2/I2
19.145 0.822 tINS FF 1 inst5/n58_s2/F
20.105 0.960 tNET FF 1 inst5/count_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 40 clk_ibuf/O
20.726 0.726 tNET RR 1 inst5/count_3_s0/CLK
20.696 -0.030 tUnc inst5/count_3_s0
20.296 -0.400 tSu 1 inst5/count_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 9.321, 48.098%; route: 9.600, 49.537%; tC2Q: 0.458, 2.365%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:
Slack 0.191
Data Arrival Time 20.105
Data Required Time 20.296
From inst2/key_13_s0
To inst5/count_4_s0
Launch Clk clkdiv_1/clk50hz[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clkdiv_1/clk50hz
0.000 0.000 tCL RR 40 clkdiv_1/clk_out_s0/Q
0.726 0.726 tNET RR 1 inst2/key_13_s0/CLK
1.184 0.458 tC2Q RF 3 inst2/key_13_s0/Q
2.144 0.960 tNET FF 1 inst3/sw_3_s3/I1
3.243 1.099 tINS FF 5 inst3/sw_3_s3/F
4.203 0.960 tNET FF 1 inst3/sw_3_s0/I1
5.302 1.099 tINS FF 2 inst3/sw_3_s0/F
6.262 0.960 tNET FF 1 inst3/seg_d_0_s/I1
7.361 1.099 tINS FF 4 inst3/seg_d_0_s/F
8.321 0.960 tNET FF 1 inst3/sw_0_s1/I3
8.947 0.626 tINS FF 1 inst3/sw_0_s1/F
9.907 0.960 tNET FF 1 inst3/sw_0_s/I2
10.729 0.822 tINS FF 23 inst3/sw_0_s/F
11.689 0.960 tNET FF 1 inst4/count_0_s16/I0
12.721 1.032 tINS FF 1 inst4/count_0_s16/F
13.681 0.960 tNET FF 2 inst5/n7_s61/I1
14.726 1.045 tINS FF 1 inst5/n7_s61/COUT
14.726 0.000 tNET FF 2 inst5/n7_s62/CIN
14.783 0.057 tINS FF 1 inst5/n7_s62/COUT
14.783 0.000 tNET FF 2 inst5/n7_s63/CIN
14.840 0.057 tINS FF 1 inst5/n7_s63/COUT
14.840 0.000 tNET FF 2 inst5/n7_s64/CIN
14.897 0.057 tINS FF 1 inst5/n7_s64/COUT
14.897 0.000 tNET FF 2 inst5/n7_s65/CIN
14.954 0.057 tINS FF 1 inst5/n7_s65/COUT
14.954 0.000 tNET FF 2 inst5/n7_s66/CIN
15.011 0.057 tINS FF 1 inst5/n7_s66/COUT
15.011 0.000 tNET FF 2 inst5/n7_s67/CIN
15.068 0.057 tINS FF 1 inst5/n7_s67/COUT
15.068 0.000 tNET FF 2 inst5/n7_s68/CIN
15.125 0.057 tINS FF 1 inst5/n7_s68/COUT
15.125 0.000 tNET FF 2 inst5/n7_s69/CIN
15.182 0.057 tINS FF 1 inst5/n7_s69/COUT
15.182 0.000 tNET FF 2 inst5/n7_s70/CIN
15.239 0.057 tINS FF 1 inst5/n7_s70/COUT
15.239 0.000 tNET FF 2 inst5/n7_s71/CIN
15.296 0.057 tINS FF 1 inst5/n7_s71/COUT
15.296 0.000 tNET FF 2 inst5/n7_s72/CIN
15.353 0.057 tINS FF 1 inst5/n7_s72/COUT
15.353 0.000 tNET FF 2 inst5/n7_s73/CIN
15.410 0.057 tINS FF 1 inst5/n7_s73/COUT
15.410 0.000 tNET FF 2 inst5/n7_s74/CIN
15.467 0.057 tINS FF 1 inst5/n7_s74/COUT
15.467 0.000 tNET FF 2 inst5/n7_s75/CIN
15.524 0.057 tINS FF 1 inst5/n7_s75/COUT
15.524 0.000 tNET FF 2 inst5/n7_s76/CIN
15.581 0.057 tINS FF 1 inst5/n7_s76/COUT
16.541 0.960 tNET FF 1 inst5/n61_s6/I2
17.363 0.822 tINS FF 18 inst5/n61_s6/F
18.323 0.960 tNET FF 1 inst5/n57_s2/I2
19.145 0.822 tINS FF 1 inst5/n57_s2/F
20.105 0.960 tNET FF 1 inst5/count_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 40 clk_ibuf/O
20.726 0.726 tNET RR 1 inst5/count_4_s0/CLK
20.696 -0.030 tUnc inst5/count_4_s0
20.296 -0.400 tSu 1 inst5/count_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 12
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 9.321, 48.098%; route: 9.600, 49.537%; tC2Q: 0.458, 2.365%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%