Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\SV_240812_mhut_2001\matrix_key\src\clkdiv.sv
C:\Gowin\SV_240812_mhut_2001\matrix_key\src\dec16to4.sv
C:\Gowin\SV_240812_mhut_2001\matrix_key\src\drv7seg.sv
C:\Gowin\SV_240812_mhut_2001\matrix_key\src\matrix_key.sv
C:\Gowin\SV_240812_mhut_2001\matrix_key\src\mux7seg.sv
C:\Gowin\SV_240812_mhut_2001\matrix_key\src\test_matrix_key.sv
GowinSynthesis Constraints File ---
Tool Version V1.9.10.01 (64-bit)
Part Number GW1NR-LV9QN88PC6/I5
Device GW1NR-9
Device Version C
Created Time Mon Aug 12 11:40:11 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module test_matrix_key
Synthesis Process Running parser:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.066s, Peak memory usage = 132.527MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 132.527MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 132.527MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 132.527MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 132.527MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 132.527MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 132.527MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 132.527MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 132.527MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 132.527MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 132.527MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.39s, Elapsed time = 0h 0m 0.409s, Peak memory usage = 161.074MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.026s, Peak memory usage = 161.074MB
Generate output files:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 161.074MB
Total Time and Memory Usage CPU time = 0h 0m 0.513s, Elapsed time = 0h 0m 0.53s, Peak memory usage = 161.074MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 23
I/O Buf 23
    IBUF 6
    OBUF 17
Register 61
    DFFE 5
    DFFPE 16
    DFFC 24
    DFFCE 16
LUT 107
    LUT2 14
    LUT3 24
    LUT4 69
INV 18
    INV 18

Resource Utilization Summary

Resource Usage Utilization
Logic 125(125 LUT, 0 ALU) / 8640 2%
Register 61 / 6693 <1%
  --Register as Latch 0 / 6693 0%
  --Register as FF 61 / 6693 <1%
BSRAM 0 / 26 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
2 clkdiv_1/clk50hz Base 20.000 50.0 0.000 10.000 clkdiv_1/clk_out_s0/Q

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 99.460(MHz) 5 TOP
2 clkdiv_1/clk50hz 50.000(MHz) 257.909(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 9.946
Data Arrival Time 10.380
Data Required Time 20.326
From clkdiv_1/count_0_s0
To clkdiv_1/count_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 21 clk_ibuf/O
0.726 0.726 tNET RR 1 clkdiv_1/count_0_s0/CLK
1.184 0.458 tC2Q RF 5 clkdiv_1/count_0_s0/Q
2.144 0.960 tNET FF 1 clkdiv_1/n57_s3/I1
3.243 1.099 tINS FF 9 clkdiv_1/n57_s3/F
4.203 0.960 tNET FF 1 clkdiv_1/n61_s5/I1
5.302 1.099 tINS FF 1 clkdiv_1/n61_s5/F
6.262 0.960 tNET FF 1 clkdiv_1/n61_s10/I1
7.361 1.099 tINS FF 15 clkdiv_1/n61_s10/F
8.321 0.960 tNET FF 1 clkdiv_1/n60_s3/I1
9.420 1.099 tINS FF 1 clkdiv_1/n60_s3/F
10.380 0.960 tNET FF 1 clkdiv_1/count_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 21 clk_ibuf/O
20.726 0.726 tNET RR 1 clkdiv_1/count_1_s0/CLK
20.326 -0.400 tSu 1 clkdiv_1/count_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 2

Path Summary:
Slack 9.946
Data Arrival Time 10.380
Data Required Time 20.326
From clkdiv_1/count_0_s0
To clkdiv_1/count_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 21 clk_ibuf/O
0.726 0.726 tNET RR 1 clkdiv_1/count_0_s0/CLK
1.184 0.458 tC2Q RF 5 clkdiv_1/count_0_s0/Q
2.144 0.960 tNET FF 1 clkdiv_1/n57_s3/I1
3.243 1.099 tINS FF 9 clkdiv_1/n57_s3/F
4.203 0.960 tNET FF 1 clkdiv_1/n61_s5/I1
5.302 1.099 tINS FF 1 clkdiv_1/n61_s5/F
6.262 0.960 tNET FF 1 clkdiv_1/n61_s10/I1
7.361 1.099 tINS FF 15 clkdiv_1/n61_s10/F
8.321 0.960 tNET FF 1 clkdiv_1/n59_s4/I1
9.420 1.099 tINS FF 1 clkdiv_1/n59_s4/F
10.380 0.960 tNET FF 1 clkdiv_1/count_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 21 clk_ibuf/O
20.726 0.726 tNET RR 1 clkdiv_1/count_2_s0/CLK
20.326 -0.400 tSu 1 clkdiv_1/count_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 3

Path Summary:
Slack 9.946
Data Arrival Time 10.380
Data Required Time 20.326
From clkdiv_1/count_0_s0
To clkdiv_1/count_3_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 21 clk_ibuf/O
0.726 0.726 tNET RR 1 clkdiv_1/count_0_s0/CLK
1.184 0.458 tC2Q RF 5 clkdiv_1/count_0_s0/Q
2.144 0.960 tNET FF 1 clkdiv_1/n57_s3/I1
3.243 1.099 tINS FF 9 clkdiv_1/n57_s3/F
4.203 0.960 tNET FF 1 clkdiv_1/n61_s5/I1
5.302 1.099 tINS FF 1 clkdiv_1/n61_s5/F
6.262 0.960 tNET FF 1 clkdiv_1/n61_s10/I1
7.361 1.099 tINS FF 15 clkdiv_1/n61_s10/F
8.321 0.960 tNET FF 1 clkdiv_1/n58_s4/I1
9.420 1.099 tINS FF 1 clkdiv_1/n58_s4/F
10.380 0.960 tNET FF 1 clkdiv_1/count_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 21 clk_ibuf/O
20.726 0.726 tNET RR 1 clkdiv_1/count_3_s0/CLK
20.326 -0.400 tSu 1 clkdiv_1/count_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 4

Path Summary:
Slack 9.946
Data Arrival Time 10.380
Data Required Time 20.326
From clkdiv_1/count_0_s0
To clkdiv_1/count_4_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 21 clk_ibuf/O
0.726 0.726 tNET RR 1 clkdiv_1/count_0_s0/CLK
1.184 0.458 tC2Q RF 5 clkdiv_1/count_0_s0/Q
2.144 0.960 tNET FF 1 clkdiv_1/n57_s3/I1
3.243 1.099 tINS FF 9 clkdiv_1/n57_s3/F
4.203 0.960 tNET FF 1 clkdiv_1/n61_s5/I1
5.302 1.099 tINS FF 1 clkdiv_1/n61_s5/F
6.262 0.960 tNET FF 1 clkdiv_1/n61_s10/I1
7.361 1.099 tINS FF 15 clkdiv_1/n61_s10/F
8.321 0.960 tNET FF 1 clkdiv_1/n57_s4/I1
9.420 1.099 tINS FF 1 clkdiv_1/n57_s4/F
10.380 0.960 tNET FF 1 clkdiv_1/count_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 21 clk_ibuf/O
20.726 0.726 tNET RR 1 clkdiv_1/count_4_s0/CLK
20.326 -0.400 tSu 1 clkdiv_1/count_4_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%

Path 5

Path Summary:
Slack 9.946
Data Arrival Time 10.380
Data Required Time 20.326
From clkdiv_1/count_0_s0
To clkdiv_1/count_5_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 21 clk_ibuf/O
0.726 0.726 tNET RR 1 clkdiv_1/count_0_s0/CLK
1.184 0.458 tC2Q RF 5 clkdiv_1/count_0_s0/Q
2.144 0.960 tNET FF 1 clkdiv_1/n57_s3/I1
3.243 1.099 tINS FF 9 clkdiv_1/n57_s3/F
4.203 0.960 tNET FF 1 clkdiv_1/n61_s5/I1
5.302 1.099 tINS FF 1 clkdiv_1/n61_s5/F
6.262 0.960 tNET FF 1 clkdiv_1/n61_s10/I1
7.361 1.099 tINS FF 15 clkdiv_1/n61_s10/F
8.321 0.960 tNET FF 1 clkdiv_1/n56_s4/I1
9.420 1.099 tINS FF 1 clkdiv_1/n56_s4/F
10.380 0.960 tNET FF 1 clkdiv_1/count_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 21 clk_ibuf/O
20.726 0.726 tNET RR 1 clkdiv_1/count_5_s0/CLK
20.326 -0.400 tSu 1 clkdiv_1/count_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%
Arrival Data Path Delay: cell: 4.396, 45.534%; route: 4.800, 49.719%; tC2Q: 0.458, 4.747%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.726, 100.000%