Synthesis Messages

Report Title GowinSynthesis Report
Design File H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\cmos_8_16bit.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\ddr3_memory_interface\DDR3MI.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\dvi_tx\DVI_TX_Top.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\fifo_hs\video_fifo.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\gowin_rpll\cmos_pll.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\gowin_rpll\mem_pll.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\gowin_rpll\sys_pll.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\gowin_rpll\TMDS_rPLL.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\i2c_master\i2c_config.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\i2c_master\i2c_master_bit_ctrl.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\i2c_master\i2c_master_byte_ctrl.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\i2c_master\i2c_master_defines.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\i2c_master\i2c_master_top.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\i2c_master\timescale.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\lut_ov5640_rgb565_480_272.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\MnistLutSimple.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\top.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\vga_timing.v
H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\video_frame_buffer\Video_Frame_Buffer_Top.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Tue Nov 19 02:10:18 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s, Peak memory usage = 226.875MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.48s, Peak memory usage = 226.875MB
    Optimizing Phase 1: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.601s, Peak memory usage = 226.875MB
    Optimizing Phase 2: CPU time = 0h 0m 0.75s, Elapsed time = 0h 0m 0.758s, Peak memory usage = 226.875MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 226.875MB
    Inferring Phase 1: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 226.875MB
    Inferring Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 226.875MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 226.875MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 0.995s, Peak memory usage = 226.875MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.311s, Peak memory usage = 226.875MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.144s, Peak memory usage = 226.875MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 20s, Elapsed time = 0h 0m 20s, Peak memory usage = 226.875MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.484s, Elapsed time = 0h 0m 0.483s, Peak memory usage = 226.875MB
Generate output files:
    CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 226.875MB
Total Time and Memory Usage CPU time = 0h 0m 28s, Elapsed time = 0h 0m 28s, Peak memory usage = 226.875MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 78
I/O Buf 71
    IBUF 13
    OBUF 30
    TBUF 3
    IOBUF 18
    TLVDS_OBUF 4
    ELVDS_OBUF 1
    ELVDS_IOBUF 2
Register 3660
    DFF 192
    DFFE 1574
    DFFS 17
    DFFSE 12
    DFFR 68
    DFFRE 58
    DFFP 79
    DFFPE 5
    DFFC 1132
    DFFCE 515
    DFFNP 8
LUT 4665
    LUT2 698
    LUT3 1465
    LUT4 2502
ALU 274
    ALU 274
SSRAM 117
    RAM16S4 46
    RAM16SDP4 71
INV 40
    INV 40
IOLOGIC 104
    IDES8_MEM 16
    OSER8 24
    OSER8_MEM 20
    OSER10 4
    IODELAY 40
BSRAM 16
    SDPB 1
    SDPX9B 15
CLOCK 8
    CLKDIV 2
    DQS 2
    DHCEN 1
    rPLL 3

Resource Utilization Summary

Resource Usage Utilization
Logic 5681(4705 LUT, 274 ALU, 117 RAM16) / 20736 28%
Register 3660 / 16173 23%
  --Register as Latch 0 / 16173 0%
  --Register as FF 3660 / 16173 23%
BSRAM 16 / 46 35%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clk Base 37.037 27.0 0.000 18.519 clk_ibuf/I
cmos_pclk Base 10.000 100.0 0.000 5.000 cmos_pclk_ibuf/I
cmos_8_16bit_m0/cmos_16bit_clk Base 10.000 100.0 0.000 5.000 cmos_8_16bit_m0/de_o_s0/Q
DVI_TX_Top/Pout_vs_dn[4] Base 10.000 100.0 0.000 5.000 Pout_vs_dn_4_s0/Q
cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk Generated 41.667 24.0 0.000 20.833 clk_ibuf/I clk cmos_pll_m0/rpll_inst/CLKOUT
cmos_pll_m0/rpll_inst/CLKOUTP.default_gen_clk Generated 41.667 24.0 0.000 20.833 clk_ibuf/I clk cmos_pll_m0/rpll_inst/CLKOUTP
cmos_pll_m0/rpll_inst/CLKOUTD.default_gen_clk Generated 83.333 12.0 0.000 41.667 clk_ibuf/I clk cmos_pll_m0/rpll_inst/CLKOUTD
cmos_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk Generated 125.000 8.0 0.000 62.500 clk_ibuf/I clk cmos_pll_m0/rpll_inst/CLKOUTD3
mem_pll_m0/rpll_inst/CLKOUT.default_gen_clk Generated 2.511 398.2 0.000 1.255 clk_ibuf/I clk mem_pll_m0/rpll_inst/CLKOUT
mem_pll_m0/rpll_inst/CLKOUTP.default_gen_clk Generated 2.511 398.2 0.000 1.255 clk_ibuf/I clk mem_pll_m0/rpll_inst/CLKOUTP
mem_pll_m0/rpll_inst/CLKOUTD.default_gen_clk Generated 5.022 199.1 0.000 2.511 clk_ibuf/I clk mem_pll_m0/rpll_inst/CLKOUTD
mem_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk Generated 7.533 132.8 0.000 3.766 clk_ibuf/I clk mem_pll_m0/rpll_inst/CLKOUTD3
u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk Generated 3.086 324.0 0.000 1.543 clk_ibuf/I clk u_tmds_rpll/rpll_inst/CLKOUT
u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk Generated 3.086 324.0 0.000 1.543 clk_ibuf/I clk u_tmds_rpll/rpll_inst/CLKOUTP
u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk Generated 6.173 162.0 0.000 3.086 clk_ibuf/I clk u_tmds_rpll/rpll_inst/CLKOUTD
u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk Generated 9.259 108.0 0.000 4.630 clk_ibuf/I clk u_tmds_rpll/rpll_inst/CLKOUTD3
u_clkdiv/CLKOUT.default_gen_clk Generated 15.432 64.8 0.000 7.716 u_tmds_rpll/rpll_inst/CLKOUT u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk u_clkdiv/CLKOUT
DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk Generated 10.044 99.6 0.000 5.022 mem_pll_m0/rpll_inst/CLKOUT mem_pll_m0/rpll_inst/CLKOUT.default_gen_clk DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 27.000(MHz) 128.139(MHz) 8 TOP
2 cmos_pclk 100.000(MHz) 577.367(MHz) 2 TOP
3 cmos_8_16bit_m0/cmos_16bit_clk 100.000(MHz) 170.999(MHz) 6 TOP
4 DVI_TX_Top/Pout_vs_dn[4] 100.000(MHz) 430.033(MHz) 3 TOP
5 cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk 24.000(MHz) 411.353(MHz) 3 TOP
6 mem_pll_m0/rpll_inst/CLKOUT.default_gen_clk 398.250(MHz) 1030.928(MHz) 1 TOP
7 u_clkdiv/CLKOUT.default_gen_clk 64.800(MHz) 91.475(MHz) 12 TOP
8 DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk 99.562(MHz) 103.263(MHz) 10 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -8.660
Data Arrival Time 302.500
Data Required Time 293.841
From bin_img[0]_7_s0
To bin_view_s0
Launch Clk cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk u_clkdiv/CLKOUT.default_gen_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
291.667 0.000 cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk
292.845 1.179 tCL RR 798 cmos_pll_m0/rpll_inst/CLKOUT
293.205 0.360 tNET RR 1 bin_img[0]_7_s0/CLK
293.437 0.232 tC2Q RF 2 bin_img[0]_7_s0/Q
293.911 0.474 tNET FF 1 n5391_s66/I1
294.466 0.555 tINS FF 1 n5391_s66/F
294.940 0.474 tNET FF 1 n5391_s60/I0
295.043 0.103 tINS FF 1 n5391_s60/O
295.517 0.474 tNET FF 1 n5391_s58/I0
295.620 0.103 tINS FF 1 n5391_s58/O
296.094 0.474 tNET FF 1 n5391_s57/I0
296.197 0.103 tINS FF 1 n5391_s57/O
296.671 0.474 tNET FF 1 n5630_s109/I1
297.226 0.555 tINS FF 1 n5630_s109/F
297.700 0.474 tNET FF 1 n5630_s86/I2
298.153 0.453 tINS FF 1 n5630_s86/F
298.627 0.474 tNET FF 1 n5630_s62/I1
299.182 0.555 tINS FF 1 n5630_s62/F
299.656 0.474 tNET FF 1 n5630_s49/I3
300.027 0.371 tINS FF 1 n5630_s49/F
300.501 0.474 tNET FF 1 n5630_s118/I3
300.872 0.371 tINS FF 1 n5630_s118/F
301.346 0.474 tNET FF 1 n5630_s116/I0
301.449 0.103 tINS FF 1 n5630_s116/O
301.923 0.474 tNET FF 1 n5630_s41/I0
302.026 0.103 tINS FF 1 n5630_s41/O
302.500 0.474 tNET FF 1 bin_view_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
293.210 0.000 u_clkdiv/CLKOUT.default_gen_clk
293.551 0.341 tCL RR 276 u_clkdiv/CLKOUT
293.911 0.360 tNET RR 1 bin_view_s0/CLK
293.876 -0.035 tUnc bin_view_s0
293.841 -0.035 tSu 1 bin_view_s0
Path Statistics:
Clock Skew: -0.838
Setup Relationship: 1.543
Logic Level: 8
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 3.375, 36.310%; route: 5.688, 61.194%; tC2Q: 0.232, 2.496%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 2

Path Summary:
Slack -5.229
Data Arrival Time 215.519
Data Required Time 210.290
From bin_img[5]_3_s0
To u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_56.lut_56_ff_s0
Launch Clk cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk cmos_8_16bit_m0/cmos_16bit_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
208.333 0.000 cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk
209.512 1.179 tCL RR 798 cmos_pll_m0/rpll_inst/CLKOUT
209.872 0.360 tNET RR 1 bin_img[5]_3_s0/CLK
210.104 0.232 tC2Q RF 4 bin_img[5]_3_s0/Q
210.578 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub1/i_MnistLutSimple_sub1_base/layer1_data_99_s2/I1
211.133 0.555 tINS FF 2 u_MnistLutSimple/i_MnistLutSimple_sub1/i_MnistLutSimple_sub1_base/layer1_data_99_s2/F
211.607 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub1/i_MnistLutSimple_sub1_base/layer1_data_99_s0/I1
212.162 0.555 tINS FF 2 u_MnistLutSimple/i_MnistLutSimple_sub1/i_MnistLutSimple_sub1_base/layer1_data_99_s0/F
212.636 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub1/i_MnistLutSimple_sub1_base/layer1_data_99_s/I2
213.089 0.453 tINS FF 2 u_MnistLutSimple/i_MnistLutSimple_sub1/i_MnistLutSimple_sub1_base/layer1_data_99_s/F
213.563 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_56_out_s48/I2
214.016 0.453 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_56_out_s48/F
214.490 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_56_out_s47/I1
215.045 0.555 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_56_out_s47/F
215.519 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_56.lut_56_ff_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
210.000 0.000 cmos_8_16bit_m0/cmos_16bit_clk
210.000 0.000 tCL RR 987 cmos_8_16bit_m0/de_o_s0/Q
210.360 0.360 tNET RR 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_56.lut_56_ff_s0/CLK
210.325 -0.035 tUnc u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_56.lut_56_ff_s0
210.290 -0.035 tSu 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_56.lut_56_ff_s0
Path Statistics:
Clock Skew: -1.179
Setup Relationship: 1.667
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.571, 45.529%; route: 2.844, 50.363%; tC2Q: 0.232, 4.108%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack -5.147
Data Arrival Time 215.437
Data Required Time 210.290
From bin_img[24]_16_s0
To u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_9.lut_9_ff_s0
Launch Clk cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk cmos_8_16bit_m0/cmos_16bit_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
208.333 0.000 cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk
209.512 1.179 tCL RR 798 cmos_pll_m0/rpll_inst/CLKOUT
209.872 0.360 tNET RR 1 bin_img[24]_16_s0/CLK
210.104 0.232 tC2Q RF 4 bin_img[24]_16_s0/Q
210.578 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_9_out_s58/I1
211.133 0.555 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_9_out_s58/F
211.607 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_9_out_s55/I2
212.060 0.453 tINS FF 2 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_9_out_s55/F
212.534 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_41_out_s49/I1
213.089 0.555 tINS FF 2 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_41_out_s49/F
213.563 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_9_out_s48/I3
213.934 0.371 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_9_out_s48/F
214.408 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_9_out_s46/I1
214.963 0.555 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_9_out_s46/F
215.437 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_9.lut_9_ff_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
210.000 0.000 cmos_8_16bit_m0/cmos_16bit_clk
210.000 0.000 tCL RR 987 cmos_8_16bit_m0/de_o_s0/Q
210.360 0.360 tNET RR 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_9.lut_9_ff_s0/CLK
210.325 -0.035 tUnc u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_9.lut_9_ff_s0
210.290 -0.035 tSu 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_9.lut_9_ff_s0
Path Statistics:
Clock Skew: -1.179
Setup Relationship: 1.667
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.489, 44.726%; route: 2.844, 51.105%; tC2Q: 0.232, 4.169%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack -5.065
Data Arrival Time 215.355
Data Required Time 210.290
From bin_img[13]_9_s0
To u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_19.lut_19_ff_s0
Launch Clk cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk cmos_8_16bit_m0/cmos_16bit_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
208.333 0.000 cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk
209.512 1.179 tCL RR 798 cmos_pll_m0/rpll_inst/CLKOUT
209.872 0.360 tNET RR 1 bin_img[13]_9_s0/CLK
210.104 0.232 tC2Q RF 4 bin_img[13]_9_s0/Q
210.578 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_51_out_s58/I1
211.133 0.555 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_51_out_s58/F
211.607 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_51_out_s50/I1
212.162 0.555 tINS FF 2 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_51_out_s50/F
212.636 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_19_out_s52/I1
213.191 0.555 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_19_out_s52/F
213.665 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_19_out_s48/I3
214.036 0.371 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_19_out_s48/F
214.510 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_19_out_s44/I3
214.881 0.371 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_19_out_s44/F
215.355 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_19.lut_19_ff_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
210.000 0.000 cmos_8_16bit_m0/cmos_16bit_clk
210.000 0.000 tCL RR 987 cmos_8_16bit_m0/de_o_s0/Q
210.360 0.360 tNET RR 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_19.lut_19_ff_s0/CLK
210.325 -0.035 tUnc u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_19.lut_19_ff_s0
210.290 -0.035 tSu 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_19.lut_19_ff_s0
Path Statistics:
Clock Skew: -1.179
Setup Relationship: 1.667
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.407, 43.899%; route: 2.844, 51.870%; tC2Q: 0.232, 4.231%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack -5.048
Data Arrival Time 215.338
Data Required Time 210.290
From bin_img[5]_24_s0
To u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_24.lut_24_ff_s1
Launch Clk cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk[R]
Latch Clk cmos_8_16bit_m0/cmos_16bit_clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
208.333 0.000 cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk
209.512 1.179 tCL RR 798 cmos_pll_m0/rpll_inst/CLKOUT
209.872 0.360 tNET RR 1 bin_img[5]_24_s0/CLK
210.104 0.232 tC2Q RF 3 bin_img[5]_24_s0/Q
210.578 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_24_out_s58/I1
211.133 0.555 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_24_out_s58/F
211.607 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_24_out_s57/I0
212.124 0.517 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_24_out_s57/F
212.598 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_24_out_s55/I2
213.051 0.453 tINS FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_24_out_s55/F
213.525 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_24_out_s50/I0
214.042 0.517 tINS FF 2 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_24_out_s50/F
214.516 0.474 tNET FF 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_24_out_s47/I2
214.978 0.462 tINS FR 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/lut_24_out_s47/F
215.338 0.360 tNET RR 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_24.lut_24_ff_s1/SET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
210.000 0.000 cmos_8_16bit_m0/cmos_16bit_clk
210.000 0.000 tCL RR 987 cmos_8_16bit_m0/de_o_s0/Q
210.360 0.360 tNET RR 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_24.lut_24_ff_s1/CLK
210.325 -0.035 tUnc u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_24.lut_24_ff_s1
210.290 -0.035 tSu 1 u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ff_24.lut_24_ff_s1
Path Statistics:
Clock Skew: -1.179
Setup Relationship: 1.667
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 2.504, 45.810%; route: 2.730, 49.946%; tC2Q: 0.232, 4.244%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%