Power Messages

Report Title Power Analysis Report
Design File H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\impl\gwsynthesis\top.vg
Physical Constraints File H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\top.cst
Timing Constraints File H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\lcd.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Tue Nov 19 02:11:06 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Power Summary

Power Information:

Total Power (mW) 603.481
Quiescent Power (mW) 91.830
Dynamic Power (mW) 511.651

Thermal Information:

Junction Temperature 44.323
Theta JA 32.020
Max Allowed Ambient Temperature 65.677

Configure Information:

Default IO Toggle Rate 0.125
Default Remain Toggle Rate 0.125
Use Vectorless Estimation false
Filter Glitches false
Related Vcd File
Related Saif File
Use Custom Theta JA false
Air Flow LFM_0
Heat Sink None
Use Custom Theta SA false
Board Thermal Model None
Use Custom Theta JB false
Ambient Temperature 25.000

Supply Information:

Voltage Source Voltage Dynamic Current(mA) Quiescent Current(mA) Power(mW)
VCC 1.000 437.044 61.461 498.505
VCCX 2.500 13.025 11.364 60.971
VCCIO12 1.200 0.158 0.056 0.257
VCCIO15 1.500 11.063 0.613 17.514
VCCIO33 3.300 7.655 0.295 26.234

Power Details

Power By Block Type:

Block Type Total Power(mW) Static Power(mW) Average Toggle Rate(millions of transitions/sec)
Logic 6.292 NA 9.065
IO 99.303 11.013 46.890
BSRAM 246.660 NA NA
PLL 78.060 NA NA
DLL 92.160 NA NA
DQS 231.300 NA NA

Power By Hierarchy:

Hierarchy Entity Total Power(mW) Block Dynamic Power(mW)
top 654.472 654.472(653.463)
top/DDR3_Memory_Interface_Top_inst/ 457.443 457.443(457.443)
top/DDR3_Memory_Interface_Top_inst/gw3_top/ 457.443 457.443(457.443)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/ 455.862 455.862(363.333)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr3_sync/ 0.058 0.058(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ 0.583 0.583(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/ 362.692 362.692(362.685)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/ 246.704 246.704(246.696)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/ 115.655 115.655(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_in_fifo/ 65.520 65.520(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_out_fifo/ 65.521 65.521(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/ 115.659 115.659(115.651)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/ 115.651 115.651(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/ 0.219 0.219(0.154)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_cmd_fifo/ 0.154 0.154(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_fifo_ctrl/ 0.103 0.103(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/ 1.580 1.580(1.320)
top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_cmd0/ 0.320 0.320(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_rd_data0/ 0.195 0.195(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/ 0.307 0.307(0.305)
top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gw_wr_data0/wr_fifo/ 0.305 0.305(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gwmc_bank_ctrl/ 0.376 0.376(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gwmc_rank_ctrl/ 0.088 0.088(0.000)
top/DDR3_Memory_Interface_Top_inst/gw3_top/u_gwmc_top/gwmc_timing_ctrl/ 0.034 0.034(0.000)
top/DVI_TX_Top_inst/ 0.473 0.473(0.473)
top/DVI_TX_Top_inst/rgb2dvi_inst/ 0.473 0.473(0.473)
top/DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_b/ 0.157 0.157(0.000)
top/DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_g/ 0.159 0.159(0.000)
top/DVI_TX_Top_inst/rgb2dvi_inst/TMDS8b10b_inst_r/ 0.157 0.157(0.000)
top/Video_Frame_Buffer_Top_inst/ 116.746 116.746(116.746)
top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/ 116.746 116.746(116.746)
top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/ 116.453 116.453(116.453)
top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_frame_ctrl/ 0.019 0.019(0.000)
top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/ 54.318 54.318(54.199)
top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/ 54.153 54.153(0.000)
top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/ 0.046 0.046(0.000)
top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/ 62.116 62.116(62.023)
top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/ 61.961 61.961(0.000)
top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/u_dma_16b_32b/ 0.062 0.062(0.000)
top/Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u_dma_bus_arbiter/ 0.293 0.293(0.000)
top/cmos_8_16bit_m0/ 0.021 0.021(0.000)
top/cmos_pll_m0/ 2.510 2.510(0.000)
top/i2c_config_m0/ 0.255 0.255(0.248)
top/i2c_config_m0/i2c_master_top_m0/ 0.248 0.248(0.082)
top/i2c_config_m0/i2c_master_top_m0/byte_controller/ 0.082 0.082(0.066)
top/i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/ 0.066 0.066(0.000)
top/mem_pll_m0/ 41.658 41.658(0.000)
top/u_MnistLutSimple/ 0.414 0.414(0.414)
top/u_MnistLutSimple/i_MnistLutSimple_sub1/ 0.008 0.008(0.008)
top/u_MnistLutSimple/i_MnistLutSimple_sub1/i_MnistLutSimple_sub1_base/ 0.008 0.008(0.000)
top/u_MnistLutSimple/i_MnistLutSimple_sub2/ 0.201 0.201(0.201)
top/u_MnistLutSimple/i_MnistLutSimple_sub2/i_MnistLutSimple_sub2_base/ 0.201 0.201(0.000)
top/u_MnistLutSimple/i_MnistLutSimple_sub5/ 0.205 0.205(0.205)
top/u_MnistLutSimple/i_MnistLutSimple_sub5/i_MnistLutSimple_sub5_base/ 0.205 0.205(0.000)
top/u_tmds_rpll/ 33.891 33.891(0.000)
top/vga_timing_m0/ 0.052 0.052(0.000)

Power By Clock Domain:

Clock Domain Clock Frequency(Mhz) Total Dynamic Power(mW)
clk 27.000 78.317
cmos_pclk 100.000 0.124
cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk 24.000 0.390
cmos_16bit_clk 100.000 29.911
u_clkdiv/CLKOUT.default_gen_clk 64.800 22.281
DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk 100.000 200.031
NO CLOCK DOMAIN 0.000 0.000
cmos_vsync 1.000 0.000
Pout_vs_dn[4] 100.000 0.049
u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk 324.000 0.044
mem_clk 400.000 323.514