Timing Messages
Report Title | Timing Analysis Report |
Design File | H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\impl\gwsynthesis\top.vg |
Physical Constraints File | H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\top.cst |
Timing Constraint File | H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\lcd.sdc |
Tool Version | V1.9.9.01 (64-bit) |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Tue Nov 19 02:11:06 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 19257 |
Numbers of Endpoints Analyzed | 10564 |
Numbers of Falling Endpoints | 14 |
Numbers of Setup Violated Endpoints | 2099 |
Numbers of Hold Violated Endpoints | 869 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clk | Base | 37.037 | 27.000 | 0.000 | 18.518 | clk | ||
cmos_pclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | cmos_pclk | ||
cmos_vsync | Base | 1000.000 | 1.000 | 0.000 | 500.000 | cmos_vsync | ||
mem_clk | Base | 2.500 | 400.000 | 0.000 | 1.250 | memory_clk | ||
Pout_vs_dn[4] | Base | 10.000 | 100.000 | 0.000 | 5.000 | Pout_vs_dn_4_s0/Q | ||
cmos_16bit_clk | Base | 10.000 | 100.000 | 0.000 | 5.000 | cmos_8_16bit_m0/de_o_s0/Q | ||
cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk | Generated | 41.667 | 24.000 | 0.000 | 20.833 | clk_ibuf/I | clk | cmos_pll_m0/rpll_inst/CLKOUT |
cmos_pll_m0/rpll_inst/CLKOUTP.default_gen_clk | Generated | 41.667 | 24.000 | 0.000 | 20.833 | clk_ibuf/I | clk | cmos_pll_m0/rpll_inst/CLKOUTP |
cmos_pll_m0/rpll_inst/CLKOUTD.default_gen_clk | Generated | 83.333 | 12.000 | 0.000 | 41.667 | clk_ibuf/I | clk | cmos_pll_m0/rpll_inst/CLKOUTD |
cmos_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 125.000 | 8.000 | 0.000 | 62.500 | clk_ibuf/I | clk | cmos_pll_m0/rpll_inst/CLKOUTD3 |
mem_pll_m0/rpll_inst/CLKOUTP.default_gen_clk | Generated | 2.511 | 398.250 | 0.000 | 1.255 | clk_ibuf/I | clk | mem_pll_m0/rpll_inst/CLKOUTP |
mem_pll_m0/rpll_inst/CLKOUTD.default_gen_clk | Generated | 5.022 | 199.125 | 0.000 | 2.511 | clk_ibuf/I | clk | mem_pll_m0/rpll_inst/CLKOUTD |
mem_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 7.533 | 132.750 | 0.000 | 3.766 | clk_ibuf/I | clk | mem_pll_m0/rpll_inst/CLKOUTD3 |
u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk | Generated | 3.086 | 324.000 | 0.000 | 1.543 | clk_ibuf/I | clk | u_tmds_rpll/rpll_inst/CLKOUT |
u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk | Generated | 3.086 | 324.000 | 0.000 | 1.543 | clk_ibuf/I | clk | u_tmds_rpll/rpll_inst/CLKOUTP |
u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk | Generated | 6.173 | 162.000 | 0.000 | 3.086 | clk_ibuf/I | clk | u_tmds_rpll/rpll_inst/CLKOUTD |
u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk | Generated | 9.259 | 108.000 | 0.000 | 4.630 | clk_ibuf/I | clk | u_tmds_rpll/rpll_inst/CLKOUTD3 |
u_clkdiv/CLKOUT.default_gen_clk | Generated | 15.432 | 64.800 | 0.000 | 7.716 | u_tmds_rpll/rpll_inst/CLKOUT | u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk | u_clkdiv/CLKOUT |
DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | Generated | 10.000 | 100.000 | 0.000 | 5.000 | mem_pll_m0/rpll_inst/CLKOUT | mem_clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk | 27.000(MHz) | 109.047(MHz) | 8 | TOP |
2 | cmos_pclk | 100.000(MHz) | 632.785(MHz) | 2 | TOP |
3 | mem_clk | 400.000(MHz) | 2016.129(MHz) | 1 | TOP |
4 | Pout_vs_dn[4] | 100.000(MHz) | 446.359(MHz) | 3 | TOP |
5 | cmos_16bit_clk | 100.000(MHz) | 200.286(MHz) | 6 | TOP |
6 | cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk | 24.000(MHz) | 401.811(MHz) | 3 | TOP |
7 | u_clkdiv/CLKOUT.default_gen_clk | 64.800(MHz) | 105.370(MHz) | 8 | TOP |
8 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | 100.000(MHz) | 816.920(MHz) | 1 | TOP |
No timing paths to get frequency of cmos_vsync!
No timing paths to get frequency of cmos_pll_m0/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of cmos_pll_m0/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of cmos_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of mem_pll_m0/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of mem_pll_m0/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of mem_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk!
No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk!
No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk!
No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk!
No timing paths to get frequency of u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk!
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk | Setup | 0.000 | 0 |
clk | Hold | 0.000 | 0 |
cmos_pclk | Setup | 0.000 | 0 |
cmos_pclk | Hold | 0.000 | 0 |
cmos_vsync | Setup | 0.000 | 0 |
cmos_vsync | Hold | 0.000 | 0 |
mem_clk | Setup | 0.000 | 0 |
mem_clk | Hold | 0.000 | 0 |
Pout_vs_dn[4] | Setup | 0.000 | 0 |
Pout_vs_dn[4] | Hold | 0.000 | 0 |
cmos_16bit_clk | Setup | 0.000 | 0 |
cmos_16bit_clk | Hold | 0.000 | 0 |
cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
cmos_pll_m0/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
cmos_pll_m0/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
cmos_pll_m0/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
cmos_pll_m0/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
cmos_pll_m0/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
cmos_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
cmos_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
mem_pll_m0/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
mem_pll_m0/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
mem_pll_m0/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
mem_pll_m0/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
mem_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
mem_pll_m0/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
u_tmds_rpll/rpll_inst/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk | Setup | 0.000 | 0 |
u_tmds_rpll/rpll_inst/CLKOUTP.default_gen_clk | Hold | 0.000 | 0 |
u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk | Setup | 0.000 | 0 |
u_tmds_rpll/rpll_inst/CLKOUTD.default_gen_clk | Hold | 0.000 | 0 |
u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk | Setup | 0.000 | 0 |
u_tmds_rpll/rpll_inst/CLKOUTD3.default_gen_clk | Hold | 0.000 | 0 |
u_clkdiv/CLKOUT.default_gen_clk | Setup | 0.000 | 0 |
u_clkdiv/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | Setup | -0.049 | 1 |
DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 27.867 | i2c_config_m0/lut_index_7_s2/Q | i2c_config_m0/i2c_master_top_m0/txr_4_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 9.135 |
2 | 28.239 | i2c_config_m0/lut_index_3_s2/Q | i2c_config_m0/i2c_master_top_m0/txr_3_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 8.763 |
3 | 28.370 | i2c_config_m0/lut_index_9_s2/Q | i2c_config_m0/i2c_master_top_m0/txr_1_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 8.632 |
4 | 28.436 | i2c_config_m0/lut_index_9_s2/Q | i2c_config_m0/i2c_master_top_m0/txr_2_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 8.566 |
5 | 28.620 | i2c_config_m0/lut_index_9_s2/Q | i2c_config_m0/i2c_master_top_m0/txr_0_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 8.382 |
6 | 28.854 | i2c_config_m0/lut_index_7_s2/Q | i2c_config_m0/i2c_master_top_m0/txr_6_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 8.148 |
7 | 28.867 | i2c_config_m0/lut_index_8_s2/Q | i2c_config_m0/i2c_master_top_m0/txr_5_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 8.135 |
8 | 28.875 | i2c_config_m0/lut_index_9_s2/Q | i2c_config_m0/i2c_master_top_m0/txr_7_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 8.127 |
9 | 30.404 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s0/CE | clk:[R] | clk:[R] | 37.037 | 0.000 | 6.598 |
10 | 30.504 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 6.498 |
11 | 30.517 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s0/CE | clk:[R] | clk:[R] | 37.037 | 0.000 | 6.485 |
12 | 31.463 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.539 |
13 | 31.738 | i2c_config_m0/lut_index_9_s2/Q | i2c_config_m0/i2c_write_req_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.264 |
14 | 32.074 | i2c_config_m0/lut_index_9_s2/Q | i2c_config_m0/i2c_write_req_s0/CE | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.928 |
15 | 32.137 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_11_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.865 |
16 | 32.197 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.805 |
17 | 32.197 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_4_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.805 |
18 | 32.197 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.805 |
19 | 32.218 | i2c_config_m0/lut_index_9_s2/Q | i2c_config_m0/state_0_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.784 |
20 | 32.234 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_11_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.768 |
21 | 32.252 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_15_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.750 |
22 | 32.252 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_16_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.750 |
23 | 32.263 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_12_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.739 |
24 | 32.288 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_7_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.714 |
25 | 32.349 | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_1_s2/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_3_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.653 |
Hold Paths Table
Report Command:report_timing -hold -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.425 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.436 |
2 | 0.425 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_6_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_6_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.436 |
3 | 0.425 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.436 |
4 | 0.425 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.436 |
5 | 0.425 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_6_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_6_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.436 |
6 | 0.425 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_8_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_8_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.436 |
7 | 0.425 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_12_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_12_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.436 |
8 | 0.425 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_14_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_14_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.436 |
9 | 0.427 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_14_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_14_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.438 |
10 | 0.427 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_1_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_1_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.438 |
11 | 0.427 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_8_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_8_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.438 |
12 | 0.427 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_12_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_12_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.438 |
13 | 0.427 | i2c_config_m0/i2c_master_top_m0/byte_controller/dcnt_1_s3/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/dcnt_1_s3/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.438 |
14 | 0.428 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_0_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.439 |
15 | 0.428 | i2c_config_m0/i2c_master_top_m0/write_s5/Q | i2c_config_m0/i2c_master_top_m0/write_s5/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.439 |
16 | 0.429 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_3_s0/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_3_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.440 |
17 | 0.429 | i2c_config_m0/lut_index_0_s4/Q | i2c_config_m0/lut_index_0_s4/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.440 |
18 | 0.429 | i2c_config_m0/lut_index_8_s2/Q | i2c_config_m0/lut_index_8_s2/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.440 |
19 | 0.430 | i2c_config_m0/lut_index_5_s2/Q | i2c_config_m0/lut_index_5_s2/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.441 |
20 | 0.430 | i2c_config_m0/lut_index_7_s2/Q | i2c_config_m0/lut_index_7_s2/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.441 |
21 | 0.432 | i2c_config_m0/lut_index_3_s2/Q | i2c_config_m0/lut_index_3_s2/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.443 |
22 | 0.434 | i2c_config_m0/lut_index_6_s2/Q | i2c_config_m0/lut_index_6_s2/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.445 |
23 | 0.460 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_1_s0/CE | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.471 |
24 | 0.460 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0/CE | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.471 |
25 | 0.460 | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/Q | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_3_s0/CE | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.471 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -4.270 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
2 | -4.270 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
3 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
4 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
5 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
6 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
7 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
8 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
9 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
10 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
11 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
12 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
13 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
14 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
15 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
16 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
17 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
18 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
19 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
20 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
21 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[5].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
22 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
23 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[3].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
24 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
25 | -3.925 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[1].u_cmd_gen/RESET | u_clkdiv/CLKOUT.default_gen_clk:[R] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | 0.001 | 1.880 | 1.858 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_0_s3/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
2 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
3 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
4 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_1_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
5 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
6 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
7 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
8 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
9 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
10 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_7_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
11 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
12 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
13 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
14 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
15 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_12_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
16 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_13_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
17 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
18 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_15_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
19 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_den_16b_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
20 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
21 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
22 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
23 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
24 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
25 | -0.991 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0/CLEAR | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] | u_clkdiv/CLKOUT.default_gen_clk:[R] | -0.002 | -1.880 | 0.936 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 1.893 | 2.893 | 1.000 | Low Pulse Width | cmos_pclk | cmos_8_16bit_m0/pdata_i_d0_6_s0 |
2 | 1.893 | 2.893 | 1.000 | Low Pulse Width | cmos_pclk | cmos_8_16bit_m0/pdata_i_d0_5_s0 |
3 | 1.893 | 2.893 | 1.000 | Low Pulse Width | cmos_pclk | cmos_8_16bit_m0/pdata_i_d0_4_s0 |
4 | 1.893 | 2.893 | 1.000 | Low Pulse Width | cmos_pclk | cmos_8_16bit_m0/pdata_i_d0_3_s0 |
5 | 1.893 | 2.893 | 1.000 | Low Pulse Width | cmos_pclk | cmos_8_16bit_m0/pdata_i_d0_2_s0 |
6 | 1.893 | 2.893 | 1.000 | Low Pulse Width | cmos_pclk | cmos_8_16bit_m0/pdata_o_7_s0 |
7 | 1.893 | 2.893 | 1.000 | Low Pulse Width | cmos_pclk | cmos_8_16bit_m0/pdata_i_d0_7_s0 |
8 | 1.893 | 2.893 | 1.000 | Low Pulse Width | cmos_pclk | cmos_8_16bit_m0/x_cnt_s1 |
9 | 1.893 | 2.893 | 1.000 | Low Pulse Width | cmos_pclk | cmos_8_16bit_m0/pdata_o_6_s0 |
10 | 1.893 | 2.893 | 1.000 | Low Pulse Width | cmos_pclk | cmos_8_16bit_m0/pdata_o_3_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 27.867 |
Data Arrival Time | 13.495 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_7_s2 |
To | i2c_config_m0/i2c_master_top_m0/txr_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R16C7[1][A] | i2c_config_m0/lut_index_7_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 18 | R16C7[1][A] | i2c_config_m0/lut_index_7_s2/Q |
5.688 | 1.097 | tNET | FF | 1 | R24C7[3][A] | i2c_config_m0/i2c_master_top_m0/n199_s15/I3 |
6.205 | 0.517 | tINS | FF | 22 | R24C7[3][A] | i2c_config_m0/i2c_master_top_m0/n199_s15/F |
7.438 | 1.233 | tNET | FF | 1 | R14C8[1][B] | i2c_config_m0/i2c_master_top_m0/n207_s14/I2 |
7.809 | 0.371 | tINS | FF | 2 | R14C8[1][B] | i2c_config_m0/i2c_master_top_m0/n207_s14/F |
8.809 | 1.000 | tNET | FF | 1 | R23C8[1][B] | i2c_config_m0/i2c_master_top_m0/n203_s56/I2 |
9.326 | 0.517 | tINS | FF | 1 | R23C8[1][B] | i2c_config_m0/i2c_master_top_m0/n203_s56/F |
9.739 | 0.413 | tNET | FF | 1 | R23C11[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s34/I3 |
10.256 | 0.517 | tINS | FF | 2 | R23C11[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s34/F |
11.337 | 1.081 | tNET | FF | 1 | R16C9[2][B] | i2c_config_m0/i2c_master_top_m0/n211_s16/I1 |
11.790 | 0.453 | tINS | FF | 1 | R16C9[2][B] | i2c_config_m0/i2c_master_top_m0/n211_s16/F |
12.203 | 0.413 | tNET | FF | 1 | R13C9[3][A] | i2c_config_m0/i2c_master_top_m0/n211_s9/I1 |
12.773 | 0.570 | tINS | FR | 1 | R13C9[3][A] | i2c_config_m0/i2c_master_top_m0/n211_s9/F |
12.946 | 0.172 | tNET | RR | 1 | R13C8[1][B] | i2c_config_m0/i2c_master_top_m0/n211_s6/I2 |
13.495 | 0.549 | tINS | RR | 1 | R13C8[1][B] | i2c_config_m0/i2c_master_top_m0/n211_s6/F |
13.495 | 0.000 | tNET | RR | 1 | R13C8[1][B] | i2c_config_m0/i2c_master_top_m0/txr_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R13C8[1][B] | i2c_config_m0/i2c_master_top_m0/txr_4_s0/CLK |
41.361 | -0.035 | tSu | 1 | R13C8[1][B] | i2c_config_m0/i2c_master_top_m0/txr_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.494, 38.247%; route: 5.409, 59.213%; tC2Q: 0.232, 2.540% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path2
Path Summary:
Slack | 28.239 |
Data Arrival Time | 13.122 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_3_s2 |
To | i2c_config_m0/i2c_master_top_m0/txr_3_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R17C7[0][A] | i2c_config_m0/lut_index_3_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 118 | R17C7[0][A] | i2c_config_m0/lut_index_3_s2/Q |
5.706 | 1.115 | tNET | FF | 1 | R14C6[0][A] | i2c_config_m0/n77_s2/I3 |
6.261 | 0.555 | tINS | FF | 21 | R14C6[0][A] | i2c_config_m0/n77_s2/F |
7.258 | 0.997 | tNET | FF | 1 | R25C8[3][A] | i2c_config_m0/i2c_master_top_m0/n203_s75/I0 |
7.813 | 0.555 | tINS | FF | 2 | R25C8[3][A] | i2c_config_m0/i2c_master_top_m0/n203_s75/F |
8.501 | 0.688 | tNET | FF | 1 | R21C8[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s22/I0 |
8.954 | 0.453 | tINS | FF | 2 | R21C8[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s22/F |
9.526 | 0.572 | tNET | FF | 1 | R21C11[2][B] | i2c_config_m0/i2c_master_top_m0/n215_s36/I3 |
10.081 | 0.555 | tINS | FF | 1 | R21C11[2][B] | i2c_config_m0/i2c_master_top_m0/n215_s36/F |
10.980 | 0.899 | tNET | FF | 1 | R24C11[2][B] | i2c_config_m0/i2c_master_top_m0/n215_s16/I3 |
11.433 | 0.453 | tINS | FF | 1 | R24C11[2][B] | i2c_config_m0/i2c_master_top_m0/n215_s16/F |
12.089 | 0.656 | tNET | FF | 1 | R25C11[2][A] | i2c_config_m0/i2c_master_top_m0/n215_s9/I1 |
12.659 | 0.570 | tINS | FR | 1 | R25C11[2][A] | i2c_config_m0/i2c_master_top_m0/n215_s9/F |
12.660 | 0.001 | tNET | RR | 1 | R25C11[1][A] | i2c_config_m0/i2c_master_top_m0/n215_s6/I2 |
13.122 | 0.462 | tINS | RR | 1 | R25C11[1][A] | i2c_config_m0/i2c_master_top_m0/n215_s6/F |
13.122 | 0.000 | tNET | RR | 1 | R25C11[1][A] | i2c_config_m0/i2c_master_top_m0/txr_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R25C11[1][A] | i2c_config_m0/i2c_master_top_m0/txr_3_s0/CLK |
41.361 | -0.035 | tSu | 1 | R25C11[1][A] | i2c_config_m0/i2c_master_top_m0/txr_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.603, 41.116%; route: 4.928, 56.236%; tC2Q: 0.232, 2.648% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path3
Path Summary:
Slack | 28.370 |
Data Arrival Time | 12.991 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_9_s2 |
To | i2c_config_m0/i2c_master_top_m0/txr_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 12 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/Q |
5.914 | 1.322 | tNET | FF | 1 | R24C10[1][B] | i2c_config_m0/i2c_master_top_m0/n211_s24/I3 |
6.431 | 0.517 | tINS | FF | 29 | R24C10[1][B] | i2c_config_m0/i2c_master_top_m0/n211_s24/F |
7.999 | 1.568 | tNET | FF | 1 | R21C7[2][B] | i2c_config_m0/i2c_master_top_m0/n219_s91/I2 |
8.461 | 0.462 | tINS | FR | 2 | R21C7[2][B] | i2c_config_m0/i2c_master_top_m0/n219_s91/F |
8.634 | 0.174 | tNET | RR | 1 | R22C7[2][A] | i2c_config_m0/i2c_master_top_m0/n223_s35/I3 |
9.087 | 0.453 | tINS | RF | 2 | R22C7[2][A] | i2c_config_m0/i2c_master_top_m0/n223_s35/F |
10.289 | 1.202 | tNET | FF | 1 | R24C9[0][B] | i2c_config_m0/i2c_master_top_m0/n223_s19/I1 |
10.751 | 0.462 | tINS | FR | 1 | R24C9[0][B] | i2c_config_m0/i2c_master_top_m0/n223_s19/F |
10.753 | 0.001 | tNET | RR | 1 | R24C9[2][A] | i2c_config_m0/i2c_master_top_m0/n223_s10/I3 |
11.308 | 0.555 | tINS | RF | 1 | R24C9[2][A] | i2c_config_m0/i2c_master_top_m0/n223_s10/F |
11.721 | 0.413 | tNET | FF | 1 | R25C8[2][B] | i2c_config_m0/i2c_master_top_m0/n223_s7/I0 |
12.270 | 0.549 | tINS | FR | 1 | R25C8[2][B] | i2c_config_m0/i2c_master_top_m0/n223_s7/F |
12.442 | 0.172 | tNET | RR | 1 | R25C9[0][A] | i2c_config_m0/i2c_master_top_m0/n223_s6/I0 |
12.991 | 0.549 | tINS | RR | 1 | R25C9[0][A] | i2c_config_m0/i2c_master_top_m0/n223_s6/F |
12.991 | 0.000 | tNET | RR | 1 | R25C9[0][A] | i2c_config_m0/i2c_master_top_m0/txr_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R25C9[0][A] | i2c_config_m0/i2c_master_top_m0/txr_1_s0/CLK |
41.361 | -0.035 | tSu | 1 | R25C9[0][A] | i2c_config_m0/i2c_master_top_m0/txr_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.547, 41.091%; route: 4.853, 56.221%; tC2Q: 0.232, 2.688% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path4
Path Summary:
Slack | 28.436 |
Data Arrival Time | 12.926 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_9_s2 |
To | i2c_config_m0/i2c_master_top_m0/txr_2_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 12 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/Q |
5.672 | 1.081 | tNET | FF | 1 | R16C8[0][B] | i2c_config_m0/i2c_master_top_m0/n203_s27/I1 |
6.227 | 0.555 | tINS | FF | 28 | R16C8[0][B] | i2c_config_m0/i2c_master_top_m0/n203_s27/F |
7.074 | 0.847 | tNET | FF | 1 | R20C7[3][B] | i2c_config_m0/i2c_master_top_m0/n228_s96/I0 |
7.591 | 0.517 | tINS | FF | 15 | R20C7[3][B] | i2c_config_m0/i2c_master_top_m0/n228_s96/F |
8.269 | 0.678 | tNET | FF | 1 | R25C7[1][B] | i2c_config_m0/i2c_master_top_m0/n215_s66/I1 |
8.731 | 0.462 | tINS | FR | 1 | R25C7[1][B] | i2c_config_m0/i2c_master_top_m0/n215_s66/F |
8.732 | 0.001 | tNET | RR | 1 | R25C7[2][A] | i2c_config_m0/i2c_master_top_m0/n215_s40/I3 |
9.287 | 0.555 | tINS | RF | 2 | R25C7[2][A] | i2c_config_m0/i2c_master_top_m0/n215_s40/F |
10.433 | 1.146 | tNET | FF | 1 | R20C9[3][B] | i2c_config_m0/i2c_master_top_m0/n219_s14/I1 |
10.988 | 0.555 | tINS | FF | 1 | R20C9[3][B] | i2c_config_m0/i2c_master_top_m0/n219_s14/F |
11.385 | 0.397 | tNET | FF | 1 | R18C9[3][B] | i2c_config_m0/i2c_master_top_m0/n219_s8/I0 |
11.838 | 0.453 | tINS | FF | 1 | R18C9[3][B] | i2c_config_m0/i2c_master_top_m0/n219_s8/F |
12.356 | 0.518 | tNET | FF | 1 | R18C13[0][A] | i2c_config_m0/i2c_master_top_m0/n219_s6/I2 |
12.926 | 0.570 | tINS | FR | 1 | R18C13[0][A] | i2c_config_m0/i2c_master_top_m0/n219_s6/F |
12.926 | 0.000 | tNET | RR | 1 | R18C13[0][A] | i2c_config_m0/i2c_master_top_m0/txr_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R18C13[0][A] | i2c_config_m0/i2c_master_top_m0/txr_2_s0/CLK |
41.361 | -0.035 | tSu | 1 | R18C13[0][A] | i2c_config_m0/i2c_master_top_m0/txr_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.667, 42.806%; route: 4.667, 54.485%; tC2Q: 0.232, 2.708% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path5
Path Summary:
Slack | 28.620 |
Data Arrival Time | 12.742 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_9_s2 |
To | i2c_config_m0/i2c_master_top_m0/txr_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 12 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/Q |
5.914 | 1.322 | tNET | FF | 1 | R24C10[1][B] | i2c_config_m0/i2c_master_top_m0/n211_s24/I3 |
6.431 | 0.517 | tINS | FF | 29 | R24C10[1][B] | i2c_config_m0/i2c_master_top_m0/n211_s24/F |
7.403 | 0.972 | tNET | FF | 1 | R12C8[2][A] | i2c_config_m0/i2c_master_top_m0/n199_s49/I0 |
7.774 | 0.371 | tINS | FF | 16 | R12C8[2][A] | i2c_config_m0/i2c_master_top_m0/n199_s49/F |
8.598 | 0.824 | tNET | FF | 1 | R24C9[3][A] | i2c_config_m0/i2c_master_top_m0/n223_s56/I1 |
9.115 | 0.517 | tINS | FF | 2 | R24C9[3][A] | i2c_config_m0/i2c_master_top_m0/n223_s56/F |
9.367 | 0.252 | tNET | FF | 1 | R24C11[3][B] | i2c_config_m0/i2c_master_top_m0/n228_s46/I3 |
9.820 | 0.453 | tINS | FF | 1 | R24C11[3][B] | i2c_config_m0/i2c_master_top_m0/n228_s46/F |
10.868 | 1.048 | tNET | FF | 1 | R20C11[0][B] | i2c_config_m0/i2c_master_top_m0/n228_s20/I2 |
11.417 | 0.549 | tINS | FR | 1 | R20C11[0][B] | i2c_config_m0/i2c_master_top_m0/n228_s20/F |
11.419 | 0.001 | tNET | RR | 1 | R20C11[2][B] | i2c_config_m0/i2c_master_top_m0/n228_s9/I3 |
11.974 | 0.555 | tINS | RF | 1 | R20C11[2][B] | i2c_config_m0/i2c_master_top_m0/n228_s9/F |
12.371 | 0.397 | tNET | FF | 1 | R20C13[0][A] | i2c_config_m0/i2c_master_top_m0/n228_s6/I2 |
12.742 | 0.371 | tINS | FF | 1 | R20C13[0][A] | i2c_config_m0/i2c_master_top_m0/n228_s6/F |
12.742 | 0.000 | tNET | FF | 1 | R20C13[0][A] | i2c_config_m0/i2c_master_top_m0/txr_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R20C13[0][A] | i2c_config_m0/i2c_master_top_m0/txr_0_s0/CLK |
41.361 | -0.035 | tSu | 1 | R20C13[0][A] | i2c_config_m0/i2c_master_top_m0/txr_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.333, 39.762%; route: 4.817, 57.470%; tC2Q: 0.232, 2.768% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path6
Path Summary:
Slack | 28.854 |
Data Arrival Time | 12.507 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_7_s2 |
To | i2c_config_m0/i2c_master_top_m0/txr_6_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R16C7[1][A] | i2c_config_m0/lut_index_7_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 18 | R16C7[1][A] | i2c_config_m0/lut_index_7_s2/Q |
5.688 | 1.097 | tNET | FF | 1 | R24C7[3][A] | i2c_config_m0/i2c_master_top_m0/n199_s15/I3 |
6.205 | 0.517 | tINS | FF | 22 | R24C7[3][A] | i2c_config_m0/i2c_master_top_m0/n199_s15/F |
7.438 | 1.233 | tNET | FF | 1 | R14C8[1][B] | i2c_config_m0/i2c_master_top_m0/n207_s14/I2 |
7.809 | 0.371 | tINS | FF | 2 | R14C8[1][B] | i2c_config_m0/i2c_master_top_m0/n207_s14/F |
8.809 | 1.000 | tNET | FF | 1 | R23C8[1][B] | i2c_config_m0/i2c_master_top_m0/n203_s56/I2 |
9.326 | 0.517 | tINS | FF | 1 | R23C8[1][B] | i2c_config_m0/i2c_master_top_m0/n203_s56/F |
9.739 | 0.413 | tNET | FF | 1 | R23C11[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s34/I3 |
10.256 | 0.517 | tINS | FF | 2 | R23C11[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s34/F |
10.944 | 0.688 | tNET | FF | 1 | R16C10[2][A] | i2c_config_m0/i2c_master_top_m0/n203_s17/I3 |
11.493 | 0.549 | tINS | FR | 1 | R16C10[2][A] | i2c_config_m0/i2c_master_top_m0/n203_s17/F |
11.495 | 0.001 | tNET | RR | 1 | R16C10[2][B] | i2c_config_m0/i2c_master_top_m0/n203_s10/I1 |
11.957 | 0.462 | tINS | RR | 1 | R16C10[2][B] | i2c_config_m0/i2c_master_top_m0/n203_s10/F |
11.958 | 0.001 | tNET | RR | 1 | R16C10[0][A] | i2c_config_m0/i2c_master_top_m0/n203_s6/I3 |
12.507 | 0.549 | tINS | RR | 1 | R16C10[0][A] | i2c_config_m0/i2c_master_top_m0/n203_s6/F |
12.507 | 0.000 | tNET | RR | 1 | R16C10[0][A] | i2c_config_m0/i2c_master_top_m0/txr_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R16C10[0][A] | i2c_config_m0/i2c_master_top_m0/txr_6_s0/CLK |
41.361 | -0.035 | tSu | 1 | R16C10[0][A] | i2c_config_m0/i2c_master_top_m0/txr_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.482, 42.736%; route: 4.434, 54.417%; tC2Q: 0.232, 2.847% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path7
Path Summary:
Slack | 28.867 |
Data Arrival Time | 12.494 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_8_s2 |
To | i2c_config_m0/i2c_master_top_m0/txr_5_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R16C7[0][A] | i2c_config_m0/lut_index_8_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 13 | R16C7[0][A] | i2c_config_m0/lut_index_8_s2/Q |
5.553 | 0.962 | tNET | FF | 1 | R24C6[0][B] | i2c_config_m0/i2c_master_top_m0/n199_s38/I0 |
6.006 | 0.453 | tINS | FF | 17 | R24C6[0][B] | i2c_config_m0/i2c_master_top_m0/n199_s38/F |
6.896 | 0.890 | tNET | FF | 1 | R16C9[2][A] | i2c_config_m0/i2c_master_top_m0/n207_s23/I2 |
7.413 | 0.517 | tINS | FF | 5 | R16C9[2][A] | i2c_config_m0/i2c_master_top_m0/n207_s23/F |
8.432 | 1.019 | tNET | FF | 1 | R22C9[0][B] | i2c_config_m0/i2c_master_top_m0/n207_s56/I1 |
8.885 | 0.453 | tINS | FF | 1 | R22C9[0][B] | i2c_config_m0/i2c_master_top_m0/n207_s56/F |
9.718 | 0.834 | tNET | FF | 1 | R17C9[0][B] | i2c_config_m0/i2c_master_top_m0/n207_s35/I2 |
10.089 | 0.371 | tINS | FF | 1 | R17C9[0][B] | i2c_config_m0/i2c_master_top_m0/n207_s35/F |
10.337 | 0.247 | tNET | FF | 1 | R17C11[3][B] | i2c_config_m0/i2c_master_top_m0/n207_s16/I2 |
10.907 | 0.570 | tINS | FR | 1 | R17C11[3][B] | i2c_config_m0/i2c_master_top_m0/n207_s16/F |
11.079 | 0.172 | tNET | RR | 1 | R17C10[0][B] | i2c_config_m0/i2c_master_top_m0/n207_s8/I2 |
11.532 | 0.453 | tINS | RF | 1 | R17C10[0][B] | i2c_config_m0/i2c_master_top_m0/n207_s8/F |
11.945 | 0.413 | tNET | FF | 1 | R16C12[0][B] | i2c_config_m0/i2c_master_top_m0/n207_s6/I1 |
12.494 | 0.549 | tINS | FR | 1 | R16C12[0][B] | i2c_config_m0/i2c_master_top_m0/n207_s6/F |
12.494 | 0.000 | tNET | RR | 1 | R16C12[0][B] | i2c_config_m0/i2c_master_top_m0/txr_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R16C12[0][B] | i2c_config_m0/i2c_master_top_m0/txr_5_s0/CLK |
41.361 | -0.035 | tSu | 1 | R16C12[0][B] | i2c_config_m0/i2c_master_top_m0/txr_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.366, 41.377%; route: 4.537, 55.771%; tC2Q: 0.232, 2.852% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path8
Path Summary:
Slack | 28.875 |
Data Arrival Time | 12.486 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_9_s2 |
To | i2c_config_m0/i2c_master_top_m0/txr_7_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 12 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/Q |
5.914 | 1.322 | tNET | FF | 1 | R24C10[1][B] | i2c_config_m0/i2c_master_top_m0/n211_s24/I3 |
6.431 | 0.517 | tINS | FF | 29 | R24C10[1][B] | i2c_config_m0/i2c_master_top_m0/n211_s24/F |
7.403 | 0.972 | tNET | FF | 1 | R12C8[2][A] | i2c_config_m0/i2c_master_top_m0/n199_s49/I0 |
7.774 | 0.371 | tINS | FF | 16 | R12C8[2][A] | i2c_config_m0/i2c_master_top_m0/n199_s49/F |
8.895 | 1.121 | tNET | FF | 1 | R18C11[0][B] | i2c_config_m0/i2c_master_top_m0/n207_s13/I2 |
9.348 | 0.453 | tINS | FF | 1 | R18C11[0][B] | i2c_config_m0/i2c_master_top_m0/n207_s13/F |
9.595 | 0.247 | tNET | FF | 1 | R16C11[2][A] | i2c_config_m0/i2c_master_top_m0/n207_s7/I3 |
10.112 | 0.517 | tINS | FF | 2 | R16C11[2][A] | i2c_config_m0/i2c_master_top_m0/n207_s7/F |
10.530 | 0.418 | tNET | FF | 1 | R14C11[2][B] | i2c_config_m0/i2c_master_top_m0/n199_s13/I3 |
10.901 | 0.371 | tINS | FF | 1 | R14C11[2][B] | i2c_config_m0/i2c_master_top_m0/n199_s13/F |
11.071 | 0.170 | tNET | FF | 1 | R14C10[1][A] | i2c_config_m0/i2c_master_top_m0/n199_s7/I3 |
11.524 | 0.453 | tINS | FF | 1 | R14C10[1][A] | i2c_config_m0/i2c_master_top_m0/n199_s7/F |
11.938 | 0.413 | tNET | FF | 1 | R13C11[2][A] | i2c_config_m0/i2c_master_top_m0/n199_s6/I0 |
12.487 | 0.549 | tINS | FR | 1 | R13C11[2][A] | i2c_config_m0/i2c_master_top_m0/n199_s6/F |
12.487 | 0.000 | tNET | RR | 1 | R13C11[2][A] | i2c_config_m0/i2c_master_top_m0/txr_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R13C11[2][A] | i2c_config_m0/i2c_master_top_m0/txr_7_s0/CLK |
41.361 | -0.035 | tSu | 1 | R13C11[2][A] | i2c_config_m0/i2c_master_top_m0/txr_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.231, 39.755%; route: 4.664, 57.390%; tC2Q: 0.232, 2.855% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path9
Path Summary:
Slack | 30.404 |
Data Arrival Time | 10.958 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/CLK |
4.591 | 0.232 | tC2Q | RF | 3 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q |
4.841 | 0.249 | tNET | FF | 1 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/I0 |
5.396 | 0.555 | tINS | FF | 5 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/F |
5.967 | 0.572 | tNET | FF | 1 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/I3 |
6.516 | 0.549 | tINS | FR | 5 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/F |
6.693 | 0.176 | tNET | RR | 1 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/I3 |
7.146 | 0.453 | tINS | RF | 6 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/F |
8.052 | 0.906 | tNET | FF | 1 | R8C12[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n318_s0/I3 |
8.601 | 0.549 | tINS | FR | 2 | R8C12[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n318_s0/F |
8.603 | 0.003 | tNET | RR | 1 | R8C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s1/I2 |
9.120 | 0.517 | tINS | RF | 2 | R8C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s1/F |
9.692 | 0.572 | tNET | FF | 1 | R7C11[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s0/I2 |
10.063 | 0.371 | tINS | FF | 3 | R7C11[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s0/F |
10.487 | 0.423 | tNET | FF | 1 | R8C9[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s2/I1 |
10.814 | 0.327 | tINS | FR | 1 | R8C9[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s2/F |
10.958 | 0.144 | tNET | RR | 1 | R8C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R8C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s0/CLK |
41.361 | -0.035 | tSu | 1 | R8C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.321, 50.330%; route: 3.045, 46.154%; tC2Q: 0.232, 3.516% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path10
Path Summary:
Slack | 30.504 |
Data Arrival Time | 10.858 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/CLK |
4.591 | 0.232 | tC2Q | RF | 3 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q |
4.841 | 0.249 | tNET | FF | 1 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/I0 |
5.396 | 0.555 | tINS | FF | 5 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/F |
5.967 | 0.572 | tNET | FF | 1 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/I3 |
6.516 | 0.549 | tINS | FR | 5 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/F |
6.693 | 0.176 | tNET | RR | 1 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/I3 |
7.146 | 0.453 | tINS | RF | 6 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/F |
8.052 | 0.906 | tNET | FF | 1 | R8C12[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n318_s0/I3 |
8.601 | 0.549 | tINS | FR | 2 | R8C12[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n318_s0/F |
8.603 | 0.003 | tNET | RR | 1 | R8C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s1/I2 |
9.120 | 0.517 | tINS | RF | 2 | R8C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s1/F |
9.692 | 0.572 | tNET | FF | 1 | R7C11[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s0/I2 |
10.063 | 0.371 | tINS | FF | 3 | R7C11[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s0/F |
10.858 | 0.794 | tNET | FF | 1 | R8C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R8C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s0/CLK |
41.361 | -0.035 | tSu | 1 | R8C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/scl_oen_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.994, 46.074%; route: 3.272, 50.356%; tC2Q: 0.232, 3.570% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path11
Path Summary:
Slack | 30.517 |
Data Arrival Time | 10.844 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/CLK |
4.591 | 0.232 | tC2Q | RF | 3 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q |
4.841 | 0.249 | tNET | FF | 1 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/I0 |
5.396 | 0.555 | tINS | FF | 5 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/F |
5.967 | 0.572 | tNET | FF | 1 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/I3 |
6.516 | 0.549 | tINS | FR | 5 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/F |
6.693 | 0.176 | tNET | RR | 1 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/I3 |
7.146 | 0.453 | tINS | RF | 6 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/F |
8.052 | 0.906 | tNET | FF | 1 | R8C12[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n318_s0/I3 |
8.601 | 0.549 | tINS | FR | 2 | R8C12[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n318_s0/F |
8.603 | 0.003 | tNET | RR | 1 | R8C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s1/I2 |
9.120 | 0.517 | tINS | RF | 2 | R8C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s1/F |
9.692 | 0.572 | tNET | FF | 1 | R7C11[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s0/I2 |
10.063 | 0.371 | tINS | FF | 3 | R7C11[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s0/F |
10.238 | 0.175 | tNET | FF | 1 | R8C11[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s2/I1 |
10.700 | 0.462 | tINS | FR | 1 | R8C11[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s2/F |
10.844 | 0.144 | tNET | RR | 1 | R8C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R8C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s0/CLK |
41.361 | -0.035 | tSu | 1 | R8C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.456, 53.292%; route: 2.797, 43.131%; tC2Q: 0.232, 3.577% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path12
Path Summary:
Slack | 31.463 |
Data Arrival Time | 9.898 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/CLK |
4.591 | 0.232 | tC2Q | RF | 3 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q |
4.841 | 0.249 | tNET | FF | 1 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/I0 |
5.396 | 0.555 | tINS | FF | 5 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/F |
5.967 | 0.572 | tNET | FF | 1 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/I3 |
6.516 | 0.549 | tINS | FR | 5 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/F |
6.693 | 0.176 | tNET | RR | 1 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/I3 |
7.146 | 0.453 | tINS | RF | 6 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/F |
8.052 | 0.906 | tNET | FF | 1 | R8C12[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n318_s0/I3 |
8.601 | 0.549 | tINS | FR | 2 | R8C12[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n318_s0/F |
8.603 | 0.003 | tNET | RR | 1 | R8C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s1/I2 |
9.152 | 0.549 | tINS | RR | 2 | R8C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n347_s1/F |
9.328 | 0.176 | tNET | RR | 1 | R8C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n353_s8/I3 |
9.898 | 0.570 | tINS | RR | 1 | R8C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n353_s8/F |
9.898 | 0.000 | tNET | RR | 1 | R8C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R8C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s0/CLK |
41.361 | -0.035 | tSu | 1 | R8C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/sda_oen_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 3.225, 58.228%; route: 2.082, 37.584%; tC2Q: 0.232, 4.189% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path13
Path Summary:
Slack | 31.738 |
Data Arrival Time | 9.624 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_9_s2 |
To | i2c_config_m0/i2c_write_req_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 12 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/Q |
5.672 | 1.081 | tNET | FF | 1 | R16C8[0][B] | i2c_config_m0/i2c_master_top_m0/n203_s27/I1 |
6.227 | 0.555 | tINS | FF | 28 | R16C8[0][B] | i2c_config_m0/i2c_master_top_m0/n203_s27/F |
6.936 | 0.709 | tNET | FF | 1 | R14C11[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s77/I3 |
7.491 | 0.555 | tINS | FF | 4 | R14C11[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s77/F |
8.189 | 0.697 | tNET | FF | 1 | R16C6[1][B] | i2c_config_m0/n124_s14/I1 |
8.560 | 0.371 | tINS | FF | 3 | R16C6[1][B] | i2c_config_m0/n124_s14/F |
9.624 | 1.064 | tNET | FF | 1 | R16C6[2][A] | i2c_config_m0/i2c_write_req_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R16C6[2][A] | i2c_config_m0/i2c_write_req_s0/CLK |
41.361 | -0.035 | tSu | 1 | R16C6[2][A] | i2c_config_m0/i2c_write_req_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 1.481, 28.134%; route: 3.551, 67.459%; tC2Q: 0.232, 4.407% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path14
Path Summary:
Slack | 32.074 |
Data Arrival Time | 9.287 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_9_s2 |
To | i2c_config_m0/i2c_write_req_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 12 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/Q |
5.672 | 1.081 | tNET | FF | 1 | R16C8[0][B] | i2c_config_m0/i2c_master_top_m0/n203_s27/I1 |
6.227 | 0.555 | tINS | FF | 28 | R16C8[0][B] | i2c_config_m0/i2c_master_top_m0/n203_s27/F |
6.936 | 0.709 | tNET | FF | 1 | R14C11[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s77/I3 |
7.491 | 0.555 | tINS | FF | 4 | R14C11[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s77/F |
8.189 | 0.697 | tNET | FF | 1 | R16C6[1][B] | i2c_config_m0/n124_s14/I1 |
8.560 | 0.371 | tINS | FF | 3 | R16C6[1][B] | i2c_config_m0/n124_s14/F |
8.573 | 0.013 | tNET | FF | 1 | R16C6[0][B] | i2c_config_m0/i2c_write_req_s4/I1 |
9.143 | 0.570 | tINS | FR | 1 | R16C6[0][B] | i2c_config_m0/i2c_write_req_s4/F |
9.287 | 0.144 | tNET | RR | 1 | R16C6[2][A] | i2c_config_m0/i2c_write_req_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R16C6[2][A] | i2c_config_m0/i2c_write_req_s0/CLK |
41.361 | -0.035 | tSu | 1 | R16C6[2][A] | i2c_config_m0/i2c_write_req_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.051, 41.622%; route: 2.645, 53.670%; tC2Q: 0.232, 4.708% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path15
Path Summary:
Slack | 32.137 |
Data Arrival Time | 9.225 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_11_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/CLK |
4.590 | 0.231 | tC2Q | RR | 2 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/Q |
4.764 | 0.174 | tNET | RR | 1 | R8C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n153_s3/I3 |
5.319 | 0.555 | tINS | RF | 4 | R8C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n153_s3/F |
5.756 | 0.437 | tNET | FF | 1 | R9C8[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s3/I3 |
6.326 | 0.570 | tINS | FR | 4 | R9C8[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s3/F |
6.502 | 0.176 | tNET | RR | 1 | R9C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s3/I3 |
6.873 | 0.371 | tINS | RF | 3 | R9C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s3/F |
6.887 | 0.013 | tNET | FF | 1 | R9C9[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s1/I2 |
7.258 | 0.371 | tINS | FF | 3 | R9C9[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s1/F |
7.686 | 0.428 | tNET | FF | 1 | R8C8[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s0/I2 |
8.241 | 0.555 | tINS | FF | 15 | R8C8[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s0/F |
8.676 | 0.435 | tNET | FF | 1 | R9C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s2/I2 |
9.225 | 0.549 | tINS | FR | 1 | R9C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s2/F |
9.225 | 0.000 | tNET | RR | 1 | R9C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R9C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_11_s0/CLK |
41.361 | -0.035 | tSu | 1 | R9C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.971, 61.064%; route: 1.663, 34.188%; tC2Q: 0.231, 4.748% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path16
Path Summary:
Slack | 32.197 |
Data Arrival Time | 9.164 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/CLK |
4.590 | 0.231 | tC2Q | RR | 2 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/Q |
4.764 | 0.174 | tNET | RR | 1 | R8C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n153_s3/I3 |
5.319 | 0.555 | tINS | RF | 4 | R8C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n153_s3/F |
5.756 | 0.437 | tNET | FF | 1 | R9C8[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s3/I3 |
6.326 | 0.570 | tINS | FR | 4 | R9C8[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s3/F |
6.502 | 0.176 | tNET | RR | 1 | R9C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s3/I3 |
6.873 | 0.371 | tINS | RF | 3 | R9C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s3/F |
6.887 | 0.013 | tNET | FF | 1 | R9C9[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s1/I2 |
7.258 | 0.371 | tINS | FF | 3 | R9C9[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s1/F |
7.686 | 0.428 | tNET | FF | 1 | R8C8[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s0/I2 |
8.241 | 0.555 | tINS | FF | 15 | R8C8[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s0/F |
8.702 | 0.461 | tNET | FF | 1 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n155_s2/I0 |
9.164 | 0.462 | tINS | FR | 1 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n155_s2/F |
9.164 | 0.000 | tNET | RR | 1 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/CLK |
41.361 | -0.035 | tSu | 1 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.884, 60.026%; route: 1.690, 35.166%; tC2Q: 0.231, 4.808% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path17
Path Summary:
Slack | 32.197 |
Data Arrival Time | 9.164 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_4_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/CLK |
4.590 | 0.231 | tC2Q | RR | 2 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/Q |
4.764 | 0.174 | tNET | RR | 1 | R8C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n153_s3/I3 |
5.319 | 0.555 | tINS | RF | 4 | R8C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n153_s3/F |
5.756 | 0.437 | tNET | FF | 1 | R9C8[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s3/I3 |
6.326 | 0.570 | tINS | FR | 4 | R9C8[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s3/F |
6.502 | 0.176 | tNET | RR | 1 | R9C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s3/I3 |
6.873 | 0.371 | tINS | RF | 3 | R9C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s3/F |
6.887 | 0.013 | tNET | FF | 1 | R9C9[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s1/I2 |
7.258 | 0.371 | tINS | FF | 3 | R9C9[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s1/F |
7.686 | 0.428 | tNET | FF | 1 | R8C8[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s0/I2 |
8.241 | 0.555 | tINS | FF | 15 | R8C8[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s0/F |
8.702 | 0.461 | tNET | FF | 1 | R9C9[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n154_s2/I0 |
9.164 | 0.462 | tINS | FR | 1 | R9C9[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n154_s2/F |
9.164 | 0.000 | tNET | RR | 1 | R9C9[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R9C9[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_4_s0/CLK |
41.361 | -0.035 | tSu | 1 | R9C9[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.884, 60.026%; route: 1.690, 35.166%; tC2Q: 0.231, 4.808% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path18
Path Summary:
Slack | 32.197 |
Data Arrival Time | 9.164 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/CLK |
4.590 | 0.231 | tC2Q | RR | 2 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/Q |
4.764 | 0.174 | tNET | RR | 1 | R8C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n153_s3/I3 |
5.319 | 0.555 | tINS | RF | 4 | R8C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n153_s3/F |
5.756 | 0.437 | tNET | FF | 1 | R9C8[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s3/I3 |
6.326 | 0.570 | tINS | FR | 4 | R9C8[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s3/F |
6.502 | 0.176 | tNET | RR | 1 | R9C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s3/I3 |
6.873 | 0.371 | tINS | RF | 3 | R9C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s3/F |
6.887 | 0.013 | tNET | FF | 1 | R9C9[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s1/I2 |
7.258 | 0.371 | tINS | FF | 3 | R9C9[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s1/F |
7.686 | 0.428 | tNET | FF | 1 | R8C8[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s0/I2 |
8.241 | 0.555 | tINS | FF | 15 | R8C8[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s0/F |
8.702 | 0.461 | tNET | FF | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n149_s2/I0 |
9.164 | 0.462 | tINS | FR | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n149_s2/F |
9.164 | 0.000 | tNET | RR | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0/CLK |
41.361 | -0.035 | tSu | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.884, 60.026%; route: 1.690, 35.166%; tC2Q: 0.231, 4.808% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path19
Path Summary:
Slack | 32.218 |
Data Arrival Time | 9.143 |
Data Required Time | 41.361 |
From | i2c_config_m0/lut_index_9_s2 |
To | i2c_config_m0/state_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 12 | R16C7[0][B] | i2c_config_m0/lut_index_9_s2/Q |
5.672 | 1.081 | tNET | FF | 1 | R16C8[0][B] | i2c_config_m0/i2c_master_top_m0/n203_s27/I1 |
6.227 | 0.555 | tINS | FF | 28 | R16C8[0][B] | i2c_config_m0/i2c_master_top_m0/n203_s27/F |
6.936 | 0.709 | tNET | FF | 1 | R14C11[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s77/I3 |
7.491 | 0.555 | tINS | FF | 4 | R14C11[1][A] | i2c_config_m0/i2c_master_top_m0/n203_s77/F |
8.189 | 0.697 | tNET | FF | 1 | R16C6[1][B] | i2c_config_m0/n124_s14/I1 |
8.560 | 0.371 | tINS | FF | 3 | R16C6[1][B] | i2c_config_m0/n124_s14/F |
8.573 | 0.013 | tNET | FF | 1 | R16C6[0][A] | i2c_config_m0/n100_s7/I0 |
9.143 | 0.570 | tINS | FR | 1 | R16C6[0][A] | i2c_config_m0/n100_s7/F |
9.143 | 0.000 | tNET | RR | 1 | R16C6[0][A] | i2c_config_m0/state_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R16C6[0][A] | i2c_config_m0/state_0_s0/CLK |
41.361 | -0.035 | tSu | 1 | R16C6[0][A] | i2c_config_m0/state_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.051, 42.876%; route: 2.501, 52.274%; tC2Q: 0.232, 4.850% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path20
Path Summary:
Slack | 32.234 |
Data Arrival Time | 9.127 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_11_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/CLK |
4.591 | 0.232 | tC2Q | RF | 3 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q |
4.841 | 0.249 | tNET | FF | 1 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/I0 |
5.396 | 0.555 | tINS | FF | 5 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/F |
5.967 | 0.572 | tNET | FF | 1 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/I3 |
6.516 | 0.549 | tINS | FR | 5 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/F |
6.693 | 0.176 | tNET | RR | 1 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/I3 |
7.146 | 0.453 | tINS | RF | 6 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/F |
7.902 | 0.756 | tNET | FF | 1 | R8C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s0/I3 |
8.355 | 0.453 | tINS | FF | 2 | R8C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s0/F |
9.127 | 0.772 | tNET | FF | 1 | R9C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R9C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_11_s0/CLK |
41.361 | -0.035 | tSu | 1 | R9C12[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.010, 42.158%; route: 2.526, 52.976%; tC2Q: 0.232, 4.866% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path21
Path Summary:
Slack | 32.252 |
Data Arrival Time | 9.109 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_15_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/CLK |
4.591 | 0.232 | tC2Q | RF | 3 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q |
4.841 | 0.249 | tNET | FF | 1 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/I0 |
5.396 | 0.555 | tINS | FF | 5 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/F |
5.967 | 0.572 | tNET | FF | 1 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/I3 |
6.516 | 0.549 | tINS | FR | 5 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/F |
6.693 | 0.176 | tNET | RR | 1 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/I3 |
7.146 | 0.453 | tINS | RF | 6 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/F |
7.726 | 0.581 | tNET | FF | 1 | R7C13[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n322_s1/I3 |
8.097 | 0.371 | tINS | FF | 3 | R7C13[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n322_s1/F |
8.111 | 0.013 | tNET | FF | 1 | R7C13[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n324_s0/I3 |
8.564 | 0.453 | tINS | FF | 2 | R7C13[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n324_s0/F |
9.109 | 0.546 | tNET | FF | 1 | R7C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R7C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_15_s0/CLK |
41.361 | -0.035 | tSu | 1 | R7C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.381, 50.125%; route: 2.137, 44.991%; tC2Q: 0.232, 4.884% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path22
Path Summary:
Slack | 32.252 |
Data Arrival Time | 9.109 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_16_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/CLK |
4.591 | 0.232 | tC2Q | RF | 3 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q |
4.841 | 0.249 | tNET | FF | 1 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/I0 |
5.396 | 0.555 | tINS | FF | 5 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/F |
5.967 | 0.572 | tNET | FF | 1 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/I3 |
6.516 | 0.549 | tINS | FR | 5 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/F |
6.693 | 0.176 | tNET | RR | 1 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/I3 |
7.146 | 0.453 | tINS | RF | 6 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/F |
7.726 | 0.581 | tNET | FF | 1 | R7C13[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n322_s1/I3 |
8.097 | 0.371 | tINS | FF | 3 | R7C13[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n322_s1/F |
8.111 | 0.013 | tNET | FF | 1 | R7C13[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n326_s0/I3 |
8.564 | 0.453 | tINS | FF | 2 | R7C13[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n326_s0/F |
9.109 | 0.546 | tNET | FF | 1 | R7C12[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R7C12[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_16_s0/CLK |
41.361 | -0.035 | tSu | 1 | R7C12[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.381, 50.125%; route: 2.137, 44.991%; tC2Q: 0.232, 4.884% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path23
Path Summary:
Slack | 32.263 |
Data Arrival Time | 9.098 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_12_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/CLK |
4.591 | 0.232 | tC2Q | RF | 3 | R9C11[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_0_s0/Q |
4.841 | 0.249 | tNET | FF | 1 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/I0 |
5.396 | 0.555 | tINS | FF | 5 | R9C13[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n308_s1/F |
5.967 | 0.572 | tNET | FF | 1 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/I3 |
6.516 | 0.549 | tINS | FR | 5 | R8C12[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n310_s3/F |
6.693 | 0.176 | tNET | RR | 1 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/I3 |
7.146 | 0.453 | tINS | RF | 6 | R7C12[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n316_s1/F |
8.052 | 0.906 | tNET | FF | 1 | R8C12[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n318_s0/I3 |
8.569 | 0.517 | tINS | FF | 2 | R8C12[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n318_s0/F |
9.098 | 0.530 | tNET | FF | 1 | R8C12[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R8C12[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_12_s0/CLK |
41.361 | -0.035 | tSu | 1 | R8C12[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 5 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.074, 43.765%; route: 2.433, 51.339%; tC2Q: 0.232, 4.896% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path24
Path Summary:
Slack | 32.288 |
Data Arrival Time | 9.073 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_7_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/CLK |
4.590 | 0.231 | tC2Q | RR | 2 | R9C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_3_s0/Q |
4.764 | 0.174 | tNET | RR | 1 | R8C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n153_s3/I3 |
5.319 | 0.555 | tINS | RF | 4 | R8C9[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n153_s3/F |
5.756 | 0.437 | tNET | FF | 1 | R9C8[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s3/I3 |
6.326 | 0.570 | tINS | FR | 4 | R9C8[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s3/F |
6.502 | 0.176 | tNET | RR | 1 | R9C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s3/I3 |
6.873 | 0.371 | tINS | RF | 3 | R9C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n147_s3/F |
6.887 | 0.013 | tNET | FF | 1 | R9C9[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s1/I2 |
7.258 | 0.371 | tINS | FF | 3 | R9C9[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s1/F |
7.686 | 0.428 | tNET | FF | 1 | R8C8[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s0/I2 |
8.241 | 0.555 | tINS | FF | 15 | R8C8[2][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n111_s0/F |
8.702 | 0.461 | tNET | FF | 1 | R9C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n151_s2/I0 |
9.073 | 0.371 | tINS | FF | 1 | R9C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n151_s2/F |
9.073 | 0.000 | tNET | FF | 1 | R9C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R9C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_7_s0/CLK |
41.361 | -0.035 | tSu | 1 | R9C9[2][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.793, 59.254%; route: 1.690, 35.845%; tC2Q: 0.231, 4.901% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Path25
Path Summary:
Slack | 32.349 |
Data Arrival Time | 9.012 |
Data Required Time | 41.361 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_1_s2 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_3_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
4.359 | 2.271 | tNET | RR | 1 | R11C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_1_s2/CLK |
4.591 | 0.232 | tC2Q | RF | 6 | R11C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_1_s2/Q |
5.258 | 0.667 | tNET | FF | 1 | R9C9[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n336_s2/I1 |
5.629 | 0.371 | tINS | FF | 6 | R9C9[3][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n336_s2/F |
6.304 | 0.675 | tNET | FF | 1 | R11C12[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/n197_s10/I3 |
6.859 | 0.555 | tINS | FF | 6 | R11C12[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/n197_s10/F |
7.124 | 0.265 | tNET | FF | 1 | R11C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_1_s5/I2 |
7.495 | 0.371 | tINS | FF | 1 | R11C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_1_s5/F |
7.499 | 0.004 | tNET | FF | 1 | R11C10[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_1_s4/I2 |
7.870 | 0.371 | tINS | FF | 4 | R11C10[3][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_1_s4/F |
8.442 | 0.572 | tNET | FF | 1 | R11C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/n203_s10/I0 |
9.012 | 0.570 | tINS | FR | 1 | R11C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/n203_s10/F |
9.012 | 0.000 | tNET | RR | 1 | R11C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk | ||||
37.037 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
41.396 | 2.271 | tNET | RR | 1 | R11C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_3_s0/CLK |
41.361 | -0.035 | tSu | 1 | R11C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/core_cmd_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Arrival Data Path Delay | cell: 2.238, 48.101%; route: 2.183, 46.913%; tC2Q: 0.232, 4.986% |
Required Clock Path Delay | cell: 2.088, 47.897%; route: 2.271, 52.103% |
Hold Analysis Report
Report Command:report_timing -hold -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.425 |
Data Arrival Time | 3.340 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/CLK |
3.105 | 0.202 | tC2Q | RR | 17 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/Q |
3.108 | 0.002 | tNET | RR | 1 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n12_s3/I0 |
3.340 | 0.232 | tINS | RF | 1 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n12_s3/F |
3.340 | 0.000 | tNET | FF | 1 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/CLK |
2.914 | 0.011 | tHld | 1 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path2
Path Summary:
Slack | 0.425 |
Data Arrival Time | 3.340 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_6_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_6_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R9C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_6_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 2 | R9C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_6_s0/Q |
3.108 | 0.002 | tNET | RR | 1 | R9C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n152_s1/I3 |
3.340 | 0.232 | tINS | RF | 1 | R9C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n152_s1/F |
3.340 | 0.000 | tNET | FF | 1 | R9C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R9C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_6_s0/CLK |
2.914 | 0.011 | tHld | 1 | R9C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path3
Path Summary:
Slack | 0.425 |
Data Arrival Time | 3.340 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 2 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0/Q |
3.108 | 0.002 | tNET | RR | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n149_s2/I2 |
3.340 | 0.232 | tINS | RF | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n149_s2/F |
3.340 | 0.000 | tNET | FF | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0/CLK |
2.914 | 0.011 | tHld | 1 | R9C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path4
Path Summary:
Slack | 0.425 |
Data Arrival Time | 3.340 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 2 | R7C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0/Q |
3.108 | 0.002 | tNET | RR | 2 | R7C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n42_s/I1 |
3.340 | 0.232 | tINS | RF | 1 | R7C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n42_s/SUM |
3.340 | 0.000 | tNET | FF | 1 | R7C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0/CLK |
2.914 | 0.011 | tHld | 1 | R7C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path5
Path Summary:
Slack | 0.425 |
Data Arrival Time | 3.340 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_6_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_6_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_6_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 2 | R7C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_6_s0/Q |
3.108 | 0.002 | tNET | RR | 2 | R7C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n38_s/I1 |
3.340 | 0.232 | tINS | RF | 1 | R7C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n38_s/SUM |
3.340 | 0.000 | tNET | FF | 1 | R7C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_6_s0/CLK |
2.914 | 0.011 | tHld | 1 | R7C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path6
Path Summary:
Slack | 0.425 |
Data Arrival Time | 3.340 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_8_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_8_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C10[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_8_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 2 | R7C10[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_8_s0/Q |
3.108 | 0.002 | tNET | RR | 2 | R7C10[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n36_s/I1 |
3.340 | 0.232 | tINS | RF | 1 | R7C10[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n36_s/SUM |
3.340 | 0.000 | tNET | FF | 1 | R7C10[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C10[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_8_s0/CLK |
2.914 | 0.011 | tHld | 1 | R7C10[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path7
Path Summary:
Slack | 0.425 |
Data Arrival Time | 3.340 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_12_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_12_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_12_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 2 | R7C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_12_s0/Q |
3.108 | 0.002 | tNET | RR | 2 | R7C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n32_s/I1 |
3.340 | 0.232 | tINS | RF | 1 | R7C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n32_s/SUM |
3.340 | 0.000 | tNET | FF | 1 | R7C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_12_s0/CLK |
2.914 | 0.011 | tHld | 1 | R7C11[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path8
Path Summary:
Slack | 0.425 |
Data Arrival Time | 3.340 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_14_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_14_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C11[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_14_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 2 | R7C11[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_14_s0/Q |
3.108 | 0.002 | tNET | RR | 2 | R7C11[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n30_s/I1 |
3.340 | 0.232 | tINS | RF | 1 | R7C11[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n30_s/SUM |
3.340 | 0.000 | tNET | FF | 1 | R7C11[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C11[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_14_s0/CLK |
2.914 | 0.011 | tHld | 1 | R7C11[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path9
Path Summary:
Slack | 0.427 |
Data Arrival Time | 3.341 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_14_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_14_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_14_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 5 | R7C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_14_s0/Q |
3.109 | 0.004 | tNET | RR | 1 | R7C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n322_s0/I0 |
3.341 | 0.232 | tINS | RF | 1 | R7C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n322_s0/F |
3.341 | 0.000 | tNET | FF | 1 | R7C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_14_s0/CLK |
2.914 | 0.011 | tHld | 1 | R7C13[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path10
Path Summary:
Slack | 0.427 |
Data Arrival Time | 3.341 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_1_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R8C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_1_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 4 | R8C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_1_s0/Q |
3.109 | 0.004 | tNET | RR | 1 | R8C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n157_s1/I1 |
3.341 | 0.232 | tINS | RF | 1 | R8C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n157_s1/F |
3.341 | 0.000 | tNET | FF | 1 | R8C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R8C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_1_s0/CLK |
2.914 | 0.011 | tHld | 1 | R8C9[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path11
Path Summary:
Slack | 0.427 |
Data Arrival Time | 3.341 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_8_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_8_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R9C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_8_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 3 | R9C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_8_s0/Q |
3.109 | 0.004 | tNET | RR | 1 | R9C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s2/I3 |
3.341 | 0.232 | tINS | RF | 1 | R9C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n150_s2/F |
3.341 | 0.000 | tNET | FF | 1 | R9C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R9C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_8_s0/CLK |
2.914 | 0.011 | tHld | 1 | R9C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path12
Path Summary:
Slack | 0.427 |
Data Arrival Time | 3.341 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_12_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_12_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R8C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_12_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 3 | R8C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_12_s0/Q |
3.109 | 0.004 | tNET | RR | 1 | R8C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n146_s2/I1 |
3.341 | 0.232 | tINS | RF | 1 | R8C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n146_s2/F |
3.341 | 0.000 | tNET | FF | 1 | R8C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R8C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_12_s0/CLK |
2.914 | 0.011 | tHld | 1 | R8C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path13
Path Summary:
Slack | 0.427 |
Data Arrival Time | 3.341 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/dcnt_1_s3 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/dcnt_1_s3 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R11C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/dcnt_1_s3/CLK |
3.105 | 0.202 | tC2Q | RR | 3 | R11C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/dcnt_1_s3/Q |
3.109 | 0.004 | tNET | RR | 1 | R11C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/n67_s3/I0 |
3.341 | 0.232 | tINS | RF | 1 | R11C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/n67_s3/F |
3.341 | 0.000 | tNET | FF | 1 | R11C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/dcnt_1_s3/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R11C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/dcnt_1_s3/CLK |
2.914 | 0.011 | tHld | 1 | R11C8[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/dcnt_1_s3 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path14
Path Summary:
Slack | 0.428 |
Data Arrival Time | 3.342 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_0_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_0_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R8C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_0_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 5 | R8C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_0_s0/Q |
3.110 | 0.005 | tNET | RR | 1 | R8C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n158_s2/I0 |
3.342 | 0.232 | tINS | RF | 1 | R8C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n158_s2/F |
3.342 | 0.000 | tNET | FF | 1 | R8C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R8C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_0_s0/CLK |
2.914 | 0.011 | tHld | 1 | R8C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/filter_cnt_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path15
Path Summary:
Slack | 0.428 |
Data Arrival Time | 3.342 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/write_s5 |
To | i2c_config_m0/i2c_master_top_m0/write_s5 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R13C11[0][A] | i2c_config_m0/i2c_master_top_m0/write_s5/CLK |
3.105 | 0.202 | tC2Q | RR | 4 | R13C11[0][A] | i2c_config_m0/i2c_master_top_m0/write_s5/Q |
3.110 | 0.005 | tNET | RR | 1 | R13C11[0][A] | i2c_config_m0/i2c_master_top_m0/n81_s8/I1 |
3.342 | 0.232 | tINS | RF | 1 | R13C11[0][A] | i2c_config_m0/i2c_master_top_m0/n81_s8/F |
3.342 | 0.000 | tNET | FF | 1 | R13C11[0][A] | i2c_config_m0/i2c_master_top_m0/write_s5/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R13C11[0][A] | i2c_config_m0/i2c_master_top_m0/write_s5/CLK |
2.914 | 0.011 | tHld | 1 | R13C11[0][A] | i2c_config_m0/i2c_master_top_m0/write_s5 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 52.861%; route: 0.005, 1.114%; tC2Q: 0.202, 46.025% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path16
Path Summary:
Slack | 0.429 |
Data Arrival Time | 3.343 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_3_s0 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_3_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R8C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_3_s0/CLK |
3.105 | 0.202 | tC2Q | RR | 7 | R8C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_3_s0/Q |
3.111 | 0.006 | tNET | RR | 1 | R8C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n300_s0/I0 |
3.343 | 0.232 | tINS | RF | 1 | R8C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/n300_s0/F |
3.343 | 0.000 | tNET | FF | 1 | R8C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R8C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_3_s0/CLK |
2.914 | 0.011 | tHld | 1 | R8C10[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/c_state_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path17
Path Summary:
Slack | 0.429 |
Data Arrival Time | 3.343 |
Data Required Time | 2.914 |
From | i2c_config_m0/lut_index_0_s4 |
To | i2c_config_m0/lut_index_0_s4 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R17C7[1][A] | i2c_config_m0/lut_index_0_s4/CLK |
3.105 | 0.202 | tC2Q | RR | 102 | R17C7[1][A] | i2c_config_m0/lut_index_0_s4/Q |
3.111 | 0.006 | tNET | RR | 1 | R17C7[1][A] | i2c_config_m0/n81_s5/I0 |
3.343 | 0.232 | tINS | RF | 1 | R17C7[1][A] | i2c_config_m0/n81_s5/F |
3.343 | 0.000 | tNET | FF | 1 | R17C7[1][A] | i2c_config_m0/lut_index_0_s4/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R17C7[1][A] | i2c_config_m0/lut_index_0_s4/CLK |
2.914 | 0.011 | tHld | 1 | R17C7[1][A] | i2c_config_m0/lut_index_0_s4 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path18
Path Summary:
Slack | 0.429 |
Data Arrival Time | 3.343 |
Data Required Time | 2.914 |
From | i2c_config_m0/lut_index_8_s2 |
To | i2c_config_m0/lut_index_8_s2 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R16C7[0][A] | i2c_config_m0/lut_index_8_s2/CLK |
3.105 | 0.202 | tC2Q | RR | 13 | R16C7[0][A] | i2c_config_m0/lut_index_8_s2/Q |
3.111 | 0.006 | tNET | RR | 1 | R16C7[0][A] | i2c_config_m0/n73_s1/I2 |
3.343 | 0.232 | tINS | RF | 1 | R16C7[0][A] | i2c_config_m0/n73_s1/F |
3.343 | 0.000 | tNET | FF | 1 | R16C7[0][A] | i2c_config_m0/lut_index_8_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R16C7[0][A] | i2c_config_m0/lut_index_8_s2/CLK |
2.914 | 0.011 | tHld | 1 | R16C7[0][A] | i2c_config_m0/lut_index_8_s2 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 52.714%; route: 0.006, 1.389%; tC2Q: 0.202, 45.898% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path19
Path Summary:
Slack | 0.430 |
Data Arrival Time | 3.345 |
Data Required Time | 2.914 |
From | i2c_config_m0/lut_index_5_s2 |
To | i2c_config_m0/lut_index_5_s2 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R17C6[1][A] | i2c_config_m0/lut_index_5_s2/CLK |
3.105 | 0.202 | tC2Q | RR | 94 | R17C6[1][A] | i2c_config_m0/lut_index_5_s2/Q |
3.113 | 0.007 | tNET | RR | 1 | R17C6[1][A] | i2c_config_m0/n76_s1/I2 |
3.345 | 0.232 | tINS | RF | 1 | R17C6[1][A] | i2c_config_m0/n76_s1/F |
3.345 | 0.000 | tNET | FF | 1 | R17C6[1][A] | i2c_config_m0/lut_index_5_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R17C6[1][A] | i2c_config_m0/lut_index_5_s2/CLK |
2.914 | 0.011 | tHld | 1 | R17C6[1][A] | i2c_config_m0/lut_index_5_s2 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 52.568%; route: 0.007, 1.662%; tC2Q: 0.202, 45.770% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path20
Path Summary:
Slack | 0.430 |
Data Arrival Time | 3.345 |
Data Required Time | 2.914 |
From | i2c_config_m0/lut_index_7_s2 |
To | i2c_config_m0/lut_index_7_s2 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R16C7[1][A] | i2c_config_m0/lut_index_7_s2/CLK |
3.105 | 0.202 | tC2Q | RR | 18 | R16C7[1][A] | i2c_config_m0/lut_index_7_s2/Q |
3.113 | 0.007 | tNET | RR | 1 | R16C7[1][A] | i2c_config_m0/n74_s4/I0 |
3.345 | 0.232 | tINS | RF | 1 | R16C7[1][A] | i2c_config_m0/n74_s4/F |
3.345 | 0.000 | tNET | FF | 1 | R16C7[1][A] | i2c_config_m0/lut_index_7_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R16C7[1][A] | i2c_config_m0/lut_index_7_s2/CLK |
2.914 | 0.011 | tHld | 1 | R16C7[1][A] | i2c_config_m0/lut_index_7_s2 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 52.568%; route: 0.007, 1.662%; tC2Q: 0.202, 45.770% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path21
Path Summary:
Slack | 0.432 |
Data Arrival Time | 3.346 |
Data Required Time | 2.914 |
From | i2c_config_m0/lut_index_3_s2 |
To | i2c_config_m0/lut_index_3_s2 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R17C7[0][A] | i2c_config_m0/lut_index_3_s2/CLK |
3.105 | 0.202 | tC2Q | RR | 118 | R17C7[0][A] | i2c_config_m0/lut_index_3_s2/Q |
3.114 | 0.009 | tNET | RR | 1 | R17C7[0][A] | i2c_config_m0/n78_s1/I2 |
3.346 | 0.232 | tINS | RF | 1 | R17C7[0][A] | i2c_config_m0/n78_s1/F |
3.346 | 0.000 | tNET | FF | 1 | R17C7[0][A] | i2c_config_m0/lut_index_3_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R17C7[0][A] | i2c_config_m0/lut_index_3_s2/CLK |
2.914 | 0.011 | tHld | 1 | R17C7[0][A] | i2c_config_m0/lut_index_3_s2 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 52.423%; route: 0.009, 1.933%; tC2Q: 0.202, 45.644% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path22
Path Summary:
Slack | 0.434 |
Data Arrival Time | 3.348 |
Data Required Time | 2.914 |
From | i2c_config_m0/lut_index_6_s2 |
To | i2c_config_m0/lut_index_6_s2 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R17C6[0][A] | i2c_config_m0/lut_index_6_s2/CLK |
3.105 | 0.202 | tC2Q | RR | 42 | R17C6[0][A] | i2c_config_m0/lut_index_6_s2/Q |
3.116 | 0.011 | tNET | RR | 1 | R17C6[0][A] | i2c_config_m0/n75_s1/I2 |
3.348 | 0.232 | tINS | RF | 1 | R17C6[0][A] | i2c_config_m0/n75_s1/F |
3.348 | 0.000 | tNET | FF | 1 | R17C6[0][A] | i2c_config_m0/lut_index_6_s2/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R17C6[0][A] | i2c_config_m0/lut_index_6_s2/CLK |
2.914 | 0.011 | tHld | 1 | R17C6[0][A] | i2c_config_m0/lut_index_6_s2 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.232, 52.135%; route: 0.011, 2.472%; tC2Q: 0.202, 45.393% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path23
Path Summary:
Slack | 0.460 |
Data Arrival Time | 3.374 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_1_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/CLK |
3.105 | 0.202 | tC2Q | RR | 17 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/Q |
3.374 | 0.269 | tNET | RR | 1 | R7C9[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_1_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C9[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_1_s0/CLK |
2.914 | 0.011 | tHld | 1 | R7C9[0][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.092%; tC2Q: 0.202, 42.908% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path24
Path Summary:
Slack | 0.460 |
Data Arrival Time | 3.374 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/CLK |
3.105 | 0.202 | tC2Q | RR | 17 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/Q |
3.374 | 0.269 | tNET | RR | 1 | R7C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0/CLK |
2.914 | 0.011 | tHld | 1 | R7C9[1][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.092%; tC2Q: 0.202, 42.908% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Path25
Path Summary:
Slack | 0.460 |
Data Arrival Time | 3.374 |
Data Required Time | 2.914 |
From | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5 |
To | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_3_s0 |
Launch Clk | clk:[R] |
Latch Clk | clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/CLK |
3.105 | 0.202 | tC2Q | RR | 17 | R7C8[0][A] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/slave_wait_s5/Q |
3.374 | 0.269 | tNET | RR | 1 | R7C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_3_s0/CE |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 127 | IOT27[A] | clk_ibuf/O |
2.903 | 1.511 | tNET | RR | 1 | R7C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_3_s0/CLK |
2.914 | 0.011 | tHld | 1 | R7C9[1][B] | i2c_config_m0/i2c_master_top_m0/byte_controller/bit_controller/cnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.269, 57.092%; tC2Q: 0.202, 42.908% |
Required Clock Path Delay | cell: 1.392, 47.946%; route: 1.511, 52.054% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -4.270 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.078 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 10 | R56C45 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | R56C45 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs | |||
1252.078 | -0.498 | tSu | 1 | R56C45 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[1].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path2
Path Summary:
Slack | -4.270 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.078 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 10 | R56C12 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | R56C12 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs | |||
1252.078 | -0.498 | tSu | 1 | R56C12 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/data_lane_gen[0].u_ddr3_phy_data_lane/u_ddr3_phy_data_io/u_dqs |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path3
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB27[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB27[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB27[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/u_ck_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path4
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[22].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path5
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB9[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[21].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path6
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB26[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB26[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB26[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[20].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path7
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOL29[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOL29[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOL29[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[19].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path8
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB4[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB4[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB4[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[18].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path9
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOL40[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOL40[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOL40[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[17].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path10
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB36[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB36[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB36[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[16].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path11
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOL31[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOL31[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOL31[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[15].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path12
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB7[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB7[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB7[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[14].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path13
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOL38[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOL38[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOL38[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[13].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path14
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB8[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB8[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB8[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[12].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path15
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOL53[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOL53[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOL53[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[11].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path16
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOL47[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOL47[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOL47[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[10].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path17
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOL35[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[9].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path18
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB3[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB3[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB3[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[8].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path19
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB2[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB2[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB2[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[7].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path20
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOL45[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOL45[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOL45[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[6].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path21
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[5].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB48[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[5].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB48[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[5].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[5].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB48[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[5].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path22
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB34[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB34[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB34[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[4].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path23
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[3].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB30[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[3].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB30[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[3].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[3].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB30[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[3].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path24
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB54[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB54[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB54[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[2].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Path25
Path Summary:
Slack | -3.925 |
Data Arrival Time | 1256.348 |
Data Required Time | 1252.423 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0 |
To | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[1].u_cmd_gen |
Launch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1249.999 | 1249.999 | active clock edge time | ||||
1249.999 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
1252.218 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
1254.490 | 2.271 | tNET | RR | 1 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/CLK |
1254.722 | 0.232 | tC2Q | RF | 1189 | R33C37[2][B] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/ddr_rsti_reg_2_s0/Q |
1256.348 | 1.626 | tNET | FF | 2 | IOB52[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[1].u_cmd_gen/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
1250.000 | 1250.000 | active clock edge time | ||||
1250.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
1250.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
1252.611 | 2.271 | tNET | RR | 1 | IOB52[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[1].u_cmd_gen/PCLK |
1252.576 | -0.035 | tUnc | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[1].u_cmd_gen | |||
1252.423 | -0.153 | tSu | 1 | IOB52[A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_wd/u_ddr3_phy_cmd_lane/u_ddr3_phy_cmd_io/cmd_oserdes_gen[1].u_cmd_gen |
Path Statistics:
Clock Skew | -1.880 |
Setup Relationship | 0.001 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 1.626, 87.517%; tC2Q: 0.232, 12.483% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 2.271, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_0_s3 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R40C42[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_0_s3/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R40C42[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_0_s3/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_0_s3 | |||
2503.774 | 0.011 | tHld | 1 | R40C42[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/allian_cnt_0_s3 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path2
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R38C45[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R38C45[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0 | |||
2503.774 | 0.011 | tHld | 1 | R38C45[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_de_16b_d1_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path3
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R45C39[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R45C39[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0 | |||
2503.774 | 0.011 | tHld | 1 | R45C39[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_0_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path4
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_1_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R45C39[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R45C39[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_1_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_1_s0 | |||
2503.774 | 0.011 | tHld | 1 | R45C39[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_1_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path5
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R44C42[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R44C42[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0 | |||
2503.774 | 0.011 | tHld | 1 | R44C42[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_2_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path6
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R47C41[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R47C41[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0 | |||
2503.774 | 0.011 | tHld | 1 | R47C41[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_3_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path7
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R44C39[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R44C39[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0 | |||
2503.774 | 0.011 | tHld | 1 | R44C39[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_4_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path8
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R47C42[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R47C42[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0 | |||
2503.774 | 0.011 | tHld | 1 | R47C42[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_5_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path9
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R45C38[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R45C38[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0 | |||
2503.774 | 0.011 | tHld | 1 | R45C38[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_6_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path10
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_7_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R45C39[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R45C39[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_7_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_7_s0 | |||
2503.774 | 0.011 | tHld | 1 | R45C39[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_7_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path11
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R45C41[2][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R45C41[2][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0 | |||
2503.774 | 0.011 | tHld | 1 | R45C41[2][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_8_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path12
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R47C42[2][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R47C42[2][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0 | |||
2503.774 | 0.011 | tHld | 1 | R47C42[2][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_9_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path13
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R44C41[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R44C41[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0 | |||
2503.774 | 0.011 | tHld | 1 | R44C41[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_10_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path14
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R44C42[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R44C42[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0 | |||
2503.774 | 0.011 | tHld | 1 | R44C42[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_11_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path15
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_12_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R45C41[0][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_12_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R45C41[0][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_12_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_12_s0 | |||
2503.774 | 0.011 | tHld | 1 | R45C41[0][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_12_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path16
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_13_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R44C41[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_13_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R44C41[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_13_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_13_s0 | |||
2503.774 | 0.011 | tHld | 1 | R44C41[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_13_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path17
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R45C40[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R45C40[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0 | |||
2503.774 | 0.011 | tHld | 1 | R45C40[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_14_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path18
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_15_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R45C40[0][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_15_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R45C40[0][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_15_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_15_s0 | |||
2503.774 | 0.011 | tHld | 1 | R45C40[0][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_16b_15_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path19
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_den_16b_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R26C38[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_den_16b_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R26C38[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_den_16b_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_den_16b_s0 | |||
2503.774 | 0.011 | tHld | 1 | R26C38[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_den_16b_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path20
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R47C43[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R47C43[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0 | |||
2503.774 | 0.011 | tHld | 1 | R47C43[1][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_16_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path21
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R47C39[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R47C39[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0 | |||
2503.774 | 0.011 | tHld | 1 | R47C39[2][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_17_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path22
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R45C44[0][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R45C44[0][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0 | |||
2503.774 | 0.011 | tHld | 1 | R45C44[0][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_18_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path23
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R45C43[2][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R45C43[2][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0 | |||
2503.774 | 0.011 | tHld | 1 | R45C43[2][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_19_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path24
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R44C41[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R44C41[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0 | |||
2503.774 | 0.011 | tHld | 1 | R44C41[0][B] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_20_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Path25
Path Summary:
Slack | -0.991 |
Data Arrival Time | 2502.786 |
Data Required Time | 2503.778 |
From | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0 |
To | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0 |
Launch Clk | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk:[R] |
Latch Clk | u_clkdiv/CLKOUT.default_gen_clk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2500.000 | 2500.000 | active clock edge time | ||||
2500.000 | 0.000 | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT.default_gen_clk | ||||
2500.339 | 0.339 | tCL | RR | 1657 | BOTTOMSIDE[0] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/fclkdiv/CLKOUT |
2501.851 | 1.511 | tNET | RR | 1 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/CLK |
2502.052 | 0.202 | tC2Q | RR | 586 | R35C31[0][A] | DDR3_Memory_Interface_Top_inst/gw3_top/i4/u_ddr_phy_init/ddr_init_complete_d_3_s0/Q |
2502.786 | 0.734 | tNET | RR | 1 | R47C42[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
2499.998 | 2499.998 | active clock edge time | ||||
2499.998 | 0.000 | u_clkdiv/CLKOUT.default_gen_clk | ||||
2502.217 | 2.219 | tCL | RR | 276 | TOPSIDE[0] | u_clkdiv/CLKOUT |
2503.728 | 1.511 | tNET | RR | 1 | R47C42[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0/CLK |
2503.763 | 0.035 | tUnc | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0 | |||
2503.774 | 0.011 | tHld | 1 | R47C42[1][A] | Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/u_dma_32b_16b/dma_d_32b_21_s0 |
Path Statistics:
Clock Skew | 1.880 |
Hold Relationship | -0.002 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.734, 78.412%; tC2Q: 0.202, 21.588% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.511, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 1.893 |
Actual Width: | 2.893 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cmos_pclk |
Objects: | cmos_8_16bit_m0/pdata_i_d0_6_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cmos_pclk | ||
5.000 | 0.000 | tCL | FF | cmos_pclk_ibuf/I |
7.314 | 2.314 | tINS | FF | cmos_pclk_ibuf/O |
10.705 | 3.391 | tNET | FF | cmos_8_16bit_m0/pdata_i_d0_6_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cmos_pclk | ||
10.000 | 0.000 | tCL | RR | cmos_pclk_ibuf/I |
11.392 | 1.392 | tINS | RR | cmos_pclk_ibuf/O |
13.598 | 2.206 | tNET | RR | cmos_8_16bit_m0/pdata_i_d0_6_s0/CLK |
MPW2
MPW Summary:
Slack: | 1.893 |
Actual Width: | 2.893 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cmos_pclk |
Objects: | cmos_8_16bit_m0/pdata_i_d0_5_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cmos_pclk | ||
5.000 | 0.000 | tCL | FF | cmos_pclk_ibuf/I |
7.314 | 2.314 | tINS | FF | cmos_pclk_ibuf/O |
10.705 | 3.391 | tNET | FF | cmos_8_16bit_m0/pdata_i_d0_5_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cmos_pclk | ||
10.000 | 0.000 | tCL | RR | cmos_pclk_ibuf/I |
11.392 | 1.392 | tINS | RR | cmos_pclk_ibuf/O |
13.598 | 2.206 | tNET | RR | cmos_8_16bit_m0/pdata_i_d0_5_s0/CLK |
MPW3
MPW Summary:
Slack: | 1.893 |
Actual Width: | 2.893 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cmos_pclk |
Objects: | cmos_8_16bit_m0/pdata_i_d0_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cmos_pclk | ||
5.000 | 0.000 | tCL | FF | cmos_pclk_ibuf/I |
7.314 | 2.314 | tINS | FF | cmos_pclk_ibuf/O |
10.705 | 3.391 | tNET | FF | cmos_8_16bit_m0/pdata_i_d0_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cmos_pclk | ||
10.000 | 0.000 | tCL | RR | cmos_pclk_ibuf/I |
11.392 | 1.392 | tINS | RR | cmos_pclk_ibuf/O |
13.598 | 2.206 | tNET | RR | cmos_8_16bit_m0/pdata_i_d0_4_s0/CLK |
MPW4
MPW Summary:
Slack: | 1.893 |
Actual Width: | 2.893 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cmos_pclk |
Objects: | cmos_8_16bit_m0/pdata_i_d0_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cmos_pclk | ||
5.000 | 0.000 | tCL | FF | cmos_pclk_ibuf/I |
7.314 | 2.314 | tINS | FF | cmos_pclk_ibuf/O |
10.705 | 3.391 | tNET | FF | cmos_8_16bit_m0/pdata_i_d0_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cmos_pclk | ||
10.000 | 0.000 | tCL | RR | cmos_pclk_ibuf/I |
11.392 | 1.392 | tINS | RR | cmos_pclk_ibuf/O |
13.598 | 2.206 | tNET | RR | cmos_8_16bit_m0/pdata_i_d0_3_s0/CLK |
MPW5
MPW Summary:
Slack: | 1.893 |
Actual Width: | 2.893 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cmos_pclk |
Objects: | cmos_8_16bit_m0/pdata_i_d0_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cmos_pclk | ||
5.000 | 0.000 | tCL | FF | cmos_pclk_ibuf/I |
7.314 | 2.314 | tINS | FF | cmos_pclk_ibuf/O |
10.705 | 3.391 | tNET | FF | cmos_8_16bit_m0/pdata_i_d0_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cmos_pclk | ||
10.000 | 0.000 | tCL | RR | cmos_pclk_ibuf/I |
11.392 | 1.392 | tINS | RR | cmos_pclk_ibuf/O |
13.598 | 2.206 | tNET | RR | cmos_8_16bit_m0/pdata_i_d0_2_s0/CLK |
MPW6
MPW Summary:
Slack: | 1.893 |
Actual Width: | 2.893 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cmos_pclk |
Objects: | cmos_8_16bit_m0/pdata_o_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cmos_pclk | ||
5.000 | 0.000 | tCL | FF | cmos_pclk_ibuf/I |
7.314 | 2.314 | tINS | FF | cmos_pclk_ibuf/O |
10.705 | 3.391 | tNET | FF | cmos_8_16bit_m0/pdata_o_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cmos_pclk | ||
10.000 | 0.000 | tCL | RR | cmos_pclk_ibuf/I |
11.392 | 1.392 | tINS | RR | cmos_pclk_ibuf/O |
13.598 | 2.206 | tNET | RR | cmos_8_16bit_m0/pdata_o_7_s0/CLK |
MPW7
MPW Summary:
Slack: | 1.893 |
Actual Width: | 2.893 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cmos_pclk |
Objects: | cmos_8_16bit_m0/pdata_i_d0_7_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cmos_pclk | ||
5.000 | 0.000 | tCL | FF | cmos_pclk_ibuf/I |
7.314 | 2.314 | tINS | FF | cmos_pclk_ibuf/O |
10.705 | 3.391 | tNET | FF | cmos_8_16bit_m0/pdata_i_d0_7_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cmos_pclk | ||
10.000 | 0.000 | tCL | RR | cmos_pclk_ibuf/I |
11.392 | 1.392 | tINS | RR | cmos_pclk_ibuf/O |
13.598 | 2.206 | tNET | RR | cmos_8_16bit_m0/pdata_i_d0_7_s0/CLK |
MPW8
MPW Summary:
Slack: | 1.893 |
Actual Width: | 2.893 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cmos_pclk |
Objects: | cmos_8_16bit_m0/x_cnt_s1 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cmos_pclk | ||
5.000 | 0.000 | tCL | FF | cmos_pclk_ibuf/I |
7.314 | 2.314 | tINS | FF | cmos_pclk_ibuf/O |
10.705 | 3.391 | tNET | FF | cmos_8_16bit_m0/x_cnt_s1/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cmos_pclk | ||
10.000 | 0.000 | tCL | RR | cmos_pclk_ibuf/I |
11.392 | 1.392 | tINS | RR | cmos_pclk_ibuf/O |
13.598 | 2.206 | tNET | RR | cmos_8_16bit_m0/x_cnt_s1/CLK |
MPW9
MPW Summary:
Slack: | 1.893 |
Actual Width: | 2.893 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cmos_pclk |
Objects: | cmos_8_16bit_m0/pdata_o_6_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cmos_pclk | ||
5.000 | 0.000 | tCL | FF | cmos_pclk_ibuf/I |
7.314 | 2.314 | tINS | FF | cmos_pclk_ibuf/O |
10.705 | 3.391 | tNET | FF | cmos_8_16bit_m0/pdata_o_6_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cmos_pclk | ||
10.000 | 0.000 | tCL | RR | cmos_pclk_ibuf/I |
11.392 | 1.392 | tINS | RR | cmos_pclk_ibuf/O |
13.598 | 2.206 | tNET | RR | cmos_8_16bit_m0/pdata_o_6_s0/CLK |
MPW10
MPW Summary:
Slack: | 1.893 |
Actual Width: | 2.893 |
Required Width: | 1.000 |
Type: | Low Pulse Width |
Clock: | cmos_pclk |
Objects: | cmos_8_16bit_m0/pdata_o_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | cmos_pclk | ||
5.000 | 0.000 | tCL | FF | cmos_pclk_ibuf/I |
7.314 | 2.314 | tINS | FF | cmos_pclk_ibuf/O |
10.705 | 3.391 | tNET | FF | cmos_8_16bit_m0/pdata_o_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
10.000 | 0.000 | active clock edge time | ||
10.000 | 0.000 | cmos_pclk | ||
10.000 | 0.000 | tCL | RR | cmos_pclk_ibuf/I |
11.392 | 1.392 | tINS | RR | cmos_pclk_ibuf/O |
13.598 | 2.206 | tNET | RR | cmos_8_16bit_m0/pdata_o_3_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
1657 | dma_clk | -2.754 | 2.274 |
1189 | ddr_rst | -5.109 | 1.869 |
987 | cmos_16bit_clk | -2.283 | 3.390 |
798 | cmos_xclk_d | -9.106 | 2.442 |
792 | prev2_vsync | 39.956 | 1.626 |
784 | n7436_4 | -5.695 | 1.329 |
586 | state_led_d_9[0] | 0.228 | 1.606 |
400 | dvi_y[4] | 5.942 | 1.628 |
276 | video_clk | -5.329 | 2.274 |
196 | n4684_11 | 5.942 | 2.416 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R43C10 | 93.06% |
R16C33 | 91.67% |
R16C34 | 90.28% |
R17C7 | 90.28% |
R22C33 | 88.89% |
R45C9 | 88.89% |
R31C47 | 88.89% |
R21C26 | 87.50% |
R22C29 | 87.50% |
R22C30 | 87.50% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk -period 37.037 [get_ports {clk}] -add |
TC_CLOCK | Actived | create_clock -name cmos_pclk -period 10 [get_ports {cmos_pclk}] -add |
TC_CLOCK | Actived | create_clock -name cmos_vsync -period 1000 [get_ports {cmos_vsync}] -add |
TC_CLOCK | Actived | create_clock -name mem_clk -period 2.5 -waveform {0 1.25} [get_nets {memory_clk}] |
TC_REPORT_TIMING | Actived | report_timing -hold -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1 |
TC_REPORT_TIMING | Actived | report_timing -setup -from_clock [get_clocks {clk*}] -to_clock [get_clocks {clk*}] -max_paths 25 -max_common_paths 1 |