PnR Messages

Report Title PnR Report
Design File H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\impl\gwsynthesis\top.vg
Physical Constraints File H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\top.cst
Timing Constraints File H:\git\TangPrimer20K_LUT-Network\primer20k\OV5640_HDMI1024_DDR3\src\lcd.sdc
Tool Version V1.9.9.01 (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Tue Nov 19 02:11:06 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s Placement Phase 1: CPU time = 0h 0m 0.712s, Elapsed time = 0h 0m 0.712s Placement Phase 2: CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s Placement Phase 3: CPU time = 0h 0m 8s, Elapsed time = 0h 0m 8s Total Placement: CPU time = 0h 0m 18s, Elapsed time = 0h 0m 18s Running routing: Routing Phase 0: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.007s Routing Phase 1: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s Routing Phase 2: CPU time = 0h 0m 18s, Elapsed time = 0h 0m 18s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 22s, Elapsed time = 0h 0m 22s Generate output files: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s
Total Time and Memory Usage CPU time = 0h 0m 44s, Elapsed time = 0h 0m 44s, Peak memory usage = 486MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 5732/20736 28%
    --LUT,ALU,ROM16 5030(4692 LUT, 338 ALU, 0 ROM16) -
    --SSRAM(RAM16) 117 -
Register 3660/16173 23%
    --Logic Register as Latch 0/15552 0%
    --Logic Register as FF 3657/15552 24%
    --I/O Register as Latch 0/621 0%
    --I/O Register as FF 3/621 <1%
CLS 4329/10368 42%
I/O Port 78 -
I/O Buf 71 -
    --Input Buf 13 -
    --Output Buf 38 -
    --Inout Buf 20 -
IOLOGIC 16 IDES8_MEM
24 OSER8
20 OSER8_MEM
4 OSER10
40 IODELAY
62%
BSRAM 1 SDPB
15 SDPX9B
35%
DSP 00%
PLL 3/4 75%
DCS 0/8 0%
DQCE 0/24 0%
OSC 0/1 0%
CLKDIV 2/8 25%
DLLDLY 0/8 0%
DQS 2/9 23%
DHCEN 1/16 7%

I/O Bank Usage Summary:

I/O Bank Usage
bank 0 15/29(51%)
bank 1 9/20(45%)
bank 2 4/20(20%)
bank 3 1/32(3%)
bank 4 19/36(52%)
bank 5 20/36(55%)
bank 6 10/18(55%)
bank 7 0/16(0%)

Global Clock Usage Summary:

Global Clock Usage
PRIMARY 8/8(100%)
LW 8/8(100%)
GCLK_PIN 5/8(63%)
PLL 3/4(75%)
CLKDIV 2/8(25%)
DLLDLY 0/8(0%)

Global Clock Signals:

Signal Global Clock Location
clk_d PRIMARY TR TL BL
cmos_pclk_d PRIMARY TR
video_clk PRIMARY TR TL BR BL
cmos_xclk_d PRIMARY TR TL
cmos_16bit_clk PRIMARY TR TL BR
dma_clk PRIMARY TR TL BR BL
serial_clk PRIMARY TL
Pout_vs_dn[4] PRIMARY TR TL
n7436_4 LW -
hdmi4_rst_n LW -
prev2_vsync LW -
state_led_d[1] LW -
state_led_d_9[0] LW -
Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_write_ctrl/fifo_write_inst/reset_r[1] LW -
Video_Frame_Buffer_Top_inst/vfb_ddr3_wrapper_inst/u0_dma_frame_buffer/u_dma_read_ctrl/fifo_read_inst/reset_r[1] LW -
DDR3_Memory_Interface_Top_inst/gw3_top/ddr_rst LW -
memory_clk HCLK BOTTOM[0] LEFT[0]
serial_clk HCLK TOP[0]

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk H11/0 Y in IOT27[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
rst_n C7/6 Y in IOL40[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.5
cmos_vsync G15/0 Y in IOT13[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
cmos_href G14/0 Y in IOT13[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
cmos_pclk F13/0 Y in IOT8[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
cmos_db[0] T12/2 Y in IOR17[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
cmos_db[1] T11/2 Y in IOR24[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
cmos_db[2] P11/2 Y in IOR24[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
cmos_db[3] R11/2 Y in IOR17[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
cmos_db[4] M15/1 Y in IOT40[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
cmos_db[5] M14/1 Y in IOT40[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
cmos_db[6] J16/0 Y in IOT22[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
cmos_db[7] J14/0 Y in IOT22[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
cmos_xclk G12/0 Y out IOT8[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
cmos_rst_n L13/1 Y out IOT38[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
cmos_pwdn C10/3 Y out IOR39[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
state_led[0] L16/1 Y out IOT34[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
state_led[1] L14/1 Y out IOT34[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
state_led[2] N14/1 Y out IOT52[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
state_led[3] N16/1 Y out IOT52[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
ddr_addr[0] F7/6 Y out IOL45[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
ddr_addr[1] A4/5 Y out IOB2[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_addr[2] D6/5 Y out IOB3[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_addr[3] F8/6 Y out IOL35[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
ddr_addr[4] C4/6 Y out IOL47[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
ddr_addr[5] E6/6 Y out IOL53[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
ddr_addr[6] B1/5 Y out IOB8[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_addr[7] D8/6 Y out IOL38[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
ddr_addr[8] A5/5 Y out IOB7[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_addr[9] F9/6 Y out IOL31[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
ddr_addr[10] K3/4 Y out IOB36[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_addr[11] B7/6 Y out IOL40[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
ddr_addr[12] A3/5 Y out IOB4[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_addr[13] C8/6 Y out IOL29[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
ddr_bank[0] H4/5 Y out IOB26[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_bank[1] D3/5 Y out IOB9[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_bank[2] H5/4 Y out IOB35[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_cs P5/4 Y out IOB50[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_ras R4/4 Y out IOB52[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_cas R6/4 Y out IOB54[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_we L2/4 Y out IOB30[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_ck ddr_ck_n J1,J3/5 Y out IOB27 SSTL15D 8 NONE NA NA NA NA NA NA 1.5
ddr_cke J2/4 Y out IOB34[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_odt R3/4 Y out IOB48[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_reset_n B9/6 Y out IOL33[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
ddr_dm[0] G1/5 Y out IOB24[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
ddr_dm[1] K5/4 Y out IOB40[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
O_tmds_clk_p O_tmds_clk_n G16,H15/0 Y out IOT16 LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
O_tmds_data_p[0] O_tmds_data_n[0] H14,H16/0 Y out IOT20 LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
O_tmds_data_p[1] O_tmds_data_n[1] J15,K16/0 Y out IOT24 LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
O_tmds_data_p[2] O_tmds_data_n[2] K14,K15/1 Y out IOT30 LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
cmos_scl F14/0 Y io IOT9[A] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
cmos_sda F16/0 Y io IOT9[B] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
ddr_dq[0] G5/5 Y io IOB20[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[1] F5/5 Y io IOB22[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[2] F4/5 Y io IOB18[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[3] F3/5 Y io IOB19[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[4] E2/5 Y io IOB12[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[5] C1/5 Y io IOB14[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[6] E1/5 Y io IOB16[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[7] B3/5 Y io IOB13[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[8] M3/4 Y io IOB42[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[9] K4/4 Y io IOB39[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[10] N2/4 Y io IOB41[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[11] L1/4 Y io IOB38[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[12] P4/4 Y io IOB45[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[13] H3/4 Y io IOB32[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[14] R1/4 Y io IOB44[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dq[15] M2/4 Y io IOB43[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
ddr_dqs[0] ddr_dqs_n[0] G2,G3/5 Y io IOB21 SSTL15D 8 NONE NA NA NA NA NA NA 1.5
ddr_dqs[1] ddr_dqs_n[1] J5,K6/4 Y io IOB37 SSTL15D 8 NONE NA NA NA NA NA NA 1.5

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
L15/0 - in IOT2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
D16/0 - in IOT4[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
E14/0 - in IOT4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
C16/0 - in IOT5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
D15/0 - in IOT5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
E16/0 - in IOT6[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
F15/0 - in IOT6[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
F13/0 cmos_pclk in IOT8[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
G12/0 cmos_xclk out IOT8[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
F14/0 cmos_scl io IOT9[A] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
F16/0 cmos_sda io IOT9[B] LVCMOS33 8 UP NA NONE OFF NA NA NA 3.3
F12/0 - in IOT12[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
G13/0 - in IOT12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
G15/0 cmos_vsync in IOT13[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
G14/0 cmos_href in IOT13[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
G11/0 - in IOT14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
H12/0 - in IOT14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
G16/0 O_tmds_clk_p out IOT16[A] LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
H15/0 O_tmds_clk_n out IOT16[B] LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
H13/0 - in IOT18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
J12/0 - in IOT18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
H14/0 O_tmds_data_p[0] out IOT20[A] LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
H16/0 O_tmds_data_n[0] out IOT20[B] LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
J16/0 cmos_db[6] in IOT22[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
J14/0 cmos_db[7] in IOT22[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
J15/0 O_tmds_data_p[1] out IOT24[A] LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
K16/0 O_tmds_data_n[1] out IOT24[B] LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
H11/0 clk in IOT27[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
J13/0 - in IOT27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
K14/1 O_tmds_data_p[2] out IOT30[A] LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
K15/1 O_tmds_data_n[2] out IOT30[B] LVDS25 3.5 NONE NA NA NA NA NA NA 3.3
J11/1 - in IOT32[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
L12/1 - in IOT32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
L16/1 state_led[0] out IOT34[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
L14/1 state_led[1] out IOT34[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
K13/1 - in IOT36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
K12/1 - in IOT36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
K11/1 - in IOT38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
L13/1 cmos_rst_n out IOT38[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
M14/1 cmos_db[5] in IOT40[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
M15/1 cmos_db[4] in IOT40[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
D14/1 - in IOT44[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
E15/1 - in IOT44[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
N15/1 - in IOT48[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
P16/1 - in IOT48[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
N16/1 state_led[3] out IOT52[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
N14/1 state_led[2] out IOT52[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
P15/1 - in IOT54[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
R16/1 - in IOT54[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
A4/5 ddr_addr[1] out IOB2[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
C5/5 - in IOB2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
D6/5 ddr_addr[2] out IOB3[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
E7/5 - in IOB3[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
A3/5 ddr_addr[12] out IOB4[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
B4/5 - in IOB4[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
A5/5 ddr_addr[8] out IOB7[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
B6/5 - in IOB7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B1/5 ddr_addr[6] out IOB8[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
C2/5 - in IOB8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
D3/5 ddr_bank[1] out IOB9[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
D1/5 - in IOB9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
E2/5 ddr_dq[4] io IOB12[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
E3/5 - in IOB12[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B3/5 ddr_dq[7] io IOB13[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
A2/5 - in IOB13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
C1/5 ddr_dq[5] io IOB14[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
D2/5 - in IOB14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
E1/5 ddr_dq[6] io IOB16[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
F2/5 - in IOB16[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F4/5 ddr_dq[2] io IOB18[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
G6/5 - in IOB18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F3/5 ddr_dq[3] io IOB19[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
F1/5 - in IOB19[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G5/5 ddr_dq[0] io IOB20[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
G4/5 - in IOB20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G2/5 ddr_dqs[0] io IOB21[A] SSTL15D 8 NONE NA NA NA NA NA NA 1.5
G3/5 ddr_dqs_n[0] io IOB21[B] SSTL15D 8 NONE NA NA NA NA NA NA 1.5
F5/5 ddr_dq[1] io IOB22[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
H6/5 - in IOB22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
G1/5 ddr_dm[0] out IOB24[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
H2/5 - in IOB24[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H4/5 ddr_bank[0] out IOB26[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
J6/5 - in IOB26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J1/5 ddr_ck out IOB27[A] SSTL15D 8 NONE NA NA NA NA NA NA 1.5
J3/5 ddr_ck_n out IOB27[B] SSTL15D 8 NONE NA NA NA NA NA NA 1.5
L2/4 ddr_we out IOB30[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
M1/4 - in IOB30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H3/4 ddr_dq[13] io IOB32[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
H1/4 - in IOB32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J2/4 ddr_cke out IOB34[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
K1/4 - in IOB34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
H5/4 ddr_bank[2] out IOB35[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
J4/4 - in IOB35[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
K3/4 ddr_addr[10] out IOB36[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
K2/4 - in IOB36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
J5/4 ddr_dqs[1] io IOB37[A] SSTL15D 8 NONE NA NA NA NA NA NA 1.5
K6/4 ddr_dqs_n[1] io IOB37[B] SSTL15D 8 NONE NA NA NA NA NA NA 1.5
L1/4 ddr_dq[11] io IOB38[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
L3/4 - in IOB38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
K4/4 ddr_dq[9] io IOB39[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
L5/4 - in IOB39[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
K5/4 ddr_dm[1] out IOB40[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
L4/4 - in IOB40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
N2/4 ddr_dq[10] io IOB41[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
P1/4 - in IOB41[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
M3/4 ddr_dq[8] io IOB42[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
N1/4 - in IOB42[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
M2/4 ddr_dq[15] io IOB43[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
N3/4 - in IOB43[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R1/4 ddr_dq[14] io IOB44[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
P2/4 - in IOB44[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
P4/4 ddr_dq[12] io IOB45[A] SSTL15 8 NONE NA NA NA INTERNAL NA NA 1.5
T4/4 - in IOB45[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R3/4 ddr_odt out IOB48[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
T2/4 - in IOB48[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
P5/4 ddr_cs out IOB50[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
R5/4 - in IOB50[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R4/4 ddr_ras out IOB52[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
T3/4 - in IOB52[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
R6/4 ddr_cas out IOB54[A] SSTL15 8 NONE NA NA NA NA NA NA 1.5
T5/4 - in IOB54[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B14/7 - in IOL2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A15/7 - in IOL2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C12/7 - in IOL7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B12/7 - in IOL7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B13/7 - in IOL8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A14/7 - in IOL8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
F10/7 - in IOL11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
B11/7 - in IOL13[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A12/7 - in IOL13[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A11/7 - in IOL15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C11/7 - in IOL15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D10/7 - in IOL17[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
E10/7 - in IOL17[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
D11/7 - in IOL22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
A9/7 - in IOL27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C9/7 - in IOL27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
C8/6 ddr_addr[13] out IOL29[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
A8/6 - in IOL29[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F9/6 ddr_addr[9] out IOL31[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
E11/6 - in IOL31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B9/6 ddr_reset_n out IOL33[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
A10/6 - in IOL33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
F8/6 ddr_addr[3] out IOL35[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
D9/6 - in IOL35[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
D8/6 ddr_addr[7] out IOL38[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
E9/6 - in IOL38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
B7/6 ddr_addr[11] out IOL40[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
C7/6 rst_n in IOL40[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.5
F7/6 ddr_addr[0] out IOL45[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
E8/6 - in IOL45[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
C4/6 ddr_addr[4] out IOL47[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
B5/6 - in IOL47[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
E6/6 ddr_addr[5] out IOL53[A] SSTL15 8 NONE NA NA NA NA OFF NA 1.5
D7/6 - in IOL53[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.5
T15/2 - in IOR7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
R14/2 - in IOR7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
P12/2 - in IOR8[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
T13/2 - in IOR8[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
R12/2 - in IOR11[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
P13/2 - in IOR11[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
R11/2 cmos_db[3] in IOR17[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
T12/2 cmos_db[0] in IOR17[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
R13/2 - in IOR20[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
T14/2 - in IOR20[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
M10/2 - in IOR22[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
N11/2 - in IOR22[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
T11/2 cmos_db[1] in IOR24[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
P11/2 cmos_db[2] in IOR24[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 1.2
C6/2 - out IOR25[A] LVCMOS18 8 UP NA NA OFF NA NA NA 1.2
B8/2 - in IOR25[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
A7/2 - in IOR26[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
A6/2 - in IOR26[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
N10/2 - in IOR27[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
M11/2 - in IOR27[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.2
T7/3 - in IOR29[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
R8/3 - in IOR29[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
M16/3 - in IOR30[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
B16/3 - in IOR30[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
C15/3 - in IOR31[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
B10/3 - in IOR31[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
A13/3 - in IOR32[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
C13/3 - in IOR32[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
P10/3 - in IOR33[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
R10/3 - in IOR33[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
M9/3 - in IOR34[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
L10/3 - in IOR34[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
R9/3 - in IOR35[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
T10/3 - in IOR35[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
M8/3 - in IOR36[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
N9/3 - in IOR36[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
T9/3 - in IOR38[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
P9/3 - in IOR38[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
C10/3 cmos_pwdn out IOR39[A] LVCMOS33 8 UP NA NA OFF NA OFF NA 3.3
N8/3 - in IOR40[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
L9/3 - in IOR40[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
P8/3 - in IOR42[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
T8/3 - in IOR42[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
M6/3 - in IOR44[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
L8/3 - in IOR44[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
M7/3 - in IOR47[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
N7/3 - in IOR47[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
R7/3 - in IOR49[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
P7/3 - in IOR49[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
N6/3 - in IOR51[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
P6/3 - in IOR53[A] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3
T6/3 - in IOR53[B] LVCMOS18 NA UP ON NONE NA NA NA NA 3.3