Timing Messages
Report Title | Timing Analysis Report |
Design File | C:\Gowin\workspace\ultra_sonic\impl\gwsynthesis\ultra_sonic.vg |
Physical Constraints File | C:\Gowin\workspace\ultra_sonic\src\ultra_sonic.cst |
Timing Constraint File | C:\Gowin\workspace\ultra_sonic\src\ultra_sonic.sdc |
Tool Version | V1.9.11.02 (64-bit) |
Part Number | GW1N-UV1P5QN48XFC7/I6 |
Device | GW1N-1P5 |
Device Version | C |
Created Time | Mon Jun 9 11:43:12 2025 |
Legal Announcement | Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 1.71V 85C C7/I6 |
Hold Delay Model | Fast 3.6V 0C C7/I6 |
Numbers of Paths Analyzed | 443 |
Numbers of Endpoints Analyzed | 267 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|---|
1 | clk27mhz | Base | 37.037 | 27.000 | 0.000 | 18.518 | clk | ||
2 | clk1mhz | Generated | 999.999 | 1.000 | 0.000 | 499.999 | clk | clk27mhz | clk_1mhz |
3 | clk270hz | Generated | 3703699.750 | 0.000 | 0.000 | 1851849.875 | clk | clk27mhz | disp_dist_1/clk270hz |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clk27mhz | 27.000(MHz) | 125.843(MHz) | 8 | TOP |
2 | clk1mhz | 1.000(MHz) | 128.407(MHz) | 8 | TOP |
3 | clk270hz | 0.000(MHz) | 181.818(MHz) | 4 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clk27mhz | Setup | 0.000 | 0 |
clk27mhz | Hold | 0.000 | 0 |
clk1mhz | Setup | 0.000 | 0 |
clk1mhz | Hold | 0.000 | 0 |
clk270hz | Setup | 0.000 | 0 |
clk270hz | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 18.892 | measure_12_s0/Q | disp_dist_1/distance_0_s0/D | clk1mhz:[R] | clk27mhz:[R] | 37.037 | -1.296 | 19.115 |
2 | 19.438 | measure_12_s0/Q | disp_dist_1/distance_1_s0/D | clk1mhz:[R] | clk27mhz:[R] | 37.037 | -1.296 | 18.568 |
3 | 20.398 | measure_12_s0/Q | disp_dist_1/distance_2_s0/D | clk1mhz:[R] | clk27mhz:[R] | 37.037 | -1.296 | 17.609 |
4 | 22.899 | measure_12_s0/Q | disp_dist_1/distance_3_s0/D | clk1mhz:[R] | clk27mhz:[R] | 37.037 | -1.296 | 15.107 |
5 | 25.761 | measure_12_s0/Q | disp_dist_1/distance_4_s0/D | clk1mhz:[R] | clk27mhz:[R] | 37.037 | -1.296 | 12.245 |
6 | 26.650 | measure_15_s0/Q | disp_dist_1/distance_5_s0/D | clk1mhz:[R] | clk27mhz:[R] | 37.037 | -1.296 | 11.357 |
7 | 28.670 | measure_15_s0/Q | disp_dist_1/distance_6_s0/D | clk1mhz:[R] | clk27mhz:[R] | 37.037 | -1.296 | 9.337 |
8 | 29.091 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.650 |
9 | 29.091 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.650 |
10 | 29.094 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.647 |
11 | 29.124 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.617 |
12 | 29.136 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.605 |
13 | 29.210 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.531 |
14 | 29.213 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.527 |
15 | 29.213 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.527 |
16 | 29.235 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.506 |
17 | 29.239 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_9_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.501 |
18 | 29.297 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.443 |
19 | 29.453 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.288 |
20 | 29.453 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.288 |
21 | 29.453 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.288 |
22 | 29.572 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.168 |
23 | 29.572 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_13_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.168 |
24 | 30.369 | disp_dist_1/clkdiv_3/count_1_s0/Q | disp_dist_1/clkdiv_3/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.371 |
25 | 31.661 | measure_12_s0/Q | disp_dist_1/distance_7_s0/D | clk1mhz:[R] | clk27mhz:[R] | 37.037 | -1.296 | 6.346 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.097 | measure_12_s0/Q | disp_dist_1/distance_10_s0/D | clk1mhz:[R] | clk27mhz:[R] | 0.000 | -0.827 | 0.954 |
2 | 0.204 | measure_7_s0/Q | disp_dist_1/distance_6_s0/D | clk1mhz:[R] | clk27mhz:[R] | 0.000 | -0.827 | 1.061 |
3 | 0.310 | measure_15_s0/Q | disp_dist_1/distance_9_s0/D | clk1mhz:[R] | clk27mhz:[R] | 0.000 | -0.827 | 1.167 |
4 | 0.328 | measure_9_s0/Q | disp_dist_1/distance_7_s0/D | clk1mhz:[R] | clk27mhz:[R] | 0.000 | -0.827 | 1.185 |
5 | 0.524 | dlkdiv_2/count_3_s0/Q | dlkdiv_2/count_3_s0/D | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.524 |
6 | 0.524 | dlkdiv_2/count_13_s0/Q | dlkdiv_2/count_13_s0/D | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.524 |
7 | 0.524 | trig_count_3_s1/Q | trig_count_3_s1/D | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.524 |
8 | 0.524 | disp_dist_1/clkdiv_3/count_0_s0/Q | disp_dist_1/clkdiv_3/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
9 | 0.524 | disp_dist_1/clkdiv_3/count_3_s0/Q | disp_dist_1/clkdiv_3/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
10 | 0.524 | disp_dist_1/clkdiv_3/count_12_s0/Q | disp_dist_1/clkdiv_3/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
11 | 0.525 | counter16_1/count_0_s0/Q | counter16_1/count_0_s0/D | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.525 |
12 | 0.525 | disp_dist_1/clkdiv_3/count_6_s0/Q | disp_dist_1/clkdiv_3/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
13 | 0.525 | disp_dist_1/clkdiv_3/count_7_s0/Q | disp_dist_1/clkdiv_3/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
14 | 0.525 | disp_dist_1/clkdiv_3/count_10_s0/Q | disp_dist_1/clkdiv_3/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
15 | 0.525 | disp_dist_1/clkdiv_3/count_13_s0/Q | disp_dist_1/clkdiv_3/count_13_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
16 | 0.525 | disp_dist_1/clkdiv_3/count_14_s0/Q | disp_dist_1/clkdiv_3/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
17 | 0.525 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
18 | 0.525 | clkdiv_1/count_2_s0/Q | clkdiv_1/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
19 | 0.527 | state_1_s0/Q | state_1_s0/D | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.527 |
20 | 0.528 | disp_dist_1/mux7seg_1/col_1_s0/Q | disp_dist_1/mux7seg_1/col_1_s0/D | clk270hz:[R] | clk270hz:[R] | 0.000 | 0.000 | 0.528 |
21 | 0.542 | counter16_1/count_2_s0/Q | counter16_1/count_2_s0/D | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.542 |
22 | 0.542 | counter16_1/count_6_s0/Q | counter16_1/count_6_s0/D | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.542 |
23 | 0.542 | counter16_1/count_8_s0/Q | counter16_1/count_8_s0/D | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.542 |
24 | 0.542 | counter16_1/count_12_s0/Q | counter16_1/count_12_s0/D | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.542 |
25 | 0.542 | counter16_1/count_14_s0/Q | counter16_1/count_14_s0/D | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.542 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 998.641 | count_nrst_s1/Q | counter16_1/count_12_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 1.326 |
2 | 998.641 | count_nrst_s1/Q | counter16_1/count_13_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 1.326 |
3 | 998.641 | count_nrst_s1/Q | counter16_1/count_14_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 1.326 |
4 | 998.641 | count_nrst_s1/Q | counter16_1/count_15_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 1.326 |
5 | 998.664 | count_nrst_s1/Q | counter16_1/ov_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 1.303 |
6 | 998.993 | count_nrst_s1/Q | counter16_1/count_1_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.974 |
7 | 998.993 | count_nrst_s1/Q | counter16_1/count_2_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.974 |
8 | 998.993 | count_nrst_s1/Q | counter16_1/count_3_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.974 |
9 | 998.993 | count_nrst_s1/Q | counter16_1/count_4_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.974 |
10 | 998.993 | count_nrst_s1/Q | counter16_1/count_5_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.974 |
11 | 999.016 | count_nrst_s1/Q | counter16_1/count_6_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.950 |
12 | 999.016 | count_nrst_s1/Q | counter16_1/count_7_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.950 |
13 | 999.016 | count_nrst_s1/Q | counter16_1/count_8_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.950 |
14 | 999.016 | count_nrst_s1/Q | counter16_1/count_9_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.950 |
15 | 999.016 | count_nrst_s1/Q | counter16_1/count_10_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.950 |
16 | 999.016 | count_nrst_s1/Q | counter16_1/count_11_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.950 |
17 | 999.023 | count_nrst_s1/Q | counter16_1/count_0_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 999.999 | 0.000 | 0.944 |
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 0.623 | count_nrst_s1/Q | counter16_1/count_1_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.632 |
2 | 0.623 | count_nrst_s1/Q | counter16_1/count_2_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.632 |
3 | 0.623 | count_nrst_s1/Q | counter16_1/count_3_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.632 |
4 | 0.623 | count_nrst_s1/Q | counter16_1/count_4_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.632 |
5 | 0.623 | count_nrst_s1/Q | counter16_1/count_5_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.632 |
6 | 0.663 | count_nrst_s1/Q | counter16_1/count_0_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.672 |
7 | 0.669 | count_nrst_s1/Q | counter16_1/count_6_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.678 |
8 | 0.669 | count_nrst_s1/Q | counter16_1/count_7_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.678 |
9 | 0.669 | count_nrst_s1/Q | counter16_1/count_8_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.678 |
10 | 0.669 | count_nrst_s1/Q | counter16_1/count_9_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.678 |
11 | 0.669 | count_nrst_s1/Q | counter16_1/count_10_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.678 |
12 | 0.669 | count_nrst_s1/Q | counter16_1/count_11_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.678 |
13 | 0.814 | count_nrst_s1/Q | counter16_1/count_12_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.823 |
14 | 0.814 | count_nrst_s1/Q | counter16_1/count_13_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.823 |
15 | 0.814 | count_nrst_s1/Q | counter16_1/count_14_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.823 |
16 | 0.814 | count_nrst_s1/Q | counter16_1/count_15_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.823 |
17 | 0.858 | count_nrst_s1/Q | counter16_1/ov_s0/CLEAR | clk1mhz:[R] | clk1mhz:[R] | 0.000 | 0.000 | 0.868 |
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/count_4_s0 |
2 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/count_2_s0 |
3 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | disp_dist_1/distance_10_s0 |
4 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | disp_dist_1/distance_2_s0 |
5 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | disp_dist_1/clkdiv_3/count_3_s0 |
6 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | disp_dist_1/clkdiv_3/count_4_s0 |
7 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | disp_dist_1/distance_3_s0 |
8 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | disp_dist_1/clkdiv_3/count_5_s0 |
9 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | disp_dist_1/clkdiv_3/count_6_s0 |
10 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/clk_out_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 18.892 |
Data Arrival Time | 20.088 |
Data Required Time | 38.979 |
From | measure_12_s0 |
To | disp_dist_1/distance_0_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R8C15[2][B] | measure_12_s0/CLK |
1.313 | 0.340 | tC2Q | RR | 11 | R8C15[2][B] | measure_12_s0/Q |
1.628 | 0.315 | tNET | RR | 1 | R8C14[3][A] | disp_dist_1/n15_s19/I1 |
2.414 | 0.786 | tINS | RR | 2 | R8C14[3][A] | disp_dist_1/n15_s19/F |
2.726 | 0.312 | tNET | RR | 1 | R8C13[1][B] | disp_dist_1/n17_s21/I3 |
3.540 | 0.814 | tINS | RF | 5 | R8C13[1][B] | disp_dist_1/n17_s21/F |
4.507 | 0.967 | tNET | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/I2 |
5.321 | 0.814 | tINS | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/F |
5.325 | 0.004 | tNET | FF | 1 | R8C12[3][B] | disp_dist_1/n17_s17/I0 |
6.090 | 0.765 | tINS | FF | 3 | R8C12[3][B] | disp_dist_1/n17_s17/F |
6.690 | 0.600 | tNET | FF | 1 | R9C11[3][A] | disp_dist_1/n17_s15/I0 |
7.299 | 0.609 | tINS | FF | 2 | R9C11[3][A] | disp_dist_1/n17_s15/F |
7.899 | 0.599 | tNET | FF | 1 | R12C11[1][A] | disp_dist_1/n18_s13/I0 |
8.363 | 0.464 | tINS | FF | 6 | R12C11[1][A] | disp_dist_1/n18_s13/F |
8.967 | 0.604 | tNET | FF | 1 | R11C11[1][B] | disp_dist_1/n21_s13/I2 |
9.753 | 0.786 | tINS | FR | 6 | R11C11[1][B] | disp_dist_1/n21_s13/F |
10.071 | 0.318 | tNET | RR | 1 | R12C11[1][B] | disp_dist_1/n20_s15/I2 |
10.835 | 0.765 | tINS | RF | 2 | R12C11[1][B] | disp_dist_1/n20_s15/F |
10.843 | 0.008 | tNET | FF | 1 | R12C11[2][B] | disp_dist_1/n20_s19/I3 |
11.658 | 0.814 | tINS | FF | 6 | R12C11[2][B] | disp_dist_1/n20_s19/F |
12.755 | 1.097 | tNET | FF | 1 | R7C11[2][B] | disp_dist_1/n21_s14/I1 |
13.569 | 0.814 | tINS | FF | 2 | R7C11[2][B] | disp_dist_1/n21_s14/F |
14.540 | 0.971 | tNET | FF | 1 | R11C11[3][A] | disp_dist_1/n21_s10/I3 |
15.301 | 0.760 | tINS | FR | 3 | R11C11[3][A] | disp_dist_1/n21_s10/F |
15.617 | 0.316 | tNET | RR | 1 | R11C10[3][A] | disp_dist_1/n22_s13/I2 |
16.081 | 0.464 | tINS | RF | 3 | R11C10[3][A] | disp_dist_1/n22_s13/F |
16.703 | 0.623 | tNET | FF | 1 | R9C10[1][B] | disp_dist_1/n22_s12/I0 |
17.518 | 0.814 | tINS | FF | 2 | R9C10[1][B] | disp_dist_1/n22_s12/F |
18.118 | 0.600 | tNET | FF | 1 | R8C10[1][B] | disp_dist_1/n24_s24/I2 |
18.883 | 0.765 | tINS | FF | 1 | R8C10[1][B] | disp_dist_1/n24_s24/F |
19.479 | 0.596 | tNET | FF | 1 | R9C9[0][B] | disp_dist_1/n24_s23/I0 |
20.088 | 0.609 | tINS | FF | 1 | R9C9[0][B] | disp_dist_1/n24_s23/F |
20.088 | 0.000 | tNET | FF | 1 | R9C9[0][B] | disp_dist_1/distance_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R9C9[0][B] | disp_dist_1/distance_0_s0/CLK |
39.276 | -0.030 | tUnc | disp_dist_1/distance_0_s0 | |||
38.979 | -0.296 | tSu | 1 | R9C9[0][B] | disp_dist_1/distance_0_s0 |
Path Statistics:
Clock Skew | 1.296 |
Setup Relationship | 37.037 |
Logic Level | 16 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 10.845, 56.734%; route: 7.931, 41.489%; tC2Q: 0.340, 1.777% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path2
Path Summary:
Slack | 19.438 |
Data Arrival Time | 19.541 |
Data Required Time | 38.979 |
From | measure_12_s0 |
To | disp_dist_1/distance_1_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R8C15[2][B] | measure_12_s0/CLK |
1.313 | 0.340 | tC2Q | RR | 11 | R8C15[2][B] | measure_12_s0/Q |
1.628 | 0.315 | tNET | RR | 1 | R8C14[3][A] | disp_dist_1/n15_s19/I1 |
2.414 | 0.786 | tINS | RR | 2 | R8C14[3][A] | disp_dist_1/n15_s19/F |
2.726 | 0.312 | tNET | RR | 1 | R8C13[1][B] | disp_dist_1/n17_s21/I3 |
3.540 | 0.814 | tINS | RF | 5 | R8C13[1][B] | disp_dist_1/n17_s21/F |
4.507 | 0.967 | tNET | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/I2 |
5.321 | 0.814 | tINS | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/F |
5.325 | 0.004 | tNET | FF | 1 | R8C12[3][B] | disp_dist_1/n17_s17/I0 |
6.090 | 0.765 | tINS | FF | 3 | R8C12[3][B] | disp_dist_1/n17_s17/F |
6.690 | 0.600 | tNET | FF | 1 | R9C11[3][A] | disp_dist_1/n17_s15/I0 |
7.299 | 0.609 | tINS | FF | 2 | R9C11[3][A] | disp_dist_1/n17_s15/F |
7.899 | 0.599 | tNET | FF | 1 | R12C11[1][A] | disp_dist_1/n18_s13/I0 |
8.363 | 0.464 | tINS | FF | 6 | R12C11[1][A] | disp_dist_1/n18_s13/F |
8.967 | 0.604 | tNET | FF | 1 | R11C11[1][B] | disp_dist_1/n21_s13/I2 |
9.753 | 0.786 | tINS | FR | 6 | R11C11[1][B] | disp_dist_1/n21_s13/F |
10.071 | 0.318 | tNET | RR | 1 | R12C11[1][B] | disp_dist_1/n20_s15/I2 |
10.835 | 0.765 | tINS | RF | 2 | R12C11[1][B] | disp_dist_1/n20_s15/F |
10.843 | 0.008 | tNET | FF | 1 | R12C11[2][B] | disp_dist_1/n20_s19/I3 |
11.658 | 0.814 | tINS | FF | 6 | R12C11[2][B] | disp_dist_1/n20_s19/F |
12.755 | 1.097 | tNET | FF | 1 | R7C11[2][B] | disp_dist_1/n21_s14/I1 |
13.569 | 0.814 | tINS | FF | 2 | R7C11[2][B] | disp_dist_1/n21_s14/F |
14.540 | 0.971 | tNET | FF | 1 | R11C11[3][A] | disp_dist_1/n21_s10/I3 |
15.301 | 0.760 | tINS | FR | 3 | R11C11[3][A] | disp_dist_1/n21_s10/F |
15.617 | 0.316 | tNET | RR | 1 | R11C10[3][B] | disp_dist_1/n23_s15/I1 |
16.081 | 0.464 | tINS | RF | 4 | R11C10[3][B] | disp_dist_1/n23_s15/F |
16.688 | 0.607 | tNET | FF | 1 | R8C10[3][B] | disp_dist_1/n23_s14/I3 |
17.297 | 0.609 | tINS | FF | 2 | R8C10[3][B] | disp_dist_1/n23_s14/F |
17.663 | 0.366 | tNET | FF | 1 | R9C10[2][B] | disp_dist_1/n23_s10/I3 |
18.477 | 0.814 | tINS | FF | 2 | R9C10[2][B] | disp_dist_1/n23_s10/F |
19.541 | 1.064 | tNET | FF | 1 | R8C9[1][B] | disp_dist_1/distance_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R8C9[1][B] | disp_dist_1/distance_1_s0/CLK |
39.276 | -0.030 | tUnc | disp_dist_1/distance_1_s0 | |||
38.979 | -0.296 | tSu | 1 | R8C9[1][B] | disp_dist_1/distance_1_s0 |
Path Statistics:
Clock Skew | 1.296 |
Setup Relationship | 37.037 |
Logic Level | 15 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 10.080, 54.285%; route: 8.149, 43.886%; tC2Q: 0.340, 1.829% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path3
Path Summary:
Slack | 20.398 |
Data Arrival Time | 18.582 |
Data Required Time | 38.979 |
From | measure_12_s0 |
To | disp_dist_1/distance_2_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R8C15[2][B] | measure_12_s0/CLK |
1.313 | 0.340 | tC2Q | RR | 11 | R8C15[2][B] | measure_12_s0/Q |
1.628 | 0.315 | tNET | RR | 1 | R8C14[3][A] | disp_dist_1/n15_s19/I1 |
2.414 | 0.786 | tINS | RR | 2 | R8C14[3][A] | disp_dist_1/n15_s19/F |
2.726 | 0.312 | tNET | RR | 1 | R8C13[1][B] | disp_dist_1/n17_s21/I3 |
3.540 | 0.814 | tINS | RF | 5 | R8C13[1][B] | disp_dist_1/n17_s21/F |
4.507 | 0.967 | tNET | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/I2 |
5.321 | 0.814 | tINS | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/F |
5.325 | 0.004 | tNET | FF | 1 | R8C12[3][B] | disp_dist_1/n17_s17/I0 |
6.090 | 0.765 | tINS | FF | 3 | R8C12[3][B] | disp_dist_1/n17_s17/F |
6.690 | 0.600 | tNET | FF | 1 | R9C11[3][A] | disp_dist_1/n17_s15/I0 |
7.299 | 0.609 | tINS | FF | 2 | R9C11[3][A] | disp_dist_1/n17_s15/F |
7.899 | 0.599 | tNET | FF | 1 | R12C11[1][A] | disp_dist_1/n18_s13/I0 |
8.363 | 0.464 | tINS | FF | 6 | R12C11[1][A] | disp_dist_1/n18_s13/F |
8.967 | 0.604 | tNET | FF | 1 | R11C11[1][B] | disp_dist_1/n21_s13/I2 |
9.753 | 0.786 | tINS | FR | 6 | R11C11[1][B] | disp_dist_1/n21_s13/F |
10.071 | 0.318 | tNET | RR | 1 | R12C11[1][B] | disp_dist_1/n20_s15/I2 |
10.835 | 0.765 | tINS | RF | 2 | R12C11[1][B] | disp_dist_1/n20_s15/F |
10.843 | 0.008 | tNET | FF | 1 | R12C11[2][B] | disp_dist_1/n20_s19/I3 |
11.658 | 0.814 | tINS | FF | 6 | R12C11[2][B] | disp_dist_1/n20_s19/F |
12.755 | 1.097 | tNET | FF | 1 | R7C11[2][B] | disp_dist_1/n21_s14/I1 |
13.569 | 0.814 | tINS | FF | 2 | R7C11[2][B] | disp_dist_1/n21_s14/F |
14.540 | 0.971 | tNET | FF | 1 | R11C11[3][A] | disp_dist_1/n21_s10/I3 |
15.301 | 0.760 | tINS | FR | 3 | R11C11[3][A] | disp_dist_1/n21_s10/F |
15.617 | 0.316 | tNET | RR | 1 | R11C10[3][A] | disp_dist_1/n22_s13/I2 |
16.081 | 0.464 | tINS | RF | 3 | R11C10[3][A] | disp_dist_1/n22_s13/F |
16.703 | 0.623 | tNET | FF | 1 | R9C10[1][B] | disp_dist_1/n22_s12/I0 |
17.518 | 0.814 | tINS | FF | 2 | R9C10[1][B] | disp_dist_1/n22_s12/F |
18.582 | 1.064 | tNET | FF | 1 | R8C9[0][A] | disp_dist_1/distance_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R8C9[0][A] | disp_dist_1/distance_2_s0/CLK |
39.276 | -0.030 | tUnc | disp_dist_1/distance_2_s0 | |||
38.979 | -0.296 | tSu | 1 | R8C9[0][A] | disp_dist_1/distance_2_s0 |
Path Statistics:
Clock Skew | 1.296 |
Setup Relationship | 37.037 |
Logic Level | 14 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 9.471, 53.784%; route: 7.798, 44.287%; tC2Q: 0.340, 1.929% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path4
Path Summary:
Slack | 22.899 |
Data Arrival Time | 16.080 |
Data Required Time | 38.979 |
From | measure_12_s0 |
To | disp_dist_1/distance_3_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R8C15[2][B] | measure_12_s0/CLK |
1.313 | 0.340 | tC2Q | RR | 11 | R8C15[2][B] | measure_12_s0/Q |
1.628 | 0.315 | tNET | RR | 1 | R8C14[3][A] | disp_dist_1/n15_s19/I1 |
2.414 | 0.786 | tINS | RR | 2 | R8C14[3][A] | disp_dist_1/n15_s19/F |
2.726 | 0.312 | tNET | RR | 1 | R8C13[1][B] | disp_dist_1/n17_s21/I3 |
3.540 | 0.814 | tINS | RF | 5 | R8C13[1][B] | disp_dist_1/n17_s21/F |
4.507 | 0.967 | tNET | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/I2 |
5.321 | 0.814 | tINS | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/F |
5.325 | 0.004 | tNET | FF | 1 | R8C12[3][B] | disp_dist_1/n17_s17/I0 |
6.090 | 0.765 | tINS | FF | 3 | R8C12[3][B] | disp_dist_1/n17_s17/F |
6.690 | 0.600 | tNET | FF | 1 | R9C11[3][A] | disp_dist_1/n17_s15/I0 |
7.299 | 0.609 | tINS | FF | 2 | R9C11[3][A] | disp_dist_1/n17_s15/F |
7.899 | 0.599 | tNET | FF | 1 | R12C11[1][A] | disp_dist_1/n18_s13/I0 |
8.363 | 0.464 | tINS | FF | 6 | R12C11[1][A] | disp_dist_1/n18_s13/F |
8.967 | 0.604 | tNET | FF | 1 | R11C11[1][B] | disp_dist_1/n21_s13/I2 |
9.753 | 0.786 | tINS | FR | 6 | R11C11[1][B] | disp_dist_1/n21_s13/F |
10.071 | 0.318 | tNET | RR | 1 | R12C11[1][B] | disp_dist_1/n20_s15/I2 |
10.835 | 0.765 | tINS | RF | 2 | R12C11[1][B] | disp_dist_1/n20_s15/F |
10.843 | 0.008 | tNET | FF | 1 | R12C11[2][B] | disp_dist_1/n20_s19/I3 |
11.658 | 0.814 | tINS | FF | 6 | R12C11[2][B] | disp_dist_1/n20_s19/F |
12.755 | 1.097 | tNET | FF | 1 | R7C11[2][B] | disp_dist_1/n21_s14/I1 |
13.569 | 0.814 | tINS | FF | 2 | R7C11[2][B] | disp_dist_1/n21_s14/F |
14.540 | 0.971 | tNET | FF | 1 | R11C11[3][A] | disp_dist_1/n21_s10/I3 |
15.301 | 0.760 | tINS | FR | 3 | R11C11[3][A] | disp_dist_1/n21_s10/F |
16.080 | 0.779 | tNET | RR | 1 | R11C10[0][A] | disp_dist_1/distance_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R11C10[0][A] | disp_dist_1/distance_3_s0/CLK |
39.276 | -0.030 | tUnc | disp_dist_1/distance_3_s0 | |||
38.979 | -0.296 | tSu | 1 | R11C10[0][A] | disp_dist_1/distance_3_s0 |
Path Statistics:
Clock Skew | 1.296 |
Setup Relationship | 37.037 |
Logic Level | 12 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 8.192, 54.230%; route: 6.575, 43.522%; tC2Q: 0.340, 2.248% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path5
Path Summary:
Slack | 25.761 |
Data Arrival Time | 13.218 |
Data Required Time | 38.979 |
From | measure_12_s0 |
To | disp_dist_1/distance_4_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R8C15[2][B] | measure_12_s0/CLK |
1.313 | 0.340 | tC2Q | RR | 11 | R8C15[2][B] | measure_12_s0/Q |
1.628 | 0.315 | tNET | RR | 1 | R8C14[3][A] | disp_dist_1/n15_s19/I1 |
2.414 | 0.786 | tINS | RR | 2 | R8C14[3][A] | disp_dist_1/n15_s19/F |
2.726 | 0.312 | tNET | RR | 1 | R8C13[1][B] | disp_dist_1/n17_s21/I3 |
3.540 | 0.814 | tINS | RF | 5 | R8C13[1][B] | disp_dist_1/n17_s21/F |
4.507 | 0.967 | tNET | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/I2 |
5.321 | 0.814 | tINS | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/F |
5.325 | 0.004 | tNET | FF | 1 | R8C12[3][B] | disp_dist_1/n17_s17/I0 |
6.090 | 0.765 | tINS | FF | 3 | R8C12[3][B] | disp_dist_1/n17_s17/F |
6.690 | 0.600 | tNET | FF | 1 | R9C11[3][A] | disp_dist_1/n17_s15/I0 |
7.299 | 0.609 | tINS | FF | 2 | R9C11[3][A] | disp_dist_1/n17_s15/F |
7.899 | 0.599 | tNET | FF | 1 | R12C11[1][A] | disp_dist_1/n18_s13/I0 |
8.363 | 0.464 | tINS | FF | 6 | R12C11[1][A] | disp_dist_1/n18_s13/F |
8.967 | 0.604 | tNET | FF | 1 | R11C11[1][B] | disp_dist_1/n21_s13/I2 |
9.753 | 0.786 | tINS | FR | 6 | R11C11[1][B] | disp_dist_1/n21_s13/F |
10.071 | 0.318 | tNET | RR | 1 | R12C11[1][B] | disp_dist_1/n20_s15/I2 |
10.835 | 0.765 | tINS | RF | 2 | R12C11[1][B] | disp_dist_1/n20_s15/F |
10.843 | 0.008 | tNET | FF | 1 | R12C11[2][B] | disp_dist_1/n20_s19/I3 |
11.658 | 0.814 | tINS | FF | 6 | R12C11[2][B] | disp_dist_1/n20_s19/F |
12.755 | 1.097 | tNET | FF | 1 | R7C11[1][B] | disp_dist_1/n20_s7/I1 |
13.218 | 0.464 | tINS | FF | 1 | R7C11[1][B] | disp_dist_1/n20_s7/F |
13.218 | 0.000 | tNET | FF | 1 | R7C11[1][B] | disp_dist_1/distance_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R7C11[1][B] | disp_dist_1/distance_4_s0/CLK |
39.276 | -0.030 | tUnc | disp_dist_1/distance_4_s0 | |||
38.979 | -0.296 | tSu | 1 | R7C11[1][B] | disp_dist_1/distance_4_s0 |
Path Statistics:
Clock Skew | 1.296 |
Setup Relationship | 37.037 |
Logic Level | 11 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 7.082, 57.832%; route: 4.824, 39.395%; tC2Q: 0.340, 2.773% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path6
Path Summary:
Slack | 26.650 |
Data Arrival Time | 12.330 |
Data Required Time | 38.979 |
From | measure_15_s0 |
To | disp_dist_1/distance_5_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R8C15[1][B] | measure_15_s0/CLK |
1.313 | 0.340 | tC2Q | RF | 12 | R8C15[1][B] | measure_15_s0/Q |
1.925 | 0.613 | tNET | FF | 1 | R9C14[1][B] | disp_dist_1/n17_s26/I1 |
2.740 | 0.814 | tINS | FF | 1 | R9C14[1][B] | disp_dist_1/n17_s26/F |
2.744 | 0.004 | tNET | FF | 1 | R9C14[1][A] | disp_dist_1/n17_s25/I3 |
3.530 | 0.786 | tINS | FR | 1 | R9C14[1][A] | disp_dist_1/n17_s25/F |
3.840 | 0.310 | tNET | RR | 1 | R9C13[1][B] | disp_dist_1/n17_s23/I2 |
4.627 | 0.786 | tINS | RR | 4 | R9C13[1][B] | disp_dist_1/n17_s23/F |
4.940 | 0.313 | tNET | RR | 1 | R8C13[2][A] | disp_dist_1/n18_s20/I3 |
5.549 | 0.609 | tINS | RF | 2 | R8C13[2][A] | disp_dist_1/n18_s20/F |
6.512 | 0.963 | tNET | FF | 1 | R11C12[0][A] | disp_dist_1/n18_s15/I1 |
7.273 | 0.760 | tINS | FR | 3 | R11C12[0][A] | disp_dist_1/n18_s15/F |
7.588 | 0.315 | tNET | RR | 1 | R11C11[0][B] | disp_dist_1/n19_s18/I2 |
8.348 | 0.760 | tINS | RR | 1 | R11C11[0][B] | disp_dist_1/n19_s18/F |
8.658 | 0.310 | tNET | RR | 1 | R12C11[3][B] | disp_dist_1/n19_s13/I1 |
9.444 | 0.786 | tINS | RR | 5 | R12C11[3][B] | disp_dist_1/n19_s13/F |
9.762 | 0.318 | tNET | RR | 1 | R12C10[3][A] | disp_dist_1/n19_s10/I2 |
10.527 | 0.765 | tINS | RF | 4 | R12C10[3][A] | disp_dist_1/n19_s10/F |
12.330 | 1.803 | tNET | FF | 1 | R7C9[0][A] | disp_dist_1/distance_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R7C9[0][A] | disp_dist_1/distance_5_s0/CLK |
39.276 | -0.030 | tUnc | disp_dist_1/distance_5_s0 | |||
38.979 | -0.296 | tSu | 1 | R7C9[0][A] | disp_dist_1/distance_5_s0 |
Path Statistics:
Clock Skew | 1.296 |
Setup Relationship | 37.037 |
Logic Level | 9 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 6.067, 53.424%; route: 4.950, 43.585%; tC2Q: 0.340, 2.990% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path7
Path Summary:
Slack | 28.670 |
Data Arrival Time | 10.310 |
Data Required Time | 38.979 |
From | measure_15_s0 |
To | disp_dist_1/distance_6_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R8C15[1][B] | measure_15_s0/CLK |
1.313 | 0.340 | tC2Q | RF | 12 | R8C15[1][B] | measure_15_s0/Q |
1.925 | 0.613 | tNET | FF | 1 | R9C14[1][B] | disp_dist_1/n17_s26/I1 |
2.740 | 0.814 | tINS | FF | 1 | R9C14[1][B] | disp_dist_1/n17_s26/F |
2.744 | 0.004 | tNET | FF | 1 | R9C14[1][A] | disp_dist_1/n17_s25/I3 |
3.530 | 0.786 | tINS | FR | 1 | R9C14[1][A] | disp_dist_1/n17_s25/F |
3.840 | 0.310 | tNET | RR | 1 | R9C13[1][B] | disp_dist_1/n17_s23/I2 |
4.655 | 0.814 | tINS | RF | 4 | R9C13[1][B] | disp_dist_1/n17_s23/F |
5.262 | 0.608 | tNET | FF | 1 | R8C12[1][B] | disp_dist_1/n18_s18/I2 |
6.027 | 0.765 | tINS | FF | 6 | R8C12[1][B] | disp_dist_1/n18_s18/F |
6.636 | 0.608 | tNET | FF | 1 | R9C11[2][B] | disp_dist_1/n18_s17/I3 |
7.450 | 0.814 | tINS | FF | 2 | R9C11[2][B] | disp_dist_1/n18_s17/F |
8.062 | 0.612 | tNET | FF | 1 | R11C11[1][A] | disp_dist_1/n18_s12/I3 |
8.876 | 0.814 | tINS | FF | 3 | R11C11[1][A] | disp_dist_1/n18_s12/F |
9.495 | 0.620 | tNET | FF | 1 | R9C11[2][A] | disp_dist_1/n18_s28/I2 |
10.310 | 0.814 | tINS | FF | 1 | R9C11[2][A] | disp_dist_1/n18_s28/F |
10.310 | 0.000 | tNET | FF | 1 | R9C11[2][A] | disp_dist_1/distance_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R9C11[2][A] | disp_dist_1/distance_6_s0/CLK |
39.276 | -0.030 | tUnc | disp_dist_1/distance_6_s0 | |||
38.979 | -0.296 | tSu | 1 | R9C11[2][A] | disp_dist_1/distance_6_s0 |
Path Statistics:
Clock Skew | 1.296 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 5.623, 60.221%; route: 3.374, 36.142%; tC2Q: 0.340, 3.637% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path8
Path Summary:
Slack | 29.091 |
Data Arrival Time | 9.919 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
9.310 | 0.670 | tNET | FF | 1 | R12C7[0][B] | disp_dist_1/clkdiv_3/n59_s4/I3 |
9.919 | 0.609 | tINS | FF | 1 | R12C7[0][B] | disp_dist_1/clkdiv_3/n59_s4/F |
9.919 | 0.000 | tNET | FF | 1 | R12C7[0][B] | disp_dist_1/clkdiv_3/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R12C7[0][B] | disp_dist_1/clkdiv_3/count_2_s0/CLK |
39.009 | -0.296 | tSu | 1 | R12C7[0][B] | disp_dist_1/clkdiv_3/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.318, 69.519%; route: 1.992, 26.042%; tC2Q: 0.340, 4.440% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path9
Path Summary:
Slack | 29.091 |
Data Arrival Time | 9.919 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
9.310 | 0.670 | tNET | FF | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/n58_s2/I3 |
9.919 | 0.609 | tINS | FF | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/n58_s2/F |
9.919 | 0.000 | tNET | FF | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/count_3_s0/CLK |
39.009 | -0.296 | tSu | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.318, 69.519%; route: 1.992, 26.042%; tC2Q: 0.340, 4.440% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path10
Path Summary:
Slack | 29.094 |
Data Arrival Time | 9.915 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
9.306 | 0.666 | tNET | FF | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/n55_s2/I3 |
9.915 | 0.609 | tINS | FF | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/n55_s2/F |
9.915 | 0.000 | tNET | FF | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/count_6_s0/CLK |
39.009 | -0.296 | tSu | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.318, 69.549%; route: 1.989, 26.009%; tC2Q: 0.340, 4.442% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path11
Path Summary:
Slack | 29.124 |
Data Arrival Time | 9.886 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_14_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
9.277 | 0.637 | tNET | FF | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/n47_s2/I3 |
9.886 | 0.609 | tINS | FF | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/n47_s2/F |
9.886 | 0.000 | tNET | FF | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/count_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/count_14_s0/CLK |
39.009 | -0.296 | tSu | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.318, 69.820%; route: 1.959, 25.721%; tC2Q: 0.340, 4.459% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path12
Path Summary:
Slack | 29.136 |
Data Arrival Time | 9.873 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
9.264 | 0.624 | tNET | FF | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/n60_s2/I2 |
9.873 | 0.609 | tINS | FF | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/n60_s2/F |
9.873 | 0.000 | tNET | FF | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
39.009 | -0.296 | tSu | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.318, 69.933%; route: 1.947, 25.601%; tC2Q: 0.340, 4.466% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path13
Path Summary:
Slack | 29.210 |
Data Arrival Time | 9.800 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_16_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.551 | 0.738 | tNET | FF | 1 | R13C9[3][A] | disp_dist_1/clkdiv_3/n53_s3/I3 |
6.316 | 0.765 | tINS | FF | 4 | R13C9[3][A] | disp_dist_1/clkdiv_3/n53_s3/F |
6.324 | 0.008 | tNET | FF | 1 | R13C9[2][A] | disp_dist_1/clkdiv_3/n50_s3/I3 |
6.933 | 0.609 | tINS | FF | 3 | R13C9[2][A] | disp_dist_1/clkdiv_3/n50_s3/F |
7.303 | 0.371 | tNET | FF | 1 | R13C7[0][B] | disp_dist_1/clkdiv_3/n48_s3/I2 |
7.898 | 0.594 | tINS | FR | 3 | R13C7[0][B] | disp_dist_1/clkdiv_3/n48_s3/F |
8.212 | 0.315 | tNET | RR | 1 | R13C8[2][B] | disp_dist_1/clkdiv_3/n46_s3/I2 |
9.027 | 0.814 | tINS | RF | 2 | R13C8[2][B] | disp_dist_1/clkdiv_3/n46_s3/F |
9.035 | 0.008 | tNET | FF | 1 | R13C8[2][A] | disp_dist_1/clkdiv_3/n45_s2/I1 |
9.800 | 0.765 | tINS | FF | 1 | R13C8[2][A] | disp_dist_1/clkdiv_3/n45_s2/F |
9.800 | 0.000 | tNET | FF | 1 | R13C8[2][A] | disp_dist_1/clkdiv_3/count_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R13C8[2][A] | disp_dist_1/clkdiv_3/count_16_s0/CLK |
39.009 | -0.296 | tSu | 1 | R13C8[2][A] | disp_dist_1/clkdiv_3/count_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.126, 68.070%; route: 2.065, 27.420%; tC2Q: 0.340, 4.510% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path14
Path Summary:
Slack | 29.213 |
Data Arrival Time | 9.796 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
9.031 | 0.392 | tNET | FF | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/n51_s2/I2 |
9.796 | 0.765 | tINS | FF | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/n51_s2/F |
9.796 | 0.000 | tNET | FF | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/count_10_s0/CLK |
39.009 | -0.296 | tSu | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.474, 72.718%; route: 1.714, 22.770%; tC2Q: 0.340, 4.512% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path15
Path Summary:
Slack | 29.213 |
Data Arrival Time | 9.796 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_12_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
9.031 | 0.392 | tNET | FF | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/n49_s2/I3 |
9.796 | 0.765 | tINS | FF | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/n49_s2/F |
9.796 | 0.000 | tNET | FF | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/count_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/count_12_s0/CLK |
39.009 | -0.296 | tSu | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.474, 72.718%; route: 1.714, 22.770%; tC2Q: 0.340, 4.512% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path16
Path Summary:
Slack | 29.235 |
Data Arrival Time | 9.774 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_15_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.551 | 0.738 | tNET | FF | 1 | R13C9[3][A] | disp_dist_1/clkdiv_3/n53_s3/I3 |
6.316 | 0.765 | tINS | FF | 4 | R13C9[3][A] | disp_dist_1/clkdiv_3/n53_s3/F |
6.324 | 0.008 | tNET | FF | 1 | R13C9[2][A] | disp_dist_1/clkdiv_3/n50_s3/I3 |
6.933 | 0.609 | tINS | FF | 3 | R13C9[2][A] | disp_dist_1/clkdiv_3/n50_s3/F |
7.303 | 0.371 | tNET | FF | 1 | R13C7[0][B] | disp_dist_1/clkdiv_3/n48_s3/I2 |
7.898 | 0.594 | tINS | FR | 3 | R13C7[0][B] | disp_dist_1/clkdiv_3/n48_s3/F |
8.212 | 0.315 | tNET | RR | 1 | R13C8[2][B] | disp_dist_1/clkdiv_3/n46_s3/I2 |
8.999 | 0.786 | tINS | RR | 2 | R13C8[2][B] | disp_dist_1/clkdiv_3/n46_s3/F |
9.310 | 0.312 | tNET | RR | 1 | R13C9[0][B] | disp_dist_1/clkdiv_3/n46_s2/I1 |
9.774 | 0.464 | tINS | RF | 1 | R13C9[0][B] | disp_dist_1/clkdiv_3/n46_s2/F |
9.774 | 0.000 | tNET | FF | 1 | R13C9[0][B] | disp_dist_1/clkdiv_3/count_15_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R13C9[0][B] | disp_dist_1/clkdiv_3/count_15_s0/CLK |
39.009 | -0.296 | tSu | 1 | R13C9[0][B] | disp_dist_1/clkdiv_3/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 4.797, 63.916%; route: 2.369, 31.559%; tC2Q: 0.340, 4.525% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path17
Path Summary:
Slack | 29.239 |
Data Arrival Time | 9.770 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_9_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
9.306 | 0.666 | tNET | FF | 1 | R12C8[2][A] | disp_dist_1/clkdiv_3/n52_s2/I3 |
9.770 | 0.464 | tINS | FF | 1 | R12C8[2][A] | disp_dist_1/clkdiv_3/n52_s2/F |
9.770 | 0.000 | tNET | FF | 1 | R12C8[2][A] | disp_dist_1/clkdiv_3/count_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R12C8[2][A] | disp_dist_1/clkdiv_3/count_9_s0/CLK |
39.009 | -0.296 | tSu | 1 | R12C8[2][A] | disp_dist_1/clkdiv_3/count_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.173, 68.960%; route: 1.989, 26.513%; tC2Q: 0.340, 4.528% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path18
Path Summary:
Slack | 29.297 |
Data Arrival Time | 9.712 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_4_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
8.947 | 0.307 | tNET | FF | 1 | R12C9[2][A] | disp_dist_1/clkdiv_3/n57_s2/I2 |
9.712 | 0.765 | tINS | FF | 1 | R12C9[2][A] | disp_dist_1/clkdiv_3/n57_s2/F |
9.712 | 0.000 | tNET | FF | 1 | R12C9[2][A] | disp_dist_1/clkdiv_3/count_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R12C9[2][A] | disp_dist_1/clkdiv_3/count_4_s0/CLK |
39.009 | -0.296 | tSu | 1 | R12C9[2][A] | disp_dist_1/clkdiv_3/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.474, 73.541%; route: 1.630, 21.896%; tC2Q: 0.340, 4.563% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path19
Path Summary:
Slack | 29.453 |
Data Arrival Time | 9.556 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_5_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
8.947 | 0.307 | tNET | FF | 1 | R12C9[1][B] | disp_dist_1/clkdiv_3/n56_s2/I2 |
9.556 | 0.609 | tINS | FF | 1 | R12C9[1][B] | disp_dist_1/clkdiv_3/n56_s2/F |
9.556 | 0.000 | tNET | FF | 1 | R12C9[1][B] | disp_dist_1/clkdiv_3/count_5_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R12C9[1][B] | disp_dist_1/clkdiv_3/count_5_s0/CLK |
39.009 | -0.296 | tSu | 1 | R12C9[1][B] | disp_dist_1/clkdiv_3/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.318, 72.976%; route: 1.630, 22.363%; tC2Q: 0.340, 4.660% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path20
Path Summary:
Slack | 29.453 |
Data Arrival Time | 9.556 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_7_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
8.947 | 0.307 | tNET | FF | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/n54_s2/I2 |
9.556 | 0.609 | tINS | FF | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/n54_s2/F |
9.556 | 0.000 | tNET | FF | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/count_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/count_7_s0/CLK |
39.009 | -0.296 | tSu | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/count_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.318, 72.976%; route: 1.630, 22.363%; tC2Q: 0.340, 4.660% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path21
Path Summary:
Slack | 29.453 |
Data Arrival Time | 9.556 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_8_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
8.947 | 0.307 | tNET | FF | 1 | R12C9[0][B] | disp_dist_1/clkdiv_3/n53_s2/I2 |
9.556 | 0.609 | tINS | FF | 1 | R12C9[0][B] | disp_dist_1/clkdiv_3/n53_s2/F |
9.556 | 0.000 | tNET | FF | 1 | R12C9[0][B] | disp_dist_1/clkdiv_3/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R12C9[0][B] | disp_dist_1/clkdiv_3/count_8_s0/CLK |
39.009 | -0.296 | tSu | 1 | R12C9[0][B] | disp_dist_1/clkdiv_3/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.318, 72.976%; route: 1.630, 22.363%; tC2Q: 0.340, 4.660% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path22
Path Summary:
Slack | 29.572 |
Data Arrival Time | 9.437 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_11_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
8.672 | 0.033 | tNET | FF | 1 | R13C9[1][B] | disp_dist_1/clkdiv_3/n50_s2/I2 |
9.437 | 0.765 | tINS | FF | 1 | R13C9[1][B] | disp_dist_1/clkdiv_3/n50_s2/F |
9.437 | 0.000 | tNET | FF | 1 | R13C9[1][B] | disp_dist_1/clkdiv_3/count_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R13C9[1][B] | disp_dist_1/clkdiv_3/count_11_s0/CLK |
39.009 | -0.296 | tSu | 1 | R13C9[1][B] | disp_dist_1/clkdiv_3/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.474, 76.360%; route: 1.355, 18.902%; tC2Q: 0.340, 4.738% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path23
Path Summary:
Slack | 29.572 |
Data Arrival Time | 9.437 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_13_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/I0 |
8.640 | 0.814 | tINS | RF | 16 | R13C9[2][B] | disp_dist_1/clkdiv_3/n61_s7/F |
8.672 | 0.033 | tNET | FF | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/n48_s2/I2 |
9.437 | 0.765 | tINS | FF | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/n48_s2/F |
9.437 | 0.000 | tNET | FF | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/count_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/count_13_s0/CLK |
39.009 | -0.296 | tSu | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 8 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 5.474, 76.360%; route: 1.355, 18.902%; tC2Q: 0.340, 4.738% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path24
Path Summary:
Slack | 30.369 |
Data Arrival Time | 8.640 |
Data Required Time | 39.009 |
From | disp_dist_1/clkdiv_3/count_1_s0 |
To | disp_dist_1/clkdiv_3/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
2.088 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
2.269 | 0.181 | tNET | RR | 1 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/CLK |
2.608 | 0.340 | tC2Q | RF | 4 | R12C9[2][B] | disp_dist_1/clkdiv_3/count_1_s0/Q |
3.226 | 0.618 | tNET | FF | 1 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/I0 |
4.040 | 0.814 | tINS | FF | 2 | R12C8[3][B] | disp_dist_1/clkdiv_3/n59_s3/F |
4.048 | 0.008 | tNET | FF | 1 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/I3 |
4.813 | 0.765 | tINS | FF | 5 | R12C8[0][B] | disp_dist_1/clkdiv_3/n56_s3/F |
5.188 | 0.375 | tNET | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/I2 |
5.953 | 0.765 | tINS | FF | 1 | R13C8[3][B] | disp_dist_1/clkdiv_3/n61_s6/F |
5.957 | 0.004 | tNET | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/I1 |
6.722 | 0.765 | tINS | FF | 1 | R13C8[1][B] | disp_dist_1/clkdiv_3/n61_s5/F |
6.726 | 0.004 | tNET | FF | 1 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/I1 |
7.512 | 0.786 | tINS | FR | 2 | R13C8[3][A] | disp_dist_1/clkdiv_3/n61_s4/F |
7.826 | 0.313 | tNET | RR | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/n61_s8/I1 |
8.640 | 0.814 | tINS | RF | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/n61_s8/F |
8.640 | 0.000 | tNET | FF | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/count_0_s0/CLK |
39.009 | -0.296 | tSu | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 37.037 |
Logic Level | 7 |
Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Arrival Data Path Delay | cell: 4.709, 73.913%; route: 1.322, 20.757%; tC2Q: 0.340, 5.331% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path25
Path Summary:
Slack | 31.661 |
Data Arrival Time | 7.319 |
Data Required Time | 38.979 |
From | measure_12_s0 |
To | disp_dist_1/distance_7_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R8C15[2][B] | measure_12_s0/CLK |
1.313 | 0.340 | tC2Q | RR | 11 | R8C15[2][B] | measure_12_s0/Q |
1.628 | 0.315 | tNET | RR | 1 | R8C14[3][A] | disp_dist_1/n15_s19/I1 |
2.414 | 0.786 | tINS | RR | 2 | R8C14[3][A] | disp_dist_1/n15_s19/F |
2.726 | 0.312 | tNET | RR | 1 | R8C13[1][B] | disp_dist_1/n17_s21/I3 |
3.540 | 0.814 | tINS | RF | 5 | R8C13[1][B] | disp_dist_1/n17_s21/F |
4.507 | 0.967 | tNET | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/I2 |
5.321 | 0.814 | tINS | FF | 1 | R8C12[2][B] | disp_dist_1/n17_s22/F |
5.325 | 0.004 | tNET | FF | 1 | R8C12[3][B] | disp_dist_1/n17_s17/I0 |
6.090 | 0.765 | tINS | FF | 3 | R8C12[3][B] | disp_dist_1/n17_s17/F |
6.710 | 0.620 | tNET | FF | 1 | R8C11[1][B] | disp_dist_1/n17_s27/I0 |
7.319 | 0.609 | tINS | FF | 1 | R8C11[1][B] | disp_dist_1/n17_s27/F |
7.319 | 0.000 | tNET | FF | 1 | R8C11[1][B] | disp_dist_1/distance_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
37.037 | 37.037 | active clock edge time | ||||
37.037 | 0.000 | clk27mhz | ||||
37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
39.125 | 2.088 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
39.306 | 0.181 | tNET | RR | 1 | R8C11[1][B] | disp_dist_1/distance_7_s0/CLK |
39.276 | -0.030 | tUnc | disp_dist_1/distance_7_s0 | |||
38.979 | -0.296 | tSu | 1 | R8C11[1][B] | disp_dist_1/distance_7_s0 |
Path Statistics:
Clock Skew | 1.296 |
Setup Relationship | 37.037 |
Logic Level | 6 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 3.789, 59.705%; route: 2.217, 34.943%; tC2Q: 0.340, 5.352% |
Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.097 |
Data Arrival Time | 1.655 |
Data Required Time | 1.559 |
From | measure_12_s0 |
To | disp_dist_1/distance_10_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R8C15[2][B] | measure_12_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 11 | R8C15[2][B] | measure_12_s0/Q |
1.380 | 0.431 | tNET | RR | 1 | R9C13[0][A] | disp_dist_1/n14_s10/I1 |
1.655 | 0.276 | tINS | RF | 1 | R9C13[0][A] | disp_dist_1/n14_s10/F |
1.655 | 0.000 | tNET | FF | 1 | R9C13[0][A] | disp_dist_1/distance_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R9C13[0][A] | disp_dist_1/distance_10_s0/CLK |
1.559 | 0.030 | tUnc | disp_dist_1/distance_10_s0 | |||
1.559 | 0.000 | tHld | 1 | R9C13[0][A] | disp_dist_1/distance_10_s0 |
Path Statistics:
Clock Skew | 0.827 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.276, 28.903%; route: 0.431, 45.197%; tC2Q: 0.247, 25.899% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path2
Path Summary:
Slack | 0.204 |
Data Arrival Time | 1.762 |
Data Required Time | 1.559 |
From | measure_7_s0 |
To | disp_dist_1/distance_6_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C13[1][A] | measure_7_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 9 | R7C13[1][A] | measure_7_s0/Q |
1.350 | 0.402 | tNET | RR | 1 | R9C11[2][A] | disp_dist_1/n18_s28/I0 |
1.762 | 0.412 | tINS | RR | 1 | R9C11[2][A] | disp_dist_1/n18_s28/F |
1.762 | 0.000 | tNET | RR | 1 | R9C11[2][A] | disp_dist_1/distance_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R9C11[2][A] | disp_dist_1/distance_6_s0/CLK |
1.559 | 0.030 | tUnc | disp_dist_1/distance_6_s0 | |||
1.559 | 0.000 | tHld | 1 | R9C11[2][A] | disp_dist_1/distance_6_s0 |
Path Statistics:
Clock Skew | 0.827 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.412, 38.837%; route: 0.402, 37.879%; tC2Q: 0.247, 23.284% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path3
Path Summary:
Slack | 0.310 |
Data Arrival Time | 1.869 |
Data Required Time | 1.559 |
From | measure_15_s0 |
To | disp_dist_1/distance_9_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R8C15[1][B] | measure_15_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 12 | R8C15[1][B] | measure_15_s0/Q |
1.331 | 0.383 | tNET | RR | 1 | R8C13[0][A] | disp_dist_1/n15_s17/I2 |
1.869 | 0.538 | tINS | RR | 1 | R8C13[0][A] | disp_dist_1/n15_s17/F |
1.869 | 0.000 | tNET | RR | 1 | R8C13[0][A] | disp_dist_1/distance_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R8C13[0][A] | disp_dist_1/distance_9_s0/CLK |
1.559 | 0.030 | tUnc | disp_dist_1/distance_9_s0 | |||
1.559 | 0.000 | tHld | 1 | R8C13[0][A] | disp_dist_1/distance_9_s0 |
Path Statistics:
Clock Skew | 0.827 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.538, 46.079%; route: 0.383, 32.764%; tC2Q: 0.247, 21.157% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path4
Path Summary:
Slack | 0.328 |
Data Arrival Time | 1.887 |
Data Required Time | 1.559 |
From | measure_9_s0 |
To | disp_dist_1/distance_7_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R8C14[0][A] | measure_9_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 9 | R8C14[0][A] | measure_9_s0/Q |
1.151 | 0.203 | tNET | RR | 1 | R8C12[0][B] | disp_dist_1/n17_s18/I1 |
1.427 | 0.276 | tINS | RF | 4 | R8C12[0][B] | disp_dist_1/n17_s18/F |
1.611 | 0.184 | tNET | FF | 1 | R8C11[1][B] | disp_dist_1/n17_s27/I2 |
1.887 | 0.276 | tINS | FF | 1 | R8C11[1][B] | disp_dist_1/n17_s27/F |
1.887 | 0.000 | tNET | FF | 1 | R8C11[1][B] | disp_dist_1/distance_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R8C11[1][B] | disp_dist_1/distance_7_s0/CLK |
1.559 | 0.030 | tUnc | disp_dist_1/distance_7_s0 | |||
1.559 | 0.000 | tHld | 1 | R8C11[1][B] | disp_dist_1/distance_7_s0 |
Path Statistics:
Clock Skew | 0.827 |
Hold Relationship | 0.000 |
Logic Level | 3 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.551, 46.525%; route: 0.387, 32.630%; tC2Q: 0.247, 20.845% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path5
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.226 |
Data Required Time | 0.702 |
From | dlkdiv_2/count_3_s0 |
To | dlkdiv_2/count_3_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R14C15[0][A] | dlkdiv_2/count_3_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 2 | R14C15[0][A] | dlkdiv_2/count_3_s0/Q |
0.950 | 0.002 | tNET | RR | 1 | R14C15[0][A] | dlkdiv_2/n58_s2/I2 |
1.226 | 0.276 | tINS | RF | 1 | R14C15[0][A] | dlkdiv_2/n58_s2/F |
1.226 | 0.000 | tNET | FF | 1 | R14C15[0][A] | dlkdiv_2/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R14C15[0][A] | dlkdiv_2/count_3_s0/CLK |
0.702 | 0.000 | tHld | 1 | R14C15[0][A] | dlkdiv_2/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path6
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.226 |
Data Required Time | 0.702 |
From | dlkdiv_2/count_13_s0 |
To | dlkdiv_2/count_13_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R14C13[1][A] | dlkdiv_2/count_13_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 3 | R14C13[1][A] | dlkdiv_2/count_13_s0/Q |
0.950 | 0.002 | tNET | RR | 1 | R14C13[1][A] | dlkdiv_2/n48_s2/I2 |
1.226 | 0.276 | tINS | RF | 1 | R14C13[1][A] | dlkdiv_2/n48_s2/F |
1.226 | 0.000 | tNET | FF | 1 | R14C13[1][A] | dlkdiv_2/count_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R14C13[1][A] | dlkdiv_2/count_13_s0/CLK |
0.702 | 0.000 | tHld | 1 | R14C13[1][A] | dlkdiv_2/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path7
Path Summary:
Slack | 0.524 |
Data Arrival Time | 1.226 |
Data Required Time | 0.702 |
From | trig_count_3_s1 |
To | trig_count_3_s1 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R8C15[0][A] | trig_count_3_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 2 | R8C15[0][A] | trig_count_3_s1/Q |
0.950 | 0.002 | tNET | RR | 1 | R8C15[0][A] | n173_s2/I1 |
1.226 | 0.276 | tINS | RF | 1 | R8C15[0][A] | n173_s2/F |
1.226 | 0.000 | tNET | FF | 1 | R8C15[0][A] | trig_count_3_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R8C15[0][A] | trig_count_3_s1/CLK |
0.702 | 0.000 | tHld | 1 | R8C15[0][A] | trig_count_3_s1 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path8
Path Summary:
Slack | 0.524 |
Data Arrival Time | 2.053 |
Data Required Time | 1.529 |
From | disp_dist_1/clkdiv_3/count_0_s0 |
To | disp_dist_1/clkdiv_3/count_0_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/count_0_s0/CLK |
1.776 | 0.247 | tC2Q | RR | 5 | R13C9[0][A] | disp_dist_1/clkdiv_3/count_0_s0/Q |
1.778 | 0.002 | tNET | RR | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/n61_s8/I0 |
2.053 | 0.276 | tINS | RF | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/n61_s8/F |
2.053 | 0.000 | tNET | FF | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/count_0_s0/CLK |
1.529 | 0.000 | tHld | 1 | R13C9[0][A] | disp_dist_1/clkdiv_3/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path9
Path Summary:
Slack | 0.524 |
Data Arrival Time | 2.053 |
Data Required Time | 1.529 |
From | disp_dist_1/clkdiv_3/count_3_s0 |
To | disp_dist_1/clkdiv_3/count_3_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/count_3_s0/CLK |
1.776 | 0.247 | tC2Q | RR | 3 | R12C7[0][A] | disp_dist_1/clkdiv_3/count_3_s0/Q |
1.778 | 0.002 | tNET | RR | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/n58_s2/I2 |
2.053 | 0.276 | tINS | RF | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/n58_s2/F |
2.053 | 0.000 | tNET | FF | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/count_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/count_3_s0/CLK |
1.529 | 0.000 | tHld | 1 | R12C7[0][A] | disp_dist_1/clkdiv_3/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path10
Path Summary:
Slack | 0.524 |
Data Arrival Time | 2.053 |
Data Required Time | 1.529 |
From | disp_dist_1/clkdiv_3/count_12_s0 |
To | disp_dist_1/clkdiv_3/count_12_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/count_12_s0/CLK |
1.776 | 0.247 | tC2Q | RR | 3 | R13C7[1][A] | disp_dist_1/clkdiv_3/count_12_s0/Q |
1.778 | 0.002 | tNET | RR | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/n49_s2/I2 |
2.053 | 0.276 | tINS | RF | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/n49_s2/F |
2.053 | 0.000 | tNET | FF | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/count_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/count_12_s0/CLK |
1.529 | 0.000 | tHld | 1 | R13C7[1][A] | disp_dist_1/clkdiv_3/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path11
Path Summary:
Slack | 0.525 |
Data Arrival Time | 1.227 |
Data Required Time | 0.702 |
From | counter16_1/count_0_s0 |
To | counter16_1/count_0_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C13[0][A] | counter16_1/count_0_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 3 | R7C13[0][A] | counter16_1/count_0_s0/Q |
0.951 | 0.003 | tNET | RR | 1 | R7C13[0][A] | counter16_1/n40_s2/I0 |
1.227 | 0.276 | tINS | RF | 1 | R7C13[0][A] | counter16_1/n40_s2/F |
1.227 | 0.000 | tNET | FF | 1 | R7C13[0][A] | counter16_1/count_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C13[0][A] | counter16_1/count_0_s0/CLK |
0.702 | 0.000 | tHld | 1 | R7C13[0][A] | counter16_1/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path12
Path Summary:
Slack | 0.525 |
Data Arrival Time | 2.054 |
Data Required Time | 1.529 |
From | disp_dist_1/clkdiv_3/count_6_s0 |
To | disp_dist_1/clkdiv_3/count_6_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/count_6_s0/CLK |
1.776 | 0.247 | tC2Q | RR | 5 | R12C8[0][A] | disp_dist_1/clkdiv_3/count_6_s0/Q |
1.778 | 0.003 | tNET | RR | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/n55_s2/I2 |
2.054 | 0.276 | tINS | RF | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/n55_s2/F |
2.054 | 0.000 | tNET | FF | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/count_6_s0/CLK |
1.529 | 0.000 | tHld | 1 | R12C8[0][A] | disp_dist_1/clkdiv_3/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path13
Path Summary:
Slack | 0.525 |
Data Arrival Time | 2.054 |
Data Required Time | 1.529 |
From | disp_dist_1/clkdiv_3/count_7_s0 |
To | disp_dist_1/clkdiv_3/count_7_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/count_7_s0/CLK |
1.776 | 0.247 | tC2Q | RR | 4 | R12C9[1][A] | disp_dist_1/clkdiv_3/count_7_s0/Q |
1.778 | 0.003 | tNET | RR | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/n54_s2/I1 |
2.054 | 0.276 | tINS | RF | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/n54_s2/F |
2.054 | 0.000 | tNET | FF | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/count_7_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/count_7_s0/CLK |
1.529 | 0.000 | tHld | 1 | R12C9[1][A] | disp_dist_1/clkdiv_3/count_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path14
Path Summary:
Slack | 0.525 |
Data Arrival Time | 2.054 |
Data Required Time | 1.529 |
From | disp_dist_1/clkdiv_3/count_10_s0 |
To | disp_dist_1/clkdiv_3/count_10_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/count_10_s0/CLK |
1.776 | 0.247 | tC2Q | RR | 4 | R12C9[0][A] | disp_dist_1/clkdiv_3/count_10_s0/Q |
1.778 | 0.003 | tNET | RR | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/n51_s2/I1 |
2.054 | 0.276 | tINS | RF | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/n51_s2/F |
2.054 | 0.000 | tNET | FF | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/count_10_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/count_10_s0/CLK |
1.529 | 0.000 | tHld | 1 | R12C9[0][A] | disp_dist_1/clkdiv_3/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path15
Path Summary:
Slack | 0.525 |
Data Arrival Time | 2.054 |
Data Required Time | 1.529 |
From | disp_dist_1/clkdiv_3/count_13_s0 |
To | disp_dist_1/clkdiv_3/count_13_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/count_13_s0/CLK |
1.776 | 0.247 | tC2Q | RR | 4 | R13C9[1][A] | disp_dist_1/clkdiv_3/count_13_s0/Q |
1.778 | 0.003 | tNET | RR | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/n48_s2/I0 |
2.054 | 0.276 | tINS | RF | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/n48_s2/F |
2.054 | 0.000 | tNET | FF | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/count_13_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/count_13_s0/CLK |
1.529 | 0.000 | tHld | 1 | R13C9[1][A] | disp_dist_1/clkdiv_3/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path16
Path Summary:
Slack | 0.525 |
Data Arrival Time | 2.054 |
Data Required Time | 1.529 |
From | disp_dist_1/clkdiv_3/count_14_s0 |
To | disp_dist_1/clkdiv_3/count_14_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/count_14_s0/CLK |
1.776 | 0.247 | tC2Q | RR | 4 | R13C8[0][A] | disp_dist_1/clkdiv_3/count_14_s0/Q |
1.778 | 0.003 | tNET | RR | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/n47_s2/I2 |
2.054 | 0.276 | tINS | RF | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/n47_s2/F |
2.054 | 0.000 | tNET | FF | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/count_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/count_14_s0/CLK |
1.529 | 0.000 | tHld | 1 | R13C8[0][A] | disp_dist_1/clkdiv_3/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path17
Path Summary:
Slack | 0.525 |
Data Arrival Time | 2.054 |
Data Required Time | 1.529 |
From | clkdiv_1/count_1_s0 |
To | clkdiv_1/count_1_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C10[0][A] | clkdiv_1/count_1_s0/CLK |
1.776 | 0.247 | tC2Q | RR | 7 | R13C10[0][A] | clkdiv_1/count_1_s0/Q |
1.778 | 0.003 | tNET | RR | 1 | R13C10[0][A] | clkdiv_1/n60_s2/I0 |
2.054 | 0.276 | tINS | RF | 1 | R13C10[0][A] | clkdiv_1/n60_s2/F |
2.054 | 0.000 | tNET | FF | 1 | R13C10[0][A] | clkdiv_1/count_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C10[0][A] | clkdiv_1/count_1_s0/CLK |
1.529 | 0.000 | tHld | 1 | R13C10[0][A] | clkdiv_1/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path18
Path Summary:
Slack | 0.525 |
Data Arrival Time | 2.054 |
Data Required Time | 1.529 |
From | clkdiv_1/count_2_s0 |
To | clkdiv_1/count_2_s0 |
Launch Clk | clk27mhz:[R] |
Latch Clk | clk27mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C10[1][A] | clkdiv_1/count_2_s0/CLK |
1.776 | 0.247 | tC2Q | RR | 6 | R13C10[1][A] | clkdiv_1/count_2_s0/Q |
1.778 | 0.003 | tNET | RR | 1 | R13C10[1][A] | clkdiv_1/n59_s2/I2 |
2.054 | 0.276 | tINS | RF | 1 | R13C10[1][A] | clkdiv_1/n59_s2/F |
2.054 | 0.000 | tNET | FF | 1 | R13C10[1][A] | clkdiv_1/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk27mhz | ||||
0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
1.392 | 1.392 | tINS | RR | 35 | IOL6[A] | clk_ibuf/O |
1.529 | 0.137 | tNET | RR | 1 | R13C10[1][A] | clkdiv_1/count_2_s0/CLK |
1.529 | 0.000 | tHld | 1 | R13C10[1][A] | clkdiv_1/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path19
Path Summary:
Slack | 0.527 |
Data Arrival Time | 1.229 |
Data Required Time | 0.702 |
From | state_1_s0 |
To | state_1_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C15[0][A] | state_1_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 7 | R9C15[0][A] | state_1_s0/Q |
0.953 | 0.004 | tNET | RR | 1 | R9C15[0][A] | n178_s7/I2 |
1.229 | 0.276 | tINS | RF | 1 | R9C15[0][A] | n178_s7/F |
1.229 | 0.000 | tNET | FF | 1 | R9C15[0][A] | state_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C15[0][A] | state_1_s0/CLK |
0.702 | 0.000 | tHld | 1 | R9C15[0][A] | state_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path20
Path Summary:
Slack | 0.528 |
Data Arrival Time | 1.477 |
Data Required Time | 0.949 |
From | disp_dist_1/mux7seg_1/col_1_s0 |
To | disp_dist_1/mux7seg_1/col_1_s0 |
Launch Clk | clk270hz:[R] |
Latch Clk | clk270hz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk270hz | ||||
0.000 | 0.000 | tCL | RR | 13 | R13C8[1][A] | disp_dist_1/clkdiv_3/clk_out_s0/Q |
0.949 | 0.949 | tNET | RR | 1 | R11C7[0][A] | disp_dist_1/mux7seg_1/col_1_s0/CLK |
1.196 | 0.247 | tC2Q | RR | 11 | R11C7[0][A] | disp_dist_1/mux7seg_1/col_1_s0/Q |
1.201 | 0.005 | tNET | RR | 1 | R11C7[0][A] | disp_dist_1/mux7seg_1/n11_s2/I1 |
1.477 | 0.276 | tINS | RF | 1 | R11C7[0][A] | disp_dist_1/mux7seg_1/n11_s2/F |
1.477 | 0.000 | tNET | FF | 1 | R11C7[0][A] | disp_dist_1/mux7seg_1/col_1_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk270hz | ||||
0.000 | 0.000 | tCL | RR | 13 | R13C8[1][A] | disp_dist_1/clkdiv_3/clk_out_s0/Q |
0.949 | 0.949 | tNET | RR | 1 | R11C7[0][A] | disp_dist_1/mux7seg_1/col_1_s0/CLK |
0.949 | 0.000 | tHld | 1 | R11C7[0][A] | disp_dist_1/mux7seg_1/col_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.949, 100.000% |
Arrival Data Path Delay | cell: 0.276, 52.217%; route: 0.005, 0.994%; tC2Q: 0.247, 46.789% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.949, 100.000% |
Path21
Path Summary:
Slack | 0.542 |
Data Arrival Time | 1.243 |
Data Required Time | 0.702 |
From | counter16_1/count_2_s0 |
To | counter16_1/count_2_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C14[1][A] | counter16_1/count_2_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 3 | R7C14[1][A] | counter16_1/count_2_s0/Q |
0.951 | 0.003 | tNET | RR | 2 | R7C14[1][A] | counter16_1/n38_s/I1 |
1.243 | 0.292 | tINS | RF | 1 | R7C14[1][A] | counter16_1/n38_s/SUM |
1.243 | 0.000 | tNET | FF | 1 | R7C14[1][A] | counter16_1/count_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C14[1][A] | counter16_1/count_2_s0/CLK |
0.702 | 0.000 | tHld | 1 | R7C14[1][A] | counter16_1/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.292, 53.908%; route: 0.003, 0.485%; tC2Q: 0.247, 45.607% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path22
Path Summary:
Slack | 0.542 |
Data Arrival Time | 1.243 |
Data Required Time | 0.702 |
From | counter16_1/count_6_s0 |
To | counter16_1/count_6_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C15[0][A] | counter16_1/count_6_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 3 | R7C15[0][A] | counter16_1/count_6_s0/Q |
0.951 | 0.003 | tNET | RR | 2 | R7C15[0][A] | counter16_1/n34_s/I1 |
1.243 | 0.292 | tINS | RF | 1 | R7C15[0][A] | counter16_1/n34_s/SUM |
1.243 | 0.000 | tNET | FF | 1 | R7C15[0][A] | counter16_1/count_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C15[0][A] | counter16_1/count_6_s0/CLK |
0.702 | 0.000 | tHld | 1 | R7C15[0][A] | counter16_1/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.292, 53.908%; route: 0.003, 0.485%; tC2Q: 0.247, 45.607% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path23
Path Summary:
Slack | 0.542 |
Data Arrival Time | 1.243 |
Data Required Time | 0.702 |
From | counter16_1/count_8_s0 |
To | counter16_1/count_8_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C15[1][A] | counter16_1/count_8_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 3 | R7C15[1][A] | counter16_1/count_8_s0/Q |
0.951 | 0.003 | tNET | RR | 2 | R7C15[1][A] | counter16_1/n32_s/I1 |
1.243 | 0.292 | tINS | RF | 1 | R7C15[1][A] | counter16_1/n32_s/SUM |
1.243 | 0.000 | tNET | FF | 1 | R7C15[1][A] | counter16_1/count_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C15[1][A] | counter16_1/count_8_s0/CLK |
0.702 | 0.000 | tHld | 1 | R7C15[1][A] | counter16_1/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.292, 53.908%; route: 0.003, 0.485%; tC2Q: 0.247, 45.607% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path24
Path Summary:
Slack | 0.542 |
Data Arrival Time | 1.243 |
Data Required Time | 0.702 |
From | counter16_1/count_12_s0 |
To | counter16_1/count_12_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C16[0][A] | counter16_1/count_12_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 3 | R7C16[0][A] | counter16_1/count_12_s0/Q |
0.951 | 0.003 | tNET | RR | 2 | R7C16[0][A] | counter16_1/n28_s/I1 |
1.243 | 0.292 | tINS | RF | 1 | R7C16[0][A] | counter16_1/n28_s/SUM |
1.243 | 0.000 | tNET | FF | 1 | R7C16[0][A] | counter16_1/count_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C16[0][A] | counter16_1/count_12_s0/CLK |
0.702 | 0.000 | tHld | 1 | R7C16[0][A] | counter16_1/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.292, 53.908%; route: 0.003, 0.485%; tC2Q: 0.247, 45.607% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path25
Path Summary:
Slack | 0.542 |
Data Arrival Time | 1.243 |
Data Required Time | 0.702 |
From | counter16_1/count_14_s0 |
To | counter16_1/count_14_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C16[1][A] | counter16_1/count_14_s0/CLK |
0.949 | 0.247 | tC2Q | RR | 3 | R7C16[1][A] | counter16_1/count_14_s0/Q |
0.951 | 0.003 | tNET | RR | 2 | R7C16[1][A] | counter16_1/n26_s/I1 |
1.243 | 0.292 | tINS | RF | 1 | R7C16[1][A] | counter16_1/n26_s/SUM |
1.243 | 0.000 | tNET | FF | 1 | R7C16[1][A] | counter16_1/count_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C16[1][A] | counter16_1/count_14_s0/CLK |
0.702 | 0.000 | tHld | 1 | R7C16[1][A] | counter16_1/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.292, 53.908%; route: 0.003, 0.485%; tC2Q: 0.247, 45.607% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 998.641 |
Data Arrival Time | 2.299 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_12_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
2.299 | 0.986 | tNET | FF | 1 | R7C16[0][A] | counter16_1/count_12_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C16[0][A] | counter16_1/count_12_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C16[0][A] | counter16_1/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.986, 74.381%; tC2Q: 0.340, 25.619% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path2
Path Summary:
Slack | 998.641 |
Data Arrival Time | 2.299 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_13_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
2.299 | 0.986 | tNET | FF | 1 | R7C16[0][B] | counter16_1/count_13_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C16[0][B] | counter16_1/count_13_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C16[0][B] | counter16_1/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.986, 74.381%; tC2Q: 0.340, 25.619% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path3
Path Summary:
Slack | 998.641 |
Data Arrival Time | 2.299 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_14_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
2.299 | 0.986 | tNET | FF | 1 | R7C16[1][A] | counter16_1/count_14_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C16[1][A] | counter16_1/count_14_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C16[1][A] | counter16_1/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.986, 74.381%; tC2Q: 0.340, 25.619% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path4
Path Summary:
Slack | 998.641 |
Data Arrival Time | 2.299 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_15_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
2.299 | 0.986 | tNET | FF | 1 | R7C16[1][B] | counter16_1/count_15_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C16[1][B] | counter16_1/count_15_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C16[1][B] | counter16_1/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.986, 74.381%; tC2Q: 0.340, 25.619% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path5
Path Summary:
Slack | 998.664 |
Data Arrival Time | 2.276 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/ov_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
2.276 | 0.963 | tNET | FF | 1 | R6C15[0][A] | counter16_1/ov_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R6C15[0][A] | counter16_1/ov_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R6C15[0][A] | counter16_1/ov_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.963, 73.931%; tC2Q: 0.340, 26.069% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path6
Path Summary:
Slack | 998.993 |
Data Arrival Time | 1.947 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_1_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.947 | 0.634 | tNET | FF | 1 | R7C14[0][B] | counter16_1/count_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C14[0][B] | counter16_1/count_1_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C14[0][B] | counter16_1/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.634, 65.126%; tC2Q: 0.340, 34.874% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path7
Path Summary:
Slack | 998.993 |
Data Arrival Time | 1.947 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_2_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.947 | 0.634 | tNET | FF | 1 | R7C14[1][A] | counter16_1/count_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C14[1][A] | counter16_1/count_2_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C14[1][A] | counter16_1/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.634, 65.126%; tC2Q: 0.340, 34.874% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path8
Path Summary:
Slack | 998.993 |
Data Arrival Time | 1.947 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_3_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.947 | 0.634 | tNET | FF | 1 | R7C14[1][B] | counter16_1/count_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C14[1][B] | counter16_1/count_3_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C14[1][B] | counter16_1/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.634, 65.126%; tC2Q: 0.340, 34.874% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path9
Path Summary:
Slack | 998.993 |
Data Arrival Time | 1.947 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_4_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.947 | 0.634 | tNET | FF | 1 | R7C14[2][A] | counter16_1/count_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C14[2][A] | counter16_1/count_4_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C14[2][A] | counter16_1/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.634, 65.126%; tC2Q: 0.340, 34.874% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path10
Path Summary:
Slack | 998.993 |
Data Arrival Time | 1.947 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_5_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.947 | 0.634 | tNET | FF | 1 | R7C14[2][B] | counter16_1/count_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C14[2][B] | counter16_1/count_5_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C14[2][B] | counter16_1/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.634, 65.126%; tC2Q: 0.340, 34.874% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path11
Path Summary:
Slack | 999.016 |
Data Arrival Time | 1.923 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_6_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.923 | 0.611 | tNET | FF | 1 | R7C15[0][A] | counter16_1/count_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C15[0][A] | counter16_1/count_6_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C15[0][A] | counter16_1/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.611, 64.268%; tC2Q: 0.340, 35.732% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path12
Path Summary:
Slack | 999.016 |
Data Arrival Time | 1.923 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_7_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.923 | 0.611 | tNET | FF | 1 | R7C15[0][B] | counter16_1/count_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C15[0][B] | counter16_1/count_7_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C15[0][B] | counter16_1/count_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.611, 64.268%; tC2Q: 0.340, 35.732% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path13
Path Summary:
Slack | 999.016 |
Data Arrival Time | 1.923 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_8_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.923 | 0.611 | tNET | FF | 1 | R7C15[1][A] | counter16_1/count_8_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C15[1][A] | counter16_1/count_8_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C15[1][A] | counter16_1/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.611, 64.268%; tC2Q: 0.340, 35.732% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path14
Path Summary:
Slack | 999.016 |
Data Arrival Time | 1.923 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_9_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.923 | 0.611 | tNET | FF | 1 | R7C15[1][B] | counter16_1/count_9_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C15[1][B] | counter16_1/count_9_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C15[1][B] | counter16_1/count_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.611, 64.268%; tC2Q: 0.340, 35.732% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path15
Path Summary:
Slack | 999.016 |
Data Arrival Time | 1.923 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_10_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.923 | 0.611 | tNET | FF | 1 | R7C15[2][A] | counter16_1/count_10_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C15[2][A] | counter16_1/count_10_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C15[2][A] | counter16_1/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.611, 64.268%; tC2Q: 0.340, 35.732% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path16
Path Summary:
Slack | 999.016 |
Data Arrival Time | 1.923 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_11_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.923 | 0.611 | tNET | FF | 1 | R7C15[2][B] | counter16_1/count_11_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C15[2][B] | counter16_1/count_11_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C15[2][B] | counter16_1/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.611, 64.268%; tC2Q: 0.340, 35.732% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Path17
Path Summary:
Slack | 999.023 |
Data Arrival Time | 1.917 |
Data Required Time | 1000.940 |
From | count_nrst_s1 |
To | counter16_1/count_0_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.973 | 0.973 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
1.313 | 0.340 | tC2Q | RF | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.917 | 0.604 | tNET | FF | 1 | R7C13[0][A] | counter16_1/count_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
999.999 | 999.999 | active clock edge time | ||||
999.999 | 0.000 | clk1mhz | ||||
999.999 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
1000.972 | 0.973 | tNET | RR | 1 | R7C13[0][A] | counter16_1/count_0_s0/CLK |
1000.940 | -0.032 | tSu | 1 | R7C13[0][A] | counter16_1/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 999.999 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.604, 64.012%; tC2Q: 0.340, 35.988% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.973, 100.000% |
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 0.623 |
Data Arrival Time | 1.334 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_1_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.334 | 0.385 | tNET | RR | 1 | R7C14[0][B] | counter16_1/count_1_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C14[0][B] | counter16_1/count_1_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C14[0][B] | counter16_1/count_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.385, 60.931%; tC2Q: 0.247, 39.069% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path2
Path Summary:
Slack | 0.623 |
Data Arrival Time | 1.334 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_2_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.334 | 0.385 | tNET | RR | 1 | R7C14[1][A] | counter16_1/count_2_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C14[1][A] | counter16_1/count_2_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C14[1][A] | counter16_1/count_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.385, 60.931%; tC2Q: 0.247, 39.069% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path3
Path Summary:
Slack | 0.623 |
Data Arrival Time | 1.334 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_3_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.334 | 0.385 | tNET | RR | 1 | R7C14[1][B] | counter16_1/count_3_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C14[1][B] | counter16_1/count_3_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C14[1][B] | counter16_1/count_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.385, 60.931%; tC2Q: 0.247, 39.069% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path4
Path Summary:
Slack | 0.623 |
Data Arrival Time | 1.334 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_4_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.334 | 0.385 | tNET | RR | 1 | R7C14[2][A] | counter16_1/count_4_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C14[2][A] | counter16_1/count_4_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C14[2][A] | counter16_1/count_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.385, 60.931%; tC2Q: 0.247, 39.069% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path5
Path Summary:
Slack | 0.623 |
Data Arrival Time | 1.334 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_5_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.334 | 0.385 | tNET | RR | 1 | R7C14[2][B] | counter16_1/count_5_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C14[2][B] | counter16_1/count_5_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C14[2][B] | counter16_1/count_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.385, 60.931%; tC2Q: 0.247, 39.069% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path6
Path Summary:
Slack | 0.663 |
Data Arrival Time | 1.374 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_0_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.374 | 0.425 | tNET | RR | 1 | R7C13[0][A] | counter16_1/count_0_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C13[0][A] | counter16_1/count_0_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C13[0][A] | counter16_1/count_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.425, 63.259%; tC2Q: 0.247, 36.741% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path7
Path Summary:
Slack | 0.669 |
Data Arrival Time | 1.379 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_6_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.379 | 0.431 | tNET | RR | 1 | R7C15[0][A] | counter16_1/count_6_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C15[0][A] | counter16_1/count_6_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C15[0][A] | counter16_1/count_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.431, 63.561%; tC2Q: 0.247, 36.439% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path8
Path Summary:
Slack | 0.669 |
Data Arrival Time | 1.379 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_7_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.379 | 0.431 | tNET | RR | 1 | R7C15[0][B] | counter16_1/count_7_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C15[0][B] | counter16_1/count_7_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C15[0][B] | counter16_1/count_7_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.431, 63.561%; tC2Q: 0.247, 36.439% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path9
Path Summary:
Slack | 0.669 |
Data Arrival Time | 1.379 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_8_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.379 | 0.431 | tNET | RR | 1 | R7C15[1][A] | counter16_1/count_8_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C15[1][A] | counter16_1/count_8_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C15[1][A] | counter16_1/count_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.431, 63.561%; tC2Q: 0.247, 36.439% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path10
Path Summary:
Slack | 0.669 |
Data Arrival Time | 1.379 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_9_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.379 | 0.431 | tNET | RR | 1 | R7C15[1][B] | counter16_1/count_9_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C15[1][B] | counter16_1/count_9_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C15[1][B] | counter16_1/count_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.431, 63.561%; tC2Q: 0.247, 36.439% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path11
Path Summary:
Slack | 0.669 |
Data Arrival Time | 1.379 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_10_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.379 | 0.431 | tNET | RR | 1 | R7C15[2][A] | counter16_1/count_10_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C15[2][A] | counter16_1/count_10_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C15[2][A] | counter16_1/count_10_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.431, 63.561%; tC2Q: 0.247, 36.439% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path12
Path Summary:
Slack | 0.669 |
Data Arrival Time | 1.379 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_11_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.379 | 0.431 | tNET | RR | 1 | R7C15[2][B] | counter16_1/count_11_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C15[2][B] | counter16_1/count_11_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C15[2][B] | counter16_1/count_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.431, 63.561%; tC2Q: 0.247, 36.439% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path13
Path Summary:
Slack | 0.814 |
Data Arrival Time | 1.525 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_12_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.525 | 0.576 | tNET | RR | 1 | R7C16[0][A] | counter16_1/count_12_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C16[0][A] | counter16_1/count_12_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C16[0][A] | counter16_1/count_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.576, 69.990%; tC2Q: 0.247, 30.010% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path14
Path Summary:
Slack | 0.814 |
Data Arrival Time | 1.525 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_13_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.525 | 0.576 | tNET | RR | 1 | R7C16[0][B] | counter16_1/count_13_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C16[0][B] | counter16_1/count_13_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C16[0][B] | counter16_1/count_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.576, 69.990%; tC2Q: 0.247, 30.010% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path15
Path Summary:
Slack | 0.814 |
Data Arrival Time | 1.525 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_14_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.525 | 0.576 | tNET | RR | 1 | R7C16[1][A] | counter16_1/count_14_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C16[1][A] | counter16_1/count_14_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C16[1][A] | counter16_1/count_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.576, 69.990%; tC2Q: 0.247, 30.010% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path16
Path Summary:
Slack | 0.814 |
Data Arrival Time | 1.525 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/count_15_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.525 | 0.576 | tNET | RR | 1 | R7C16[1][B] | counter16_1/count_15_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R7C16[1][B] | counter16_1/count_15_s0/CLK |
0.711 | 0.009 | tHld | 1 | R7C16[1][B] | counter16_1/count_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.576, 69.990%; tC2Q: 0.247, 30.010% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Path17
Path Summary:
Slack | 0.858 |
Data Arrival Time | 1.569 |
Data Required Time | 0.711 |
From | count_nrst_s1 |
To | counter16_1/ov_s0 |
Launch Clk | clk1mhz:[R] |
Latch Clk | clk1mhz:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R9C14[0][A] | count_nrst_s1/CLK |
0.949 | 0.247 | tC2Q | RR | 17 | R9C14[0][A] | count_nrst_s1/Q |
1.569 | 0.621 | tNET | RR | 1 | R6C15[0][A] | counter16_1/ov_s0/CLEAR |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clk1mhz | ||||
0.000 | 0.000 | tCL | RR | 60 | R14C10[0][A] | clkdiv_1/clk_out_s0/Q |
0.702 | 0.702 | tNET | RR | 1 | R6C15[0][A] | counter16_1/ov_s0/CLK |
0.711 | 0.009 | tHld | 1 | R6C15[0][A] | counter16_1/ov_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 1 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Arrival Data Path Delay | cell: 0.000, 0.000%; route: 0.621, 71.535%; tC2Q: 0.247, 28.465% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.702, 100.000% |
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 16.613 |
Actual Width: | 17.539 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.026 | 0.195 | tNET | FF | clkdiv_1/count_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.566 | 0.137 | tNET | RR | clkdiv_1/count_4_s0/CLK |
MPW2
MPW Summary:
Slack: | 16.613 |
Actual Width: | 17.539 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/count_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.026 | 0.195 | tNET | FF | clkdiv_1/count_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.566 | 0.137 | tNET | RR | clkdiv_1/count_2_s0/CLK |
MPW3
MPW Summary:
Slack: | 16.613 |
Actual Width: | 17.539 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | disp_dist_1/distance_10_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.026 | 0.195 | tNET | FF | disp_dist_1/distance_10_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.566 | 0.137 | tNET | RR | disp_dist_1/distance_10_s0/CLK |
MPW4
MPW Summary:
Slack: | 16.613 |
Actual Width: | 17.539 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | disp_dist_1/distance_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.026 | 0.195 | tNET | FF | disp_dist_1/distance_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.566 | 0.137 | tNET | RR | disp_dist_1/distance_2_s0/CLK |
MPW5
MPW Summary:
Slack: | 16.613 |
Actual Width: | 17.539 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | disp_dist_1/clkdiv_3/count_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.026 | 0.195 | tNET | FF | disp_dist_1/clkdiv_3/count_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.566 | 0.137 | tNET | RR | disp_dist_1/clkdiv_3/count_3_s0/CLK |
MPW6
MPW Summary:
Slack: | 16.613 |
Actual Width: | 17.539 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | disp_dist_1/clkdiv_3/count_4_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.026 | 0.195 | tNET | FF | disp_dist_1/clkdiv_3/count_4_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.566 | 0.137 | tNET | RR | disp_dist_1/clkdiv_3/count_4_s0/CLK |
MPW7
MPW Summary:
Slack: | 16.613 |
Actual Width: | 17.539 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | disp_dist_1/distance_3_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.026 | 0.195 | tNET | FF | disp_dist_1/distance_3_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.566 | 0.137 | tNET | RR | disp_dist_1/distance_3_s0/CLK |
MPW8
MPW Summary:
Slack: | 16.613 |
Actual Width: | 17.539 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | disp_dist_1/clkdiv_3/count_5_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.026 | 0.195 | tNET | FF | disp_dist_1/clkdiv_3/count_5_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.566 | 0.137 | tNET | RR | disp_dist_1/clkdiv_3/count_5_s0/CLK |
MPW9
MPW Summary:
Slack: | 16.613 |
Actual Width: | 17.539 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | disp_dist_1/clkdiv_3/count_6_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.026 | 0.195 | tNET | FF | disp_dist_1/clkdiv_3/count_6_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.566 | 0.137 | tNET | RR | disp_dist_1/clkdiv_3/count_6_s0/CLK |
MPW10
MPW Summary:
Slack: | 16.613 |
Actual Width: | 17.539 |
Required Width: | 0.926 |
Type: | Low Pulse Width |
Clock: | clk27mhz |
Objects: | clkdiv_1/clk_out_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
18.518 | 0.000 | active clock edge time | ||
18.518 | 0.000 | clk27mhz | ||
18.518 | 0.000 | tCL | FF | clk_ibuf/I |
20.832 | 2.314 | tINS | FF | clk_ibuf/O |
21.026 | 0.195 | tNET | FF | clkdiv_1/clk_out_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
37.037 | 0.000 | active clock edge time | ||
37.037 | 0.000 | clk27mhz | ||
37.037 | 0.000 | tCL | RR | clk_ibuf/I |
38.429 | 1.392 | tINS | RR | clk_ibuf/O |
38.566 | 0.137 | tNET | RR | clkdiv_1/clk_out_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
60 | clk_1mhz | 18.892 | 1.157 |
35 | clk_d | 29.091 | 0.195 |
19 | dlkdiv_2/n7_109 | 992.450 | 1.097 |
17 | disp_dist_1/mux7seg_1/col[0] | 3703694.500 | 0.999 |
16 | disp_dist_1/clkdiv_3/n61_13 | 29.091 | 0.670 |
16 | n106_7 | 996.715 | 1.465 |
16 | counter16_1/count_15_8 | 996.439 | 0.631 |
13 | disp_dist_1/clk270hz | 3703694.750 | 1.504 |
12 | measure[15] | 18.909 | 0.627 |
11 | measure[12] | 18.892 | 0.972 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R2C2 | 100.00% |
R2C5 | 100.00% |
R2C7 | 100.00% |
R2C8 | 100.00% |
R3C6 | 100.00% |
R5C2 | 100.00% |
R16C2 | 100.00% |
R16C3 | 100.00% |
R15C18 | 100.00% |
R15C19 | 100.00% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|---|---|
TC_CLOCK | Actived | create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk1mhz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 27 [get_nets {clk_1mhz}] |
TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk270hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 100000 [get_nets {disp_dist_1/clk270hz}] |
TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk27mhz}] -to [get_clocks {clk270hz}] |