Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\workspace\ultra_sonic\src\clkdiv.sv
C:\Gowin\workspace\ultra_sonic\src\top.sv
C:\Gowin\workspace\ultra_sonic\src\count16.sv
C:\Gowin\workspace\ultra_sonic\src\drv7seg4.sv
C:\Gowin\workspace\ultra_sonic\src\mux7seg.sv
C:\Gowin\workspace\ultra_sonic\src\disp_dist.sv
GowinSynthesis Constraints File ---
Tool Version V1.9.11.02 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Mon Jun 9 11:31:54 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module top
Synthesis Process Running parser:
    CPU time = 0h 0m 0.343s, Elapsed time = 0h 0m 0.293s, Peak memory usage = 218.164MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.06s, Peak memory usage = 218.164MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 218.164MB
    Optimizing Phase 2: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 218.164MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 218.164MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 218.164MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 218.164MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 218.164MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.032s, Peak memory usage = 218.164MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 218.164MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 218.164MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 218.164MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.114s, Peak memory usage = 218.164MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 218.164MB
Total Time and Memory Usage CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s, Peak memory usage = 218.164MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 16
I/O Buf 16
    IBUF 3
    OBUF 13
Register 108
    DFFE 14
    DFFC 56
    DFFCE 38
LUT 297
    LUT2 41
    LUT3 78
    LUT4 178
ALU 15
    ALU 15
INV 4
    INV 4

Resource Utilization Summary

Resource Usage Utilization
Logic 316(301 LUT, 15 ALU) / 1584 20%
Register 108 / 1704 7%
  --Register as Latch 0 / 1704 0%
  --Register as FF 108 / 1704 7%
BSRAM 0 / 4 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.000 0.000 10.000 clk_ibuf/I
2 clkdiv_1/clk_1mhz Base 20.000 50.000 0.000 10.000 clkdiv_1/clk_out_s0/Q
3 disp_dist_1/clkdiv_3/clk270hz Base 20.000 50.000 0.000 10.000 disp_dist_1/clkdiv_3/clk_out_s0/Q

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 89.152(MHz) 8 TOP
2 clkdiv_1/clk_1mhz 50.000(MHz) 92.845(MHz) 8 TOP
3 disp_dist_1/clkdiv_3/clk270hz 50.000(MHz) 168.789(MHz) 4 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack -3.909
Data Arrival Time 24.121
Data Required Time 20.212
From measure_12_s0
To disp_dist_1/distance_0_s0
Launch Clk clkdiv_1/clk_1mhz[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clkdiv_1/clk_1mhz
0.000 0.000 tCL RR 60 clkdiv_1/clk_out_s0/Q
0.538 0.538 tNET RR 1 measure_12_s0/CLK
0.878 0.340 tC2Q RF 11 measure_12_s0/Q
1.589 0.711 tNET FF 1 disp_dist_1/n16_s31/I1
2.403 0.814 tINS FF 1 disp_dist_1/n16_s31/F
3.115 0.711 tNET FF 1 disp_dist_1/n16_s28/I1
3.929 0.814 tINS FF 3 disp_dist_1/n16_s28/F
4.640 0.711 tNET FF 1 disp_dist_1/n17_s19/I1
5.455 0.814 tINS FF 1 disp_dist_1/n17_s19/F
6.166 0.711 tNET FF 1 disp_dist_1/n17_s16/I1
6.980 0.814 tINS FF 8 disp_dist_1/n17_s16/F
7.692 0.711 tNET FF 1 disp_dist_1/n17_s15/I1
8.506 0.814 tINS FF 2 disp_dist_1/n17_s15/F
9.218 0.711 tNET FF 1 disp_dist_1/n18_s13/I0
9.982 0.765 tINS FF 6 disp_dist_1/n18_s13/F
10.694 0.711 tNET FF 1 disp_dist_1/n21_s26/I1
11.508 0.814 tINS FF 3 disp_dist_1/n21_s26/F
12.219 0.711 tNET FF 1 disp_dist_1/n21_s24/I1
13.034 0.814 tINS FF 1 disp_dist_1/n21_s24/F
13.745 0.711 tNET FF 1 disp_dist_1/n21_s17/I1
14.559 0.814 tINS FF 4 disp_dist_1/n21_s17/F
15.271 0.711 tNET FF 1 disp_dist_1/n21_s11/I2
15.880 0.609 tINS FF 2 disp_dist_1/n21_s11/F
16.591 0.711 tNET FF 1 disp_dist_1/n21_s10/I0
17.356 0.765 tINS FF 3 disp_dist_1/n21_s10/F
18.067 0.711 tNET FF 1 disp_dist_1/n23_s15/I1
18.882 0.814 tINS FF 4 disp_dist_1/n23_s15/F
19.593 0.711 tNET FF 1 disp_dist_1/n23_s12/I0
20.358 0.765 tINS FF 3 disp_dist_1/n23_s12/F
21.069 0.711 tNET FF 1 disp_dist_1/n23_s10/I1
21.883 0.814 tINS FF 2 disp_dist_1/n23_s10/F
22.595 0.711 tNET FF 1 disp_dist_1/n24_s23/I1
23.409 0.814 tINS FF 1 disp_dist_1/n24_s23/F
24.121 0.711 tNET FF 1 disp_dist_1/distance_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 35 clk_ibuf/O
20.538 0.538 tNET RR 1 disp_dist_1/distance_0_s0/CLK
20.508 -0.030 tUnc disp_dist_1/distance_0_s0
20.212 -0.296 tSu 1 disp_dist_1/distance_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 11.861, 50.297%; route: 11.382, 48.263%; tC2Q: 0.340, 1.440%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack -3.870
Data Arrival Time 24.082
Data Required Time 20.212
From disp_dist_1/distance_9_s0
To disp_dist_1/mux7seg_1/seg_5_s0
Launch Clk clk[R]
Latch Clk disp_dist_1/clkdiv_3/clk270hz[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 35 clk_ibuf/O
0.538 0.538 tNET RR 1 disp_dist_1/distance_9_s0/CLK
0.878 0.340 tC2Q RF 9 disp_dist_1/distance_9_s0/Q
1.589 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s7/I1
2.403 0.814 tINS FF 2 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s7/F
3.115 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s6/I0
3.879 0.765 tINS FF 4 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s6/F
4.591 0.711 tNET FF 1 disp_dist_1/drv_7seg4_1/seg_in[0]_2_s7/I1
5.405 0.814 tINS FF 4 disp_dist_1/drv_7seg4_1/seg_in[0]_2_s7/F
6.116 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s9/I1
6.931 0.814 tINS FF 7 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s9/F
7.642 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s2/I0
8.407 0.765 tINS FF 6 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s2/F
9.118 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s4/I0
9.883 0.765 tINS FF 5 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s4/F
10.594 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s3/I2
11.203 0.609 tINS FF 2 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s3/F
11.915 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s0/I1
12.729 0.814 tINS FF 4 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s0/F
13.441 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s8/I2
14.050 0.609 tINS FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s8/F
14.761 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s14/I0
15.526 0.765 tINS FF 6 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s14/F
16.237 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s6/I2
16.846 0.609 tINS FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s6/F
17.558 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s2/I1
18.372 0.814 tINS FF 15 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s2/F
19.083 0.711 tNET FF 1 disp_dist_1/drv_7seg4_2/seg_in[1]_5_s5/I1
19.898 0.814 tINS FF 4 disp_dist_1/drv_7seg4_2/seg_in[1]_5_s5/F
20.609 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n15_s9/I3
21.073 0.464 tINS FF 1 disp_dist_1/mux7seg_1/n15_s9/F
21.784 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n15_s4/I1
21.895 0.110 tINS FF 1 disp_dist_1/mux7seg_1/n15_s4/O
22.606 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n15_s6/I0
23.371 0.765 tINS FF 1 disp_dist_1/mux7seg_1/n15_s6/F
24.082 0.711 tNET FF 1 disp_dist_1/mux7seg_1/seg_5_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 disp_dist_1/clkdiv_3/clk270hz
20.000 0.000 tCL RR 13 disp_dist_1/clkdiv_3/clk_out_s0/Q
20.538 0.538 tNET RR 1 disp_dist_1/mux7seg_1/seg_5_s0/CLK
20.508 -0.030 tUnc disp_dist_1/mux7seg_1/seg_5_s0
20.212 -0.296 tSu 1 disp_dist_1/mux7seg_1/seg_5_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 11.111, 47.194%; route: 12.093, 51.363%; tC2Q: 0.340, 1.443%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack -3.244
Data Arrival Time 23.455
Data Required Time 20.212
From disp_dist_1/distance_9_s0
To disp_dist_1/mux7seg_1/seg_6_s0
Launch Clk clk[R]
Latch Clk disp_dist_1/clkdiv_3/clk270hz[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 35 clk_ibuf/O
0.538 0.538 tNET RR 1 disp_dist_1/distance_9_s0/CLK
0.878 0.340 tC2Q RF 9 disp_dist_1/distance_9_s0/Q
1.589 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s7/I1
2.403 0.814 tINS FF 2 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s7/F
3.115 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s6/I0
3.879 0.765 tINS FF 4 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s6/F
4.591 0.711 tNET FF 1 disp_dist_1/drv_7seg4_1/seg_in[0]_2_s7/I1
5.405 0.814 tINS FF 4 disp_dist_1/drv_7seg4_1/seg_in[0]_2_s7/F
6.116 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s9/I1
6.931 0.814 tINS FF 7 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s9/F
7.642 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s2/I0
8.407 0.765 tINS FF 6 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s2/F
9.118 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s4/I0
9.883 0.765 tINS FF 5 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s4/F
10.594 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s3/I2
11.203 0.609 tINS FF 2 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s3/F
11.915 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s0/I1
12.729 0.814 tINS FF 4 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s0/F
13.441 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s8/I2
14.050 0.609 tINS FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s8/F
14.761 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s14/I0
15.526 0.765 tINS FF 6 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s14/F
16.237 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s6/I2
16.846 0.609 tINS FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s6/F
17.558 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s2/I1
18.372 0.814 tINS FF 15 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s2/F
19.083 0.711 tNET FF 1 disp_dist_1/drv_7seg4_2/seg_in[1]_5_s5/I1
19.898 0.814 tINS FF 4 disp_dist_1/drv_7seg4_2/seg_in[1]_5_s5/F
20.609 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n14_s7/I1
21.423 0.814 tINS FF 1 disp_dist_1/mux7seg_1/n14_s7/F
22.135 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n14_s4/I2
22.744 0.609 tINS FF 1 disp_dist_1/mux7seg_1/n14_s4/F
23.455 0.711 tNET FF 1 disp_dist_1/mux7seg_1/seg_6_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 disp_dist_1/clkdiv_3/clk270hz
20.000 0.000 tCL RR 13 disp_dist_1/clkdiv_3/clk_out_s0/Q
20.538 0.538 tNET RR 1 disp_dist_1/mux7seg_1/seg_6_s0/CLK
20.508 -0.030 tUnc disp_dist_1/mux7seg_1/seg_6_s0
20.212 -0.296 tSu 1 disp_dist_1/mux7seg_1/seg_6_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 11.196, 48.853%; route: 11.382, 49.665%; tC2Q: 0.340, 1.482%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack -3.227
Data Arrival Time 23.438
Data Required Time 20.212
From disp_dist_1/distance_9_s0
To disp_dist_1/mux7seg_1/seg_2_s0
Launch Clk clk[R]
Latch Clk disp_dist_1/clkdiv_3/clk270hz[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 35 clk_ibuf/O
0.538 0.538 tNET RR 1 disp_dist_1/distance_9_s0/CLK
0.878 0.340 tC2Q RF 9 disp_dist_1/distance_9_s0/Q
1.589 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s7/I1
2.403 0.814 tINS FF 2 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s7/F
3.115 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s6/I0
3.879 0.765 tINS FF 4 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s6/F
4.591 0.711 tNET FF 1 disp_dist_1/drv_7seg4_1/seg_in[0]_2_s7/I1
5.405 0.814 tINS FF 4 disp_dist_1/drv_7seg4_1/seg_in[0]_2_s7/F
6.116 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s9/I1
6.931 0.814 tINS FF 7 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s9/F
7.642 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s2/I0
8.407 0.765 tINS FF 6 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s2/F
9.118 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s4/I0
9.883 0.765 tINS FF 5 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s4/F
10.594 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s3/I2
11.203 0.609 tINS FF 2 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s3/F
11.915 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s0/I1
12.729 0.814 tINS FF 4 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s0/F
13.441 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s8/I2
14.050 0.609 tINS FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s8/F
14.761 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s14/I0
15.526 0.765 tINS FF 6 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s14/F
16.237 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s6/I2
16.846 0.609 tINS FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s6/F
17.558 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s2/I1
18.372 0.814 tINS FF 15 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s2/F
19.083 0.711 tNET FF 1 disp_dist_1/drv_7seg4_2/seg_in[1]_5_s5/I1
19.898 0.814 tINS FF 4 disp_dist_1/drv_7seg4_2/seg_in[1]_5_s5/F
20.609 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n18_s9/I3
21.073 0.464 tINS FF 1 disp_dist_1/mux7seg_1/n18_s9/F
21.784 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n18_s6/I1
21.895 0.110 tINS FF 1 disp_dist_1/mux7seg_1/n18_s6/O
22.606 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n18_s3/I0
22.727 0.121 tINS FF 1 disp_dist_1/mux7seg_1/n18_s3/O
23.438 0.711 tNET FF 1 disp_dist_1/mux7seg_1/seg_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 disp_dist_1/clkdiv_3/clk270hz
20.000 0.000 tCL RR 13 disp_dist_1/clkdiv_3/clk_out_s0/Q
20.538 0.538 tNET RR 1 disp_dist_1/mux7seg_1/seg_2_s0/CLK
20.508 -0.030 tUnc disp_dist_1/mux7seg_1/seg_2_s0
20.212 -0.296 tSu 1 disp_dist_1/mux7seg_1/seg_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 15
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 10.467, 45.709%; route: 12.093, 52.808%; tC2Q: 0.340, 1.483%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack -3.194
Data Arrival Time 23.405
Data Required Time 20.212
From disp_dist_1/distance_9_s0
To disp_dist_1/mux7seg_1/seg_3_s0
Launch Clk clk[R]
Latch Clk disp_dist_1/clkdiv_3/clk270hz[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 35 clk_ibuf/O
0.538 0.538 tNET RR 1 disp_dist_1/distance_9_s0/CLK
0.878 0.340 tC2Q RF 9 disp_dist_1/distance_9_s0/Q
1.589 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s7/I1
2.403 0.814 tINS FF 2 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s7/F
3.115 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s6/I0
3.879 0.765 tINS FF 4 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s6/F
4.591 0.711 tNET FF 1 disp_dist_1/drv_7seg4_1/seg_in[0]_2_s7/I1
5.405 0.814 tINS FF 4 disp_dist_1/drv_7seg4_1/seg_in[0]_2_s7/F
6.116 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s9/I1
6.931 0.814 tINS FF 7 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s9/F
7.642 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s2/I0
8.407 0.765 tINS FF 6 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s2/F
9.118 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s4/I0
9.883 0.765 tINS FF 5 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s4/F
10.594 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s3/I2
11.203 0.609 tINS FF 2 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s3/F
11.915 0.711 tNET FF 1 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s0/I1
12.729 0.814 tINS FF 4 disp_dist_1/drv_7seg4_4/seg_in[3]_5_s0/F
13.441 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s8/I2
14.050 0.609 tINS FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s8/F
14.761 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s14/I0
15.526 0.765 tINS FF 6 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s14/F
16.237 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s6/I2
16.846 0.609 tINS FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s6/F
17.558 0.711 tNET FF 1 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s2/I1
18.372 0.814 tINS FF 15 disp_dist_1/drv_7seg4_3/seg_in[2]_5_s2/F
19.083 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n13_s9/I2
19.692 0.609 tINS FF 2 disp_dist_1/mux7seg_1/n13_s9/F
20.404 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n17_s5/I0
21.168 0.765 tINS FF 1 disp_dist_1/mux7seg_1/n17_s5/F
21.880 0.711 tNET FF 1 disp_dist_1/mux7seg_1/n17_s3/I1
22.694 0.814 tINS FF 1 disp_dist_1/mux7seg_1/n17_s3/F
23.405 0.711 tNET FF 1 disp_dist_1/mux7seg_1/seg_3_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 disp_dist_1/clkdiv_3/clk270hz
20.000 0.000 tCL RR 13 disp_dist_1/clkdiv_3/clk_out_s0/Q
20.538 0.538 tNET RR 1 disp_dist_1/mux7seg_1/seg_3_s0/CLK
20.508 -0.030 tUnc disp_dist_1/mux7seg_1/seg_3_s0
20.212 -0.296 tSu 1 disp_dist_1/mux7seg_1/seg_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 16
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 11.146, 48.742%; route: 11.382, 49.773%; tC2Q: 0.340, 1.485%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%