Pin Messages

Report Title Pin Report
Design File C:\Gowin\workspace\ultra_sonic\impl\gwsynthesis\ultra_sonic.vg
Physical Constraints File C:\Gowin\workspace\ultra_sonic\src\ultra_sonic.cst
Timing Constraints File C:\Gowin\workspace\ultra_sonic\src\ultra_sonic.sdc
Tool Version V1.9.11.02 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Mon Jun 9 11:43:12 2025
Legal Announcement Copyright (C)2014-2025 Gowin Semiconductor Corporation. All rights reserved.

Pin Details

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 4/5 Y in IOL6[A] GCLKT_7 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
nrst - 35/1 Y in IOR1[B] - LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
echo - 36/1 Y in IOR1[A] - LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
trigger - 28/1 Y out IOR15[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
seg[0] - 26/1 Y out IOR17[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
seg[1] - 21/2 Y out IOB9[B] GCLKC_3 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
seg[2] - 20/2 Y out IOB9[A] GCLKT_3 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
seg[3] - 19/2 Y out IOB7[B] GCLKC_4 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
seg[4] - 18/2 Y out IOB7[A] GCLKT_4 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
seg[5] - 15/2 Y out IOB2[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
seg[6] - 14/2 Y out IOB2[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
seg[7] - 12/3 Y out IOL17[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
dig[0] - 31/1 Y out IOR13[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
dig[1] - 29/1 Y out IOR15[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
dig[2] - 40/0 Y out IOT15[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
dig[3] - 41/0 Y out IOT15[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site CFG IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
48/0 - out IOT7[A] TDO LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
47/0 - in IOT7[B] TDI LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
45/0 - in IOT9[A] TCK LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
44/0 - in IOT9[B] TMS LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
43/0 - in IOT14[A] GCLKT_1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
42/0 - in IOT14[B] GCLKC_1 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
41/0 dig[3] out IOT15[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
40/0 dig[2] out IOT15[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
38/0 - in IOT18[A] READY LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
37/0 - in IOT18[B] DONE LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
14/2 seg[6] out IOB2[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
15/2 seg[5] out IOB2[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
16/2 - in IOB5[A] SCLK LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
17/2 - in IOB5[B] SO LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
18/2 seg[4] out IOB7[A] GCLKT_4 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
19/2 seg[3] out IOB7[B] GCLKC_4 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
20/2 seg[2] out IOB9[A] GCLKT_3 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
21/2 seg[1] out IOB9[B] GCLKC_3 LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
23/2 - in IOB18[A] SSPI_CS_N LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
24/2 - in IOB18[B] SI LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
2/5 - in IOL4[A] LPLL_T_fb LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
3/5 - in IOL4[B] LPLL_C_fb LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
4/5 clk in IOL6[A] GCLKT_7 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
5/5 - in IOL6[B] GCLKC_7 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
7/4 - in IOL11[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
8/4 - in IOL11[B] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
9/4 - in IOL12[A] GCLKT_6 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
10/4 - in IOL12[B] GCLKC_6 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
11/3 - in IOL17[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
12/3 seg[7] out IOL17[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
36/1 echo in IOR1[A] - LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
35/1 nrst in IOR1[B] - LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
34/1 - in IOR11[A] GCLKT_2 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
33/1 - in IOR11[B] GCLKC_2 LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
32/1 - in IOR13[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
31/1 dig[0] out IOR13[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
29/1 dig[1] out IOR15[A] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
28/1 trigger out IOR15[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
27/1 - in IOR17[A] - LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
26/1 seg[0] out IOR17[B] - LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3