Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\alu.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\clkdiv.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\debounce.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\drv7seg.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\leg4.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\leg4rom.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\leg4sys.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\mux7seg.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\pc.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\toggle.sv |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW1N-UV1P5QN48XFC7/I6 |
| Device | GW1N-1P5 |
| Device Version | C |
| Created Time | Mon Dec 16 15:42:41 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | leg4sys |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.115s, Peak memory usage = 193.211MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.012s, Peak memory usage = 193.211MB Optimizing Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 193.211MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 193.211MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 193.211MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 193.211MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 193.211MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 193.211MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.021s, Peak memory usage = 193.211MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 193.211MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 193.211MB Tech-Mapping Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 219.094MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.152s, Peak memory usage = 219.094MB Generate output files: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.043s, Peak memory usage = 219.094MB |
| Total Time and Memory Usage | CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s, Peak memory usage = 219.094MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 30 |
| I/O Buf | 30 |
|     IBUF | 9 |
|     OBUF | 21 |
| Register | 138 |
|     DFFE | 18 |
|     DFFP | 4 |
|     DFFC | 108 |
|     DFFCE | 8 |
| LUT | 360 |
|     LUT2 | 48 |
|     LUT3 | 130 |
|     LUT4 | 182 |
| ALU | 4 |
|     ALU | 4 |
| INV | 7 |
|     INV | 7 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 371(367 LUT, 4 ALU) / 1584 | 24% |
| Register | 138 / 1704 | 9% |
|   --Register as Latch | 0 / 1704 | 0% |
|   --Register as FF | 138 / 1704 | 9% |
| BSRAM | 0 / 4 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | clkdiv_1/clk400hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_1/clk_out_s0/Q | ||
| 3 | leg4_clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | leg4_clk_s5/O | ||
| 4 | clkdiv_5/clk160hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_5/clk_out_s0/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 134.223(MHz) | 5 | TOP |
| 2 | clkdiv_1/clk400hz | 50.000(MHz) | 348.056(MHz) | 2 | TOP |
| 3 | leg4_clk | 50.000(MHz) | 85.830(MHz) | 8 | TOP |
| 4 | clkdiv_5/clk160hz | 50.000(MHz) | 181.015(MHz) | 4 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 8.349 |
| Data Arrival Time | 11.893 |
| Data Required Time | 20.242 |
| From | leg4_1/inst1/adr_1_s0 |
| To | leg4_1/out_2_s0 |
| Launch Clk | leg4_clk[R] |
| Latch Clk | leg4_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | leg4_clk | |||
| 0.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
| 0.538 | 0.538 | tNET | RR | 1 | leg4_1/inst1/adr_1_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 27 | leg4_1/inst1/adr_1_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | drv7seg_1/seg_1_s32/I1 |
| 2.403 | 0.814 | tINS | FF | 7 | drv7seg_1/seg_1_s32/F |
| 3.115 | 0.711 | tNET | FF | 1 | leg4_rom_1/rom_out_1_s/I1 |
| 3.929 | 0.814 | tINS | FF | 4 | leg4_rom_1/rom_out_1_s/F |
| 4.640 | 0.711 | tNET | FF | 2 | leg4_1/inst2/n8_s/I1 |
| 5.415 | 0.774 | tINS | FF | 1 | leg4_1/inst2/n8_s/COUT |
| 5.415 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n7_s/CIN |
| 5.832 | 0.417 | tINS | FF | 1 | leg4_1/inst2/n7_s/SUM |
| 6.543 | 0.711 | tNET | FF | 1 | leg4_1/inst2/n17_s21/I1 |
| 7.358 | 0.814 | tINS | FF | 1 | leg4_1/inst2/n17_s21/F |
| 8.069 | 0.711 | tNET | FF | 1 | leg4_1/inst2/n17_s19/I0 |
| 8.179 | 0.110 | tINS | FF | 1 | leg4_1/inst2/n17_s19/O |
| 8.891 | 0.711 | tNET | FF | 1 | leg4_1/inst2/data_Z_2_s0/I0 |
| 9.655 | 0.765 | tINS | FF | 1 | leg4_1/inst2/data_Z_2_s0/F |
| 10.367 | 0.711 | tNET | FF | 1 | leg4_1/inst2/data_Z_2_s/I1 |
| 11.181 | 0.814 | tINS | FF | 2 | leg4_1/inst2/data_Z_2_s/F |
| 11.893 | 0.711 | tNET | FF | 1 | leg4_1/out_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | leg4_clk | |||
| 20.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
| 20.538 | 0.538 | tNET | RR | 1 | leg4_1/out_2_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | leg4_1/out_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 5.324, 46.889%; route: 5.691, 50.120%; tC2Q: 0.340, 2.991% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 2
Path Summary:| Slack | 8.349 |
| Data Arrival Time | 11.893 |
| Data Required Time | 20.242 |
| From | leg4_1/inst1/adr_1_s0 |
| To | leg4_1/a_2_s0 |
| Launch Clk | leg4_clk[R] |
| Latch Clk | leg4_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | leg4_clk | |||
| 0.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
| 0.538 | 0.538 | tNET | RR | 1 | leg4_1/inst1/adr_1_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 27 | leg4_1/inst1/adr_1_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | drv7seg_1/seg_1_s32/I1 |
| 2.403 | 0.814 | tINS | FF | 7 | drv7seg_1/seg_1_s32/F |
| 3.115 | 0.711 | tNET | FF | 1 | leg4_rom_1/rom_out_1_s/I1 |
| 3.929 | 0.814 | tINS | FF | 4 | leg4_rom_1/rom_out_1_s/F |
| 4.640 | 0.711 | tNET | FF | 2 | leg4_1/inst2/n8_s/I1 |
| 5.415 | 0.774 | tINS | FF | 1 | leg4_1/inst2/n8_s/COUT |
| 5.415 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n7_s/CIN |
| 5.832 | 0.417 | tINS | FF | 1 | leg4_1/inst2/n7_s/SUM |
| 6.543 | 0.711 | tNET | FF | 1 | leg4_1/inst2/n17_s21/I1 |
| 7.358 | 0.814 | tINS | FF | 1 | leg4_1/inst2/n17_s21/F |
| 8.069 | 0.711 | tNET | FF | 1 | leg4_1/inst2/n17_s19/I0 |
| 8.179 | 0.110 | tINS | FF | 1 | leg4_1/inst2/n17_s19/O |
| 8.891 | 0.711 | tNET | FF | 1 | leg4_1/inst2/data_Z_2_s0/I0 |
| 9.655 | 0.765 | tINS | FF | 1 | leg4_1/inst2/data_Z_2_s0/F |
| 10.367 | 0.711 | tNET | FF | 1 | leg4_1/inst2/data_Z_2_s/I1 |
| 11.181 | 0.814 | tINS | FF | 2 | leg4_1/inst2/data_Z_2_s/F |
| 11.893 | 0.711 | tNET | FF | 1 | leg4_1/a_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | leg4_clk | |||
| 20.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
| 20.538 | 0.538 | tNET | RR | 1 | leg4_1/a_2_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | leg4_1/a_2_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 5.324, 46.889%; route: 5.691, 50.120%; tC2Q: 0.340, 2.991% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 3
Path Summary:| Slack | 8.356 |
| Data Arrival Time | 11.885 |
| Data Required Time | 20.242 |
| From | leg4_1/inst1/adr_1_s0 |
| To | leg4_1/a_3_s0 |
| Launch Clk | leg4_clk[R] |
| Latch Clk | leg4_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | leg4_clk | |||
| 0.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
| 0.538 | 0.538 | tNET | RR | 1 | leg4_1/inst1/adr_1_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 27 | leg4_1/inst1/adr_1_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | drv7seg_1/seg_1_s32/I1 |
| 2.403 | 0.814 | tINS | FF | 7 | drv7seg_1/seg_1_s32/F |
| 3.115 | 0.711 | tNET | FF | 1 | leg4_rom_1/rom_out_1_s/I1 |
| 3.929 | 0.814 | tINS | FF | 4 | leg4_rom_1/rom_out_1_s/F |
| 4.640 | 0.711 | tNET | FF | 2 | leg4_1/inst2/n8_s/I1 |
| 5.415 | 0.774 | tINS | FF | 1 | leg4_1/inst2/n8_s/COUT |
| 5.415 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n7_s/CIN |
| 5.457 | 0.042 | tINS | FF | 1 | leg4_1/inst2/n7_s/COUT |
| 5.457 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n6_s/CIN |
| 5.874 | 0.417 | tINS | FF | 1 | leg4_1/inst2/n6_s/SUM |
| 6.586 | 0.711 | tNET | FF | 1 | leg4_1/inst2/n16_s23/I0 |
| 7.350 | 0.765 | tINS | FF | 1 | leg4_1/inst2/n16_s23/F |
| 8.062 | 0.711 | tNET | FF | 1 | leg4_1/inst2/n16_s19/I0 |
| 8.172 | 0.110 | tINS | FF | 1 | leg4_1/inst2/n16_s19/O |
| 8.883 | 0.711 | tNET | FF | 1 | leg4_1/inst2/data_Z_3_s0/I0 |
| 9.648 | 0.765 | tINS | FF | 1 | leg4_1/inst2/data_Z_3_s0/F |
| 10.359 | 0.711 | tNET | FF | 1 | leg4_1/inst2/data_Z_3_s/I1 |
| 11.174 | 0.814 | tINS | FF | 2 | leg4_1/inst2/data_Z_3_s/F |
| 11.885 | 0.711 | tNET | FF | 1 | leg4_1/a_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | leg4_clk | |||
| 20.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
| 20.538 | 0.538 | tNET | RR | 1 | leg4_1/a_3_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | leg4_1/a_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 5.317, 46.855%; route: 5.691, 50.152%; tC2Q: 0.340, 2.993% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 4
Path Summary:| Slack | 8.356 |
| Data Arrival Time | 11.885 |
| Data Required Time | 20.242 |
| From | leg4_1/inst1/adr_1_s0 |
| To | leg4_1/out_3_s0 |
| Launch Clk | leg4_clk[R] |
| Latch Clk | leg4_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | leg4_clk | |||
| 0.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
| 0.538 | 0.538 | tNET | RR | 1 | leg4_1/inst1/adr_1_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 27 | leg4_1/inst1/adr_1_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | drv7seg_1/seg_1_s32/I1 |
| 2.403 | 0.814 | tINS | FF | 7 | drv7seg_1/seg_1_s32/F |
| 3.115 | 0.711 | tNET | FF | 1 | leg4_rom_1/rom_out_1_s/I1 |
| 3.929 | 0.814 | tINS | FF | 4 | leg4_rom_1/rom_out_1_s/F |
| 4.640 | 0.711 | tNET | FF | 2 | leg4_1/inst2/n8_s/I1 |
| 5.415 | 0.774 | tINS | FF | 1 | leg4_1/inst2/n8_s/COUT |
| 5.415 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n7_s/CIN |
| 5.457 | 0.042 | tINS | FF | 1 | leg4_1/inst2/n7_s/COUT |
| 5.457 | 0.000 | tNET | FF | 2 | leg4_1/inst2/n6_s/CIN |
| 5.874 | 0.417 | tINS | FF | 1 | leg4_1/inst2/n6_s/SUM |
| 6.586 | 0.711 | tNET | FF | 1 | leg4_1/inst2/n16_s23/I0 |
| 7.350 | 0.765 | tINS | FF | 1 | leg4_1/inst2/n16_s23/F |
| 8.062 | 0.711 | tNET | FF | 1 | leg4_1/inst2/n16_s19/I0 |
| 8.172 | 0.110 | tINS | FF | 1 | leg4_1/inst2/n16_s19/O |
| 8.883 | 0.711 | tNET | FF | 1 | leg4_1/inst2/data_Z_3_s0/I0 |
| 9.648 | 0.765 | tINS | FF | 1 | leg4_1/inst2/data_Z_3_s0/F |
| 10.359 | 0.711 | tNET | FF | 1 | leg4_1/inst2/data_Z_3_s/I1 |
| 11.174 | 0.814 | tINS | FF | 2 | leg4_1/inst2/data_Z_3_s/F |
| 11.885 | 0.711 | tNET | FF | 1 | leg4_1/out_3_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | leg4_clk | |||
| 20.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
| 20.538 | 0.538 | tNET | RR | 1 | leg4_1/out_3_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | leg4_1/out_3_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 8 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 5.317, 46.855%; route: 5.691, 50.152%; tC2Q: 0.340, 2.993% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 5
Path Summary:| Slack | 9.069 |
| Data Arrival Time | 11.172 |
| Data Required Time | 20.242 |
| From | leg4_1/inst1/adr_1_s0 |
| To | leg4_1/out_1_s0 |
| Launch Clk | leg4_clk[R] |
| Latch Clk | leg4_clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | leg4_clk | |||
| 0.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
| 0.538 | 0.538 | tNET | RR | 1 | leg4_1/inst1/adr_1_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 27 | leg4_1/inst1/adr_1_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | drv7seg_1/seg_1_s32/I1 |
| 2.403 | 0.814 | tINS | FF | 7 | drv7seg_1/seg_1_s32/F |
| 3.115 | 0.711 | tNET | FF | 1 | leg4_rom_1/rom_out_1_s/I1 |
| 3.929 | 0.814 | tINS | FF | 4 | leg4_rom_1/rom_out_1_s/F |
| 4.640 | 0.711 | tNET | FF | 2 | leg4_1/inst2/n8_s/I1 |
| 5.161 | 0.521 | tINS | FF | 1 | leg4_1/inst2/n8_s/SUM |
| 5.873 | 0.711 | tNET | FF | 1 | leg4_1/inst2/n18_s21/I1 |
| 6.687 | 0.814 | tINS | FF | 1 | leg4_1/inst2/n18_s21/F |
| 7.398 | 0.711 | tNET | FF | 1 | leg4_1/inst2/n18_s19/I0 |
| 7.509 | 0.110 | tINS | FF | 1 | leg4_1/inst2/n18_s19/O |
| 8.220 | 0.711 | tNET | FF | 1 | leg4_1/inst2/data_Z_1_s0/I0 |
| 8.985 | 0.765 | tINS | FF | 1 | leg4_1/inst2/data_Z_1_s0/F |
| 9.696 | 0.711 | tNET | FF | 1 | leg4_1/inst2/data_Z_1_s/I0 |
| 10.461 | 0.765 | tINS | FF | 2 | leg4_1/inst2/data_Z_1_s/F |
| 11.172 | 0.711 | tNET | FF | 1 | leg4_1/out_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | leg4_clk | |||
| 20.000 | 0.000 | tCL | RR | 17 | leg4_clk_s5/O |
| 20.538 | 0.538 | tNET | RR | 1 | leg4_1/out_1_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | leg4_1/out_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 7 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 4.604, 43.292%; route: 5.691, 53.514%; tC2Q: 0.340, 3.194% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |