Timing Messages

Report Title Timing Analysis Report
Design File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\impl\gwsynthesis\matrix_key.vg
Physical Constraints File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\src\matrix_key.cst
Timing Constraint File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\src\matrix_key.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Thu Dec 19 16:26:53 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.71V 85C C7/I6
Hold Delay Model Fast 3.6V 0C C7/I6
Numbers of Paths Analyzed 278
Numbers of Endpoints Analyzed 171
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk27mhz Base 37.037 27.000 0.000 18.518 clk
2 clk50hz Generated 1481480.000 0.001 0.000 740740.000 clk clk27mhz clk50hz

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk27mhz 27.000(MHz) 159.978(MHz) 5 TOP
2 clk50hz 0.001(MHz) 285.714(MHz) 2 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk27mhz Setup 0.000 0
clk27mhz Hold 0.000 0
clk50hz Setup 0.000 0
clk50hz Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 30.786 clkdiv_1/count_15_s0/Q clkdiv_1/count_8_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.954
2 30.836 clkdiv_1/count_15_s0/Q clkdiv_1/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.905
3 30.844 clkdiv_1/count_15_s0/Q clkdiv_1/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.896
4 31.027 clkdiv_1/count_15_s0/Q clkdiv_1/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.713
5 31.070 clkdiv_1/count_15_s0/Q clkdiv_1/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.670
6 31.070 clkdiv_1/count_15_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.670
7 31.070 clkdiv_1/count_15_s0/Q clkdiv_1/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.670
8 31.130 clkdiv_1/count_15_s0/Q clkdiv_1/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.611
9 31.130 clkdiv_1/count_15_s0/Q clkdiv_1/count_19_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.611
10 31.152 clkdiv_1/count_15_s0/Q clkdiv_1/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.589
11 31.152 clkdiv_1/count_15_s0/Q clkdiv_1/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.589
12 31.155 clkdiv_1/count_15_s0/Q clkdiv_1/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.586
13 31.310 clkdiv_1/count_15_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.430
14 31.310 clkdiv_1/count_15_s0/Q clkdiv_1/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.430
15 31.456 clkdiv_1/count_15_s0/Q clkdiv_1/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.285
16 32.090 clkdiv_1/count_0_s0/Q clkdiv_1/clk_out_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.651
17 32.151 clkdiv_1/count_0_s0/Q clkdiv_1/count_18_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.589
18 32.271 clkdiv_1/count_0_s0/Q clkdiv_1/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.470
19 32.502 clkdiv_1/count_0_s0/Q clkdiv_1/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.239
20 32.970 clkdiv_1/count_0_s0/Q clkdiv_1/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 3.771
21 33.115 clkdiv_1/count_0_s0/Q clkdiv_1/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 3.625
22 1481476.500 matrix_key_1/index_0_s0/Q matrix_key_1/tc_s0/D clk50hz:[R] clk50hz:[R] 1481480.000 0.000 3.301
23 1481476.625 matrix_key_1/index_0_s0/Q matrix_key_1/tmp_15_s1/D clk50hz:[R] clk50hz:[R] 1481480.000 0.000 3.174
24 1481476.875 matrix_key_1/index_0_s0/Q matrix_key_1/tmp_11_s1/D clk50hz:[R] clk50hz:[R] 1481480.000 0.000 2.909
25 1481476.875 matrix_key_1/index_0_s0/Q matrix_key_1/tmp_14_s1/D clk50hz:[R] clk50hz:[R] 1481480.000 0.000 2.815

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.526 clkdiv_1/count_8_s0/Q clkdiv_1/count_8_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
2 0.526 clkdiv_1/count_9_s0/Q clkdiv_1/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
3 0.526 clkdiv_1/count_13_s0/Q clkdiv_1/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
4 0.526 matrix_key_1/index_0_s0/Q matrix_key_1/index_0_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.526
5 0.526 matrix_key_1/index_2_s0/Q matrix_key_1/index_2_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.526
6 0.527 clkdiv_1/count_4_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.527
7 0.527 clkdiv_1/count_5_s0/Q clkdiv_1/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.527
8 0.527 clkdiv_1/count_6_s0/Q clkdiv_1/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.527
9 0.662 clkdiv_1/count_17_s0/Q clkdiv_1/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.662
10 0.694 matrix_key_1/tmp_8_s1/Q matrix_key_1/key_8_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.694
11 0.694 matrix_key_1/tmp_14_s1/Q matrix_key_1/key_14_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.694
12 0.700 clkdiv_1/count_1_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.700
13 0.786 clkdiv_1/count_1_s0/Q clkdiv_1/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.786
14 0.786 clkdiv_1/count_7_s0/Q clkdiv_1/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.786
15 0.786 clkdiv_1/count_10_s0/Q clkdiv_1/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.786
16 0.786 clkdiv_1/count_14_s0/Q clkdiv_1/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.786
17 0.786 matrix_key_1/index_1_s0/Q matrix_key_1/index_1_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.786
18 0.787 clkdiv_1/count_3_s0/Q clkdiv_1/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.787
19 0.787 clkdiv_1/count_11_s0/Q clkdiv_1/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.787
20 0.787 clkdiv_1/count_15_s0/Q clkdiv_1/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.787
21 0.788 clkdiv_1/count_18_s0/Q clkdiv_1/count_18_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.788
22 0.788 clkdiv_1/count_19_s0/Q clkdiv_1/count_19_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.788
23 0.830 matrix_key_1/tmp_4_s1/Q matrix_key_1/key_4_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.830
24 0.830 matrix_key_1/tmp_15_s1/Q matrix_key_1/key_15_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.830
25 0.955 matrix_key_1/tmp_1_s1/Q matrix_key_1/key_1_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.955

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_19_s0
2 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_17_s0
3 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_13_s0
4 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_5_s0
5 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_6_s0
6 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_14_s0
7 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_7_s0
8 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_8_s0
9 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_18_s0
10 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_15_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 30.786
Data Arrival Time 8.223
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_8_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.784 0.609 tINS FF 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.409 0.625 tNET FF 1 R8C13[1][A] clkdiv_1/n54_s4/I0
8.223 0.814 tINS FF 1 R8C13[1][A] clkdiv_1/n54_s4/F
8.223 0.000 tNET FF 1 R8C13[1][A] clkdiv_1/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C13[1][A] clkdiv_1/count_8_s0/CLK
39.009 -0.296 tSu 1 R8C13[1][A] clkdiv_1/count_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.052, 51.259%; route: 2.563, 43.037%; tC2Q: 0.340, 5.704%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path2

Path Summary:

Slack 30.836
Data Arrival Time 8.174
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.784 0.609 tINS FF 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.409 0.625 tNET FF 1 R8C12[1][A] clkdiv_1/n49_s4/I0
8.174 0.765 tINS FF 1 R8C12[1][A] clkdiv_1/n49_s4/F
8.174 0.000 tNET FF 1 R8C12[1][A] clkdiv_1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C12[1][A] clkdiv_1/count_13_s0/CLK
39.009 -0.296 tSu 1 R8C12[1][A] clkdiv_1/count_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.003, 50.849%; route: 2.563, 43.399%; tC2Q: 0.340, 5.752%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path3

Path Summary:

Slack 30.844
Data Arrival Time 8.165
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.784 0.609 tINS FF 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.400 0.616 tNET FF 1 R9C13[2][A] clkdiv_1/n50_s2/I0
8.165 0.765 tINS FF 1 R9C13[2][A] clkdiv_1/n50_s2/F
8.165 0.000 tNET FF 1 R9C13[2][A] clkdiv_1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C13[2][A] clkdiv_1/count_12_s0/CLK
39.009 -0.296 tSu 1 R9C13[2][A] clkdiv_1/count_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.003, 50.921%; route: 2.554, 43.319%; tC2Q: 0.340, 5.760%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path4

Path Summary:

Slack 31.027
Data Arrival Time 7.982
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.784 0.609 tINS FF 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.168 0.383 tNET FF 1 R11C12[3][A] clkdiv_1/n62_s11/I1
7.982 0.814 tINS FF 1 R11C12[3][A] clkdiv_1/n62_s11/F
7.982 0.000 tNET FF 1 R11C12[3][A] clkdiv_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C12[3][A] clkdiv_1/count_0_s0/CLK
39.009 -0.296 tSu 1 R11C12[3][A] clkdiv_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.052, 53.424%; route: 2.321, 40.632%; tC2Q: 0.340, 5.945%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path5

Path Summary:

Slack 31.070
Data Arrival Time 7.939
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.784 0.609 tINS FF 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.174 0.390 tNET FF 1 R7C12[1][B] clkdiv_1/n61_s3/I1
7.939 0.765 tINS FF 1 R7C12[1][B] clkdiv_1/n61_s3/F
7.939 0.000 tNET FF 1 R7C12[1][B] clkdiv_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R7C12[1][B] clkdiv_1/count_1_s0/CLK
39.009 -0.296 tSu 1 R7C12[1][B] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.003, 52.952%; route: 2.328, 41.058%; tC2Q: 0.340, 5.990%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path6

Path Summary:

Slack 31.070
Data Arrival Time 7.939
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.784 0.609 tINS FF 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.174 0.390 tNET FF 1 R7C12[0][B] clkdiv_1/n60_s5/I0
7.939 0.765 tINS FF 1 R7C12[0][B] clkdiv_1/n60_s5/F
7.939 0.000 tNET FF 1 R7C12[0][B] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R7C12[0][B] clkdiv_1/count_2_s0/CLK
39.009 -0.296 tSu 1 R7C12[0][B] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.003, 52.952%; route: 2.328, 41.058%; tC2Q: 0.340, 5.990%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path7

Path Summary:

Slack 31.070
Data Arrival Time 7.939
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.784 0.609 tINS FF 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.174 0.390 tNET FF 1 R7C12[1][A] clkdiv_1/n56_s5/I0
7.939 0.765 tINS FF 1 R7C12[1][A] clkdiv_1/n56_s5/F
7.939 0.000 tNET FF 1 R7C12[1][A] clkdiv_1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R7C12[1][A] clkdiv_1/count_6_s0/CLK
39.009 -0.296 tSu 1 R7C12[1][A] clkdiv_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.003, 52.952%; route: 2.328, 41.058%; tC2Q: 0.340, 5.990%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path8

Path Summary:

Slack 31.130
Data Arrival Time 7.879
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.784 0.609 tINS FF 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.416 0.631 tNET FF 1 R8C13[2][B] clkdiv_1/n59_s4/I0
7.879 0.464 tINS FF 1 R8C13[2][B] clkdiv_1/n59_s4/F
7.879 0.000 tNET FF 1 R8C13[2][B] clkdiv_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C13[2][B] clkdiv_1/count_3_s0/CLK
39.009 -0.296 tSu 1 R8C13[2][B] clkdiv_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.702, 48.152%; route: 2.569, 45.794%; tC2Q: 0.340, 6.053%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path9

Path Summary:

Slack 31.130
Data Arrival Time 7.879
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_19_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.784 0.609 tINS FF 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.416 0.631 tNET FF 1 R8C13[1][B] clkdiv_1/n43_s4/I0
7.879 0.464 tINS FF 1 R8C13[1][B] clkdiv_1/n43_s4/F
7.879 0.000 tNET FF 1 R8C13[1][B] clkdiv_1/count_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C13[1][B] clkdiv_1/count_19_s0/CLK
39.009 -0.296 tSu 1 R8C13[1][B] clkdiv_1/count_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.702, 48.152%; route: 2.569, 45.794%; tC2Q: 0.340, 6.053%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path10

Path Summary:

Slack 31.152
Data Arrival Time 7.857
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.769 0.594 tINS FR 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.093 0.323 tNET RR 1 R9C11[1][A] clkdiv_1/n53_s6/I0
7.857 0.765 tINS RF 1 R9C11[1][A] clkdiv_1/n53_s6/F
7.857 0.000 tNET FF 1 R9C11[1][A] clkdiv_1/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C11[1][A] clkdiv_1/count_9_s0/CLK
39.009 -0.296 tSu 1 R9C11[1][A] clkdiv_1/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.988, 53.460%; route: 2.261, 40.463%; tC2Q: 0.340, 6.077%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path11

Path Summary:

Slack 31.152
Data Arrival Time 7.857
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.769 0.594 tINS FR 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.093 0.323 tNET RR 1 R9C11[1][B] clkdiv_1/n52_s5/I0
7.857 0.765 tINS RF 1 R9C11[1][B] clkdiv_1/n52_s5/F
7.857 0.000 tNET FF 1 R9C11[1][B] clkdiv_1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C11[1][B] clkdiv_1/count_10_s0/CLK
39.009 -0.296 tSu 1 R9C11[1][B] clkdiv_1/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.988, 53.460%; route: 2.261, 40.463%; tC2Q: 0.340, 6.077%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path12

Path Summary:

Slack 31.155
Data Arrival Time 7.855
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.769 0.594 tINS FR 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.090 0.321 tNET RR 1 R8C12[0][A] clkdiv_1/n57_s5/I0
7.855 0.765 tINS RF 1 R8C12[0][A] clkdiv_1/n57_s5/F
7.855 0.000 tNET FF 1 R8C12[0][A] clkdiv_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C12[0][A] clkdiv_1/count_5_s0/CLK
39.009 -0.296 tSu 1 R8C12[0][A] clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.988, 53.488%; route: 2.258, 40.432%; tC2Q: 0.340, 6.080%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path13

Path Summary:

Slack 31.310
Data Arrival Time 7.699
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.769 0.594 tINS FR 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.090 0.321 tNET RR 1 R9C11[0][A] clkdiv_1/n58_s4/I0
7.699 0.609 tINS RF 1 R9C11[0][A] clkdiv_1/n58_s4/F
7.699 0.000 tNET FF 1 R9C11[0][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C11[0][A] clkdiv_1/count_4_s0/CLK
39.009 -0.296 tSu 1 R9C11[0][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.832, 52.155%; route: 2.258, 41.590%; tC2Q: 0.340, 6.254%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path14

Path Summary:

Slack 31.310
Data Arrival Time 7.699
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.769 0.594 tINS FR 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.090 0.321 tNET RR 1 R9C11[2][B] clkdiv_1/n51_s4/I0
7.699 0.609 tINS RF 1 R9C11[2][B] clkdiv_1/n51_s4/F
7.699 0.000 tNET FF 1 R9C11[2][B] clkdiv_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C11[2][B] clkdiv_1/count_11_s0/CLK
39.009 -0.296 tSu 1 R9C11[2][B] clkdiv_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.832, 52.155%; route: 2.258, 41.590%; tC2Q: 0.340, 6.254%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path15

Path Summary:

Slack 31.456
Data Arrival Time 7.554
Data Required Time 39.009
From clkdiv_1/count_15_s0
To clkdiv_1/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
2.608 0.340 tC2Q RF 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
3.572 0.963 tNET FF 1 R11C13[0][B] clkdiv_1/n64_s85/I1
4.386 0.814 tINS FF 2 R11C13[0][B] clkdiv_1/n64_s85/F
4.752 0.366 tNET FF 1 R9C13[0][B] clkdiv_1/n62_s8/I1
5.567 0.814 tINS FF 1 R9C13[0][B] clkdiv_1/n62_s8/F
6.175 0.608 tNET FF 1 R9C12[2][B] clkdiv_1/n62_s4/I2
6.769 0.594 tINS FR 15 R9C12[2][B] clkdiv_1/n62_s4/F
7.090 0.321 tNET RR 1 R8C12[1][B] clkdiv_1/n55_s5/I0
7.554 0.464 tINS RF 1 R8C12[1][B] clkdiv_1/n55_s5/F
7.554 0.000 tNET FF 1 R8C12[1][B] clkdiv_1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C12[1][B] clkdiv_1/count_7_s0/CLK
39.009 -0.296 tSu 1 R8C12[1][B] clkdiv_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.687, 50.840%; route: 2.258, 42.733%; tC2Q: 0.340, 6.426%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path16

Path Summary:

Slack 32.090
Data Arrival Time 6.920
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/clk_out_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C12[3][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R11C12[3][A] clkdiv_1/count_0_s0/Q
3.336 0.728 tNET FF 1 R8C12[0][B] clkdiv_1/n58_s3/I1
3.945 0.609 tINS FF 11 R8C12[0][B] clkdiv_1/n58_s3/F
4.929 0.984 tNET FF 1 R9C13[3][A] clkdiv_1/n64_s83/I1
5.538 0.609 tINS FF 1 R9C13[3][A] clkdiv_1/n64_s83/F
5.542 0.004 tNET FF 1 R9C13[2][B] clkdiv_1/n64_s80/I0
6.151 0.609 tINS FF 1 R9C13[2][B] clkdiv_1/n64_s80/F
6.155 0.004 tNET FF 1 R9C13[1][A] clkdiv_1/n64_s88/I0
6.920 0.765 tINS FF 1 R9C13[1][A] clkdiv_1/n64_s88/F
6.920 0.000 tNET FF 1 R9C13[1][A] clkdiv_1/clk_out_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C13[1][A] clkdiv_1/clk_out_s0/CLK
39.009 -0.296 tSu 1 R9C13[1][A] clkdiv_1/clk_out_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.592, 55.732%; route: 1.719, 36.966%; tC2Q: 0.340, 7.302%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path17

Path Summary:

Slack 32.151
Data Arrival Time 6.858
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/count_18_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C12[3][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R11C12[3][A] clkdiv_1/count_0_s0/Q
3.336 0.728 tNET FF 1 R8C12[0][B] clkdiv_1/n58_s3/I1
3.945 0.609 tINS FF 11 R8C12[0][B] clkdiv_1/n58_s3/F
4.585 0.640 tNET FF 1 R9C12[2][A] clkdiv_1/n49_s3/I1
5.049 0.464 tINS FF 7 R9C12[2][A] clkdiv_1/n49_s3/F
5.430 0.381 tNET FF 1 R11C12[1][B] clkdiv_1/n44_s3/I1
6.039 0.609 tINS FF 1 R11C12[1][B] clkdiv_1/n44_s3/F
6.044 0.004 tNET FF 1 R11C12[2][B] clkdiv_1/n44_s4/I0
6.858 0.814 tINS FF 1 R11C12[2][B] clkdiv_1/n44_s4/F
6.858 0.000 tNET FF 1 R11C12[2][B] clkdiv_1/count_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C12[2][B] clkdiv_1/count_18_s0/CLK
39.009 -0.296 tSu 1 R11C12[2][B] clkdiv_1/count_18_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.496, 54.399%; route: 1.753, 38.201%; tC2Q: 0.340, 7.401%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path18

Path Summary:

Slack 32.271
Data Arrival Time 6.739
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C12[3][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R11C12[3][A] clkdiv_1/count_0_s0/Q
3.336 0.728 tNET FF 1 R8C12[0][B] clkdiv_1/n58_s3/I1
3.945 0.609 tINS FF 11 R8C12[0][B] clkdiv_1/n58_s3/F
4.585 0.640 tNET FF 1 R9C12[2][A] clkdiv_1/n49_s3/I1
5.049 0.464 tINS FF 7 R9C12[2][A] clkdiv_1/n49_s3/F
5.662 0.613 tNET FF 1 R8C13[0][A] clkdiv_1/n47_s3/I2
6.271 0.609 tINS FF 1 R8C13[0][A] clkdiv_1/n47_s3/F
6.275 0.004 tNET FF 1 R8C13[0][B] clkdiv_1/n47_s4/I0
6.739 0.464 tINS FF 1 R8C13[0][B] clkdiv_1/n47_s4/F
6.739 0.000 tNET FF 1 R8C13[0][B] clkdiv_1/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
39.009 -0.296 tSu 1 R8C13[0][B] clkdiv_1/count_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.146, 48.010%; route: 1.984, 44.392%; tC2Q: 0.340, 7.598%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path19

Path Summary:

Slack 32.502
Data Arrival Time 6.507
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C12[3][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R11C12[3][A] clkdiv_1/count_0_s0/Q
3.336 0.728 tNET FF 1 R8C12[0][B] clkdiv_1/n58_s3/I1
3.945 0.609 tINS FF 11 R8C12[0][B] clkdiv_1/n58_s3/F
4.585 0.640 tNET FF 1 R9C12[2][A] clkdiv_1/n49_s3/I1
5.049 0.464 tINS FF 7 R9C12[2][A] clkdiv_1/n49_s3/F
5.430 0.381 tNET FF 1 R11C12[1][A] clkdiv_1/n46_s3/I3
6.039 0.609 tINS FF 1 R11C12[1][A] clkdiv_1/n46_s3/F
6.044 0.004 tNET FF 1 R11C12[0][A] clkdiv_1/n46_s4/I0
6.507 0.464 tINS FF 1 R11C12[0][A] clkdiv_1/n46_s4/F
6.507 0.000 tNET FF 1 R11C12[0][A] clkdiv_1/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C12[0][A] clkdiv_1/count_16_s0/CLK
39.009 -0.296 tSu 1 R11C12[0][A] clkdiv_1/count_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.146, 50.628%; route: 1.753, 41.359%; tC2Q: 0.340, 8.013%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path20

Path Summary:

Slack 32.970
Data Arrival Time 6.039
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C12[3][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R11C12[3][A] clkdiv_1/count_0_s0/Q
3.336 0.728 tNET FF 1 R8C12[0][B] clkdiv_1/n58_s3/I1
3.945 0.609 tINS FF 11 R8C12[0][B] clkdiv_1/n58_s3/F
4.585 0.640 tNET FF 1 R9C12[2][A] clkdiv_1/n49_s3/I1
5.049 0.464 tINS FF 7 R9C12[2][A] clkdiv_1/n49_s3/F
5.430 0.381 tNET FF 1 R11C12[0][B] clkdiv_1/n48_s3/I1
6.039 0.609 tINS FF 1 R11C12[0][B] clkdiv_1/n48_s3/F
6.039 0.000 tNET FF 1 R11C12[0][B] clkdiv_1/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C12[0][B] clkdiv_1/count_14_s0/CLK
39.009 -0.296 tSu 1 R11C12[0][B] clkdiv_1/count_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 1.682, 44.609%; route: 1.749, 46.384%; tC2Q: 0.340, 9.007%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path21

Path Summary:

Slack 33.115
Data Arrival Time 5.894
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C12[3][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R11C12[3][A] clkdiv_1/count_0_s0/Q
3.336 0.728 tNET FF 1 R8C12[0][B] clkdiv_1/n58_s3/I1
3.945 0.609 tINS FF 11 R8C12[0][B] clkdiv_1/n58_s3/F
4.585 0.640 tNET FF 1 R9C12[2][A] clkdiv_1/n49_s3/I1
5.049 0.464 tINS FF 7 R9C12[2][A] clkdiv_1/n49_s3/F
5.430 0.381 tNET FF 1 R11C12[2][A] clkdiv_1/n45_s4/I0
5.894 0.464 tINS FF 1 R11C12[2][A] clkdiv_1/n45_s4/F
5.894 0.000 tNET FF 1 R11C12[2][A] clkdiv_1/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 21 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C12[2][A] clkdiv_1/count_17_s0/CLK
39.009 -0.296 tSu 1 R11C12[2][A] clkdiv_1/count_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 4
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 1.537, 42.390%; route: 1.749, 48.242%; tC2Q: 0.340, 9.368%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path22

Path Summary:

Slack 1481476.500
Data Arrival Time 4.000
Data Required Time 1481480.500
From matrix_key_1/index_0_s0
To matrix_key_1/tc_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.762 0.762 tNET RR 1 R9C7[1][A] matrix_key_1/index_0_s0/CLK
1.101 0.340 tC2Q RR 12 R9C7[1][A] matrix_key_1/index_0_s0/Q
1.430 0.328 tNET RR 1 R9C8[2][B] matrix_key_1/key_15_s2/I0
2.244 0.814 tINS RF 17 R9C8[2][B] matrix_key_1/key_15_s2/F
4.062 1.818 tNET FF 1 IOR15[B] matrix_key_1/tc_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1481480.000 1481480.000 active clock edge time
1481480.000 0.000 clk50hz
1481480.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
1481480.750 0.762 tNET RR 1 IOR15[B] matrix_key_1/tc_s0/CLK
1481480.500 -0.296 tSu 1 IOR15[B] matrix_key_1/tc_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 1481480.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.762, 100.000%
Arrival Data Path Delay cell: 0.814, 24.674%; route: 2.147, 65.036%; tC2Q: 0.340, 10.290%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.762, 100.000%

Path23

Path Summary:

Slack 1481476.625
Data Arrival Time 3.875
Data Required Time 1481480.500
From matrix_key_1/index_0_s0
To matrix_key_1/tmp_15_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.762 0.762 tNET RR 1 R9C7[1][A] matrix_key_1/index_0_s0/CLK
1.101 0.340 tC2Q RF 12 R9C7[1][A] matrix_key_1/index_0_s0/Q
1.728 0.627 tNET FF 1 R7C7[0][B] matrix_key_1/n118_s2/I1
2.493 0.765 tINS FF 4 R7C7[0][B] matrix_key_1/n118_s2/F
3.936 1.443 tNET FF 1 R7C11[0][A] matrix_key_1/tmp_15_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1481480.000 1481480.000 active clock edge time
1481480.000 0.000 clk50hz
1481480.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
1481480.750 0.762 tNET RR 1 R7C11[0][A] matrix_key_1/tmp_15_s1/CLK
1481480.500 -0.296 tSu 1 R7C11[0][A] matrix_key_1/tmp_15_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 1481480.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.762, 100.000%
Arrival Data Path Delay cell: 0.765, 24.093%; route: 2.070, 65.207%; tC2Q: 0.340, 10.700%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.762, 100.000%

Path24

Path Summary:

Slack 1481476.875
Data Arrival Time 3.625
Data Required Time 1481480.500
From matrix_key_1/index_0_s0
To matrix_key_1/tmp_11_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.762 0.762 tNET RR 1 R9C7[1][A] matrix_key_1/index_0_s0/CLK
1.101 0.340 tC2Q RR 12 R9C7[1][A] matrix_key_1/index_0_s0/Q
1.418 0.317 tNET RR 1 R8C7[0][B] matrix_key_1/n122_s2/I1
2.232 0.814 tINS RF 4 R8C7[0][B] matrix_key_1/n122_s2/F
3.671 1.439 tNET FF 1 R8C11[1][A] matrix_key_1/tmp_11_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1481480.000 1481480.000 active clock edge time
1481480.000 0.000 clk50hz
1481480.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
1481480.750 0.762 tNET RR 1 R8C11[1][A] matrix_key_1/tmp_11_s1/CLK
1481480.500 -0.296 tSu 1 R8C11[1][A] matrix_key_1/tmp_11_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 1481480.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.762, 100.000%
Arrival Data Path Delay cell: 0.814, 27.993%; route: 1.755, 60.332%; tC2Q: 0.340, 11.674%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.762, 100.000%

Path25

Path Summary:

Slack 1481476.875
Data Arrival Time 3.625
Data Required Time 1481480.500
From matrix_key_1/index_0_s0
To matrix_key_1/tmp_14_s1
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.762 0.762 tNET RR 1 R9C7[1][A] matrix_key_1/index_0_s0/CLK
1.101 0.340 tC2Q RF 12 R9C7[1][A] matrix_key_1/index_0_s0/Q
1.728 0.627 tNET FF 1 R7C7[0][B] matrix_key_1/n118_s2/I1
2.493 0.765 tINS FF 4 R7C7[0][B] matrix_key_1/n118_s2/F
3.577 1.084 tNET FF 1 R7C9[2][B] matrix_key_1/tmp_14_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
1481480.000 1481480.000 active clock edge time
1481480.000 0.000 clk50hz
1481480.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
1481480.750 0.762 tNET RR 1 R7C9[2][B] matrix_key_1/tmp_14_s1/CLK
1481480.500 -0.296 tSu 1 R7C9[2][B] matrix_key_1/tmp_14_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 1481480.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.762, 100.000%
Arrival Data Path Delay cell: 0.765, 27.166%; route: 1.711, 60.769%; tC2Q: 0.340, 12.065%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.762, 100.000%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_1/count_8_s0
To clkdiv_1/count_8_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C13[1][A] clkdiv_1/count_8_s0/CLK
1.776 0.247 tC2Q RR 5 R8C13[1][A] clkdiv_1/count_8_s0/Q
1.779 0.003 tNET RR 1 R8C13[1][A] clkdiv_1/n54_s4/I2
2.055 0.276 tINS RF 1 R8C13[1][A] clkdiv_1/n54_s4/F
2.055 0.000 tNET FF 1 R8C13[1][A] clkdiv_1/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C13[1][A] clkdiv_1/count_8_s0/CLK
1.529 0.000 tHld 1 R8C13[1][A] clkdiv_1/count_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path2

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_1/count_9_s0
To clkdiv_1/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[1][A] clkdiv_1/count_9_s0/CLK
1.776 0.247 tC2Q RR 6 R9C11[1][A] clkdiv_1/count_9_s0/Q
1.779 0.003 tNET RR 1 R9C11[1][A] clkdiv_1/n53_s6/I2
2.055 0.276 tINS RF 1 R9C11[1][A] clkdiv_1/n53_s6/F
2.055 0.000 tNET FF 1 R9C11[1][A] clkdiv_1/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[1][A] clkdiv_1/count_9_s0/CLK
1.529 0.000 tHld 1 R9C11[1][A] clkdiv_1/count_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path3

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_1/count_13_s0
To clkdiv_1/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C12[1][A] clkdiv_1/count_13_s0/CLK
1.776 0.247 tC2Q RR 7 R8C12[1][A] clkdiv_1/count_13_s0/Q
1.779 0.003 tNET RR 1 R8C12[1][A] clkdiv_1/n49_s4/I1
2.055 0.276 tINS RF 1 R8C12[1][A] clkdiv_1/n49_s4/F
2.055 0.000 tNET FF 1 R8C12[1][A] clkdiv_1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C12[1][A] clkdiv_1/count_13_s0/CLK
1.529 0.000 tHld 1 R8C12[1][A] clkdiv_1/count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path4

Path Summary:

Slack 0.526
Data Arrival Time 1.084
Data Required Time 0.558
From matrix_key_1/index_0_s0
To matrix_key_1/index_0_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R9C7[1][A] matrix_key_1/index_0_s0/CLK
0.805 0.247 tC2Q RR 12 R9C7[1][A] matrix_key_1/index_0_s0/Q
0.809 0.003 tNET RR 1 R9C7[1][A] matrix_key_1/n137_s2/I0
1.084 0.276 tINS RF 1 R9C7[1][A] matrix_key_1/n137_s2/F
1.084 0.000 tNET FF 1 R9C7[1][A] matrix_key_1/index_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R9C7[1][A] matrix_key_1/index_0_s0/CLK
0.558 0.000 tHld 1 R9C7[1][A] matrix_key_1/index_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path5

Path Summary:

Slack 0.526
Data Arrival Time 1.084
Data Required Time 0.558
From matrix_key_1/index_2_s0
To matrix_key_1/index_2_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R9C8[0][A] matrix_key_1/index_2_s0/CLK
0.805 0.247 tC2Q RR 10 R9C8[0][A] matrix_key_1/index_2_s0/Q
0.809 0.003 tNET RR 1 R9C8[0][A] matrix_key_1/n135_s0/I2
1.084 0.276 tINS RF 1 R9C8[0][A] matrix_key_1/n135_s0/F
1.084 0.000 tNET FF 1 R9C8[0][A] matrix_key_1/index_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R9C8[0][A] matrix_key_1/index_2_s0/CLK
0.558 0.000 tHld 1 R9C8[0][A] matrix_key_1/index_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path6

Path Summary:

Slack 0.527
Data Arrival Time 2.056
Data Required Time 1.529
From clkdiv_1/count_4_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[0][A] clkdiv_1/count_4_s0/CLK
1.776 0.247 tC2Q RR 11 R9C11[0][A] clkdiv_1/count_4_s0/Q
1.780 0.004 tNET RR 1 R9C11[0][A] clkdiv_1/n58_s4/I1
2.056 0.276 tINS RF 1 R9C11[0][A] clkdiv_1/n58_s4/F
2.056 0.000 tNET FF 1 R9C11[0][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[0][A] clkdiv_1/count_4_s0/CLK
1.529 0.000 tHld 1 R9C11[0][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path7

Path Summary:

Slack 0.527
Data Arrival Time 2.056
Data Required Time 1.529
From clkdiv_1/count_5_s0
To clkdiv_1/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C12[0][A] clkdiv_1/count_5_s0/CLK
1.776 0.247 tC2Q RR 7 R8C12[0][A] clkdiv_1/count_5_s0/Q
1.780 0.004 tNET RR 1 R8C12[0][A] clkdiv_1/n57_s5/I1
2.056 0.276 tINS RF 1 R8C12[0][A] clkdiv_1/n57_s5/F
2.056 0.000 tNET FF 1 R8C12[0][A] clkdiv_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C12[0][A] clkdiv_1/count_5_s0/CLK
1.529 0.000 tHld 1 R8C12[0][A] clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path8

Path Summary:

Slack 0.527
Data Arrival Time 2.056
Data Required Time 1.529
From clkdiv_1/count_6_s0
To clkdiv_1/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[1][A] clkdiv_1/count_6_s0/CLK
1.776 0.247 tC2Q RR 7 R7C12[1][A] clkdiv_1/count_6_s0/Q
1.780 0.004 tNET RR 1 R7C12[1][A] clkdiv_1/n56_s5/I2
2.056 0.276 tINS RF 1 R7C12[1][A] clkdiv_1/n56_s5/F
2.056 0.000 tNET FF 1 R7C12[1][A] clkdiv_1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[1][A] clkdiv_1/count_6_s0/CLK
1.529 0.000 tHld 1 R7C12[1][A] clkdiv_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path9

Path Summary:

Slack 0.662
Data Arrival Time 2.191
Data Required Time 1.529
From clkdiv_1/count_17_s0
To clkdiv_1/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[2][A] clkdiv_1/count_17_s0/CLK
1.776 0.247 tC2Q RR 4 R11C12[2][A] clkdiv_1/count_17_s0/Q
1.779 0.003 tNET RR 1 R11C12[2][A] clkdiv_1/n45_s4/I2
2.191 0.412 tINS RR 1 R11C12[2][A] clkdiv_1/n45_s4/F
2.191 0.000 tNET RR 1 R11C12[2][A] clkdiv_1/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[2][A] clkdiv_1/count_17_s0/CLK
1.529 0.000 tHld 1 R11C12[2][A] clkdiv_1/count_17_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.412, 62.189%; route: 0.003, 0.528%; tC2Q: 0.247, 37.283%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path10

Path Summary:

Slack 0.694
Data Arrival Time 1.252
Data Required Time 0.558
From matrix_key_1/tmp_8_s1
To matrix_key_1/key_8_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R8C9[2][A] matrix_key_1/tmp_8_s1/CLK
0.805 0.247 tC2Q RF 1 R8C9[2][A] matrix_key_1/tmp_8_s1/Q
0.977 0.171 tNET FF 1 R7C9[1][B] matrix_key_1/n109_s3/I0
1.252 0.276 tINS FF 1 R7C9[1][B] matrix_key_1/n109_s3/F
1.252 0.000 tNET FF 1 R7C9[1][B] matrix_key_1/key_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R7C9[1][B] matrix_key_1/key_8_s0/CLK
0.558 0.000 tHld 1 R7C9[1][B] matrix_key_1/key_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.276, 39.719%; route: 0.171, 24.691%; tC2Q: 0.247, 35.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path11

Path Summary:

Slack 0.694
Data Arrival Time 1.252
Data Required Time 0.558
From matrix_key_1/tmp_14_s1
To matrix_key_1/key_14_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R7C9[2][B] matrix_key_1/tmp_14_s1/CLK
0.805 0.247 tC2Q RF 1 R7C9[2][B] matrix_key_1/tmp_14_s1/Q
0.977 0.171 tNET FF 1 R7C10[1][A] matrix_key_1/n103_s3/I0
1.252 0.276 tINS FF 1 R7C10[1][A] matrix_key_1/n103_s3/F
1.252 0.000 tNET FF 1 R7C10[1][A] matrix_key_1/key_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R7C10[1][A] matrix_key_1/key_14_s0/CLK
0.558 0.000 tHld 1 R7C10[1][A] matrix_key_1/key_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.276, 39.719%; route: 0.171, 24.691%; tC2Q: 0.247, 35.590%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path12

Path Summary:

Slack 0.700
Data Arrival Time 2.228
Data Required Time 1.529
From clkdiv_1/count_1_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[1][B] clkdiv_1/count_1_s0/CLK
1.776 0.247 tC2Q RR 4 R7C12[1][B] clkdiv_1/count_1_s0/Q
1.953 0.177 tNET RR 1 R7C12[0][B] clkdiv_1/n60_s5/I1
2.228 0.276 tINS RF 1 R7C12[0][B] clkdiv_1/n60_s5/F
2.228 0.000 tNET FF 1 R7C12[0][B] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[0][B] clkdiv_1/count_2_s0/CLK
1.529 0.000 tHld 1 R7C12[0][B] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 39.403%; route: 0.177, 25.289%; tC2Q: 0.247, 35.307%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path13

Path Summary:

Slack 0.786
Data Arrival Time 2.315
Data Required Time 1.529
From clkdiv_1/count_1_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[1][B] clkdiv_1/count_1_s0/CLK
1.776 0.247 tC2Q RR 4 R7C12[1][B] clkdiv_1/count_1_s0/Q
1.778 0.003 tNET RR 1 R7C12[1][B] clkdiv_1/n61_s3/I2
2.315 0.536 tINS RR 1 R7C12[1][B] clkdiv_1/n61_s3/F
2.315 0.000 tNET RR 1 R7C12[1][B] clkdiv_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[1][B] clkdiv_1/count_1_s0/CLK
1.529 0.000 tHld 1 R7C12[1][B] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path14

Path Summary:

Slack 0.786
Data Arrival Time 2.315
Data Required Time 1.529
From clkdiv_1/count_7_s0
To clkdiv_1/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C12[1][B] clkdiv_1/count_7_s0/CLK
1.776 0.247 tC2Q RR 5 R8C12[1][B] clkdiv_1/count_7_s0/Q
1.778 0.003 tNET RR 1 R8C12[1][B] clkdiv_1/n55_s5/I2
2.315 0.536 tINS RR 1 R8C12[1][B] clkdiv_1/n55_s5/F
2.315 0.000 tNET RR 1 R8C12[1][B] clkdiv_1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C12[1][B] clkdiv_1/count_7_s0/CLK
1.529 0.000 tHld 1 R8C12[1][B] clkdiv_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path15

Path Summary:

Slack 0.786
Data Arrival Time 2.315
Data Required Time 1.529
From clkdiv_1/count_10_s0
To clkdiv_1/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[1][B] clkdiv_1/count_10_s0/CLK
1.776 0.247 tC2Q RR 5 R9C11[1][B] clkdiv_1/count_10_s0/Q
1.778 0.003 tNET RR 1 R9C11[1][B] clkdiv_1/n52_s5/I2
2.315 0.536 tINS RR 1 R9C11[1][B] clkdiv_1/n52_s5/F
2.315 0.000 tNET RR 1 R9C11[1][B] clkdiv_1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[1][B] clkdiv_1/count_10_s0/CLK
1.529 0.000 tHld 1 R9C11[1][B] clkdiv_1/count_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path16

Path Summary:

Slack 0.786
Data Arrival Time 2.315
Data Required Time 1.529
From clkdiv_1/count_14_s0
To clkdiv_1/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[0][B] clkdiv_1/count_14_s0/CLK
1.776 0.247 tC2Q RR 5 R11C12[0][B] clkdiv_1/count_14_s0/Q
1.778 0.003 tNET RR 1 R11C12[0][B] clkdiv_1/n48_s3/I2
2.315 0.536 tINS RR 1 R11C12[0][B] clkdiv_1/n48_s3/F
2.315 0.000 tNET RR 1 R11C12[0][B] clkdiv_1/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[0][B] clkdiv_1/count_14_s0/CLK
1.529 0.000 tHld 1 R11C12[0][B] clkdiv_1/count_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path17

Path Summary:

Slack 0.786
Data Arrival Time 1.344
Data Required Time 0.558
From matrix_key_1/index_1_s0
To matrix_key_1/index_1_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R9C7[0][B] matrix_key_1/index_1_s0/CLK
0.805 0.247 tC2Q RR 11 R9C7[0][B] matrix_key_1/index_1_s0/Q
0.808 0.003 tNET RR 1 R9C7[0][B] matrix_key_1/n136_s0/I1
1.344 0.536 tINS RR 1 R9C7[0][B] matrix_key_1/n136_s0/F
1.344 0.000 tNET RR 1 R9C7[0][B] matrix_key_1/index_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R9C7[0][B] matrix_key_1/index_1_s0/CLK
0.558 0.000 tHld 1 R9C7[0][B] matrix_key_1/index_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path18

Path Summary:

Slack 0.787
Data Arrival Time 2.315
Data Required Time 1.529
From clkdiv_1/count_3_s0
To clkdiv_1/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C13[2][B] clkdiv_1/count_3_s0/CLK
1.776 0.247 tC2Q RR 2 R8C13[2][B] clkdiv_1/count_3_s0/Q
1.778 0.002 tNET RR 1 R8C13[2][B] clkdiv_1/n59_s4/I2
2.315 0.538 tINS RR 1 R8C13[2][B] clkdiv_1/n59_s4/F
2.315 0.000 tNET RR 1 R8C13[2][B] clkdiv_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C13[2][B] clkdiv_1/count_3_s0/CLK
1.529 0.000 tHld 1 R8C13[2][B] clkdiv_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.538, 68.381%; route: 0.002, 0.222%; tC2Q: 0.247, 31.396%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path19

Path Summary:

Slack 0.787
Data Arrival Time 2.315
Data Required Time 1.529
From clkdiv_1/count_11_s0
To clkdiv_1/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[2][B] clkdiv_1/count_11_s0/CLK
1.776 0.247 tC2Q RR 4 R9C11[2][B] clkdiv_1/count_11_s0/Q
1.778 0.002 tNET RR 1 R9C11[2][B] clkdiv_1/n51_s4/I2
2.315 0.538 tINS RR 1 R9C11[2][B] clkdiv_1/n51_s4/F
2.315 0.000 tNET RR 1 R9C11[2][B] clkdiv_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[2][B] clkdiv_1/count_11_s0/CLK
1.529 0.000 tHld 1 R9C11[2][B] clkdiv_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.538, 68.381%; route: 0.002, 0.222%; tC2Q: 0.247, 31.396%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path20

Path Summary:

Slack 0.787
Data Arrival Time 2.316
Data Required Time 1.529
From clkdiv_1/count_15_s0
To clkdiv_1/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
1.776 0.247 tC2Q RR 4 R8C13[0][B] clkdiv_1/count_15_s0/Q
1.779 0.003 tNET RR 1 R8C13[0][B] clkdiv_1/n47_s4/I1
2.316 0.536 tINS RR 1 R8C13[0][B] clkdiv_1/n47_s4/F
2.316 0.000 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C13[0][B] clkdiv_1/count_15_s0/CLK
1.529 0.000 tHld 1 R8C13[0][B] clkdiv_1/count_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.170%; route: 0.003, 0.445%; tC2Q: 0.247, 31.386%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path21

Path Summary:

Slack 0.788
Data Arrival Time 2.316
Data Required Time 1.529
From clkdiv_1/count_18_s0
To clkdiv_1/count_18_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[2][B] clkdiv_1/count_18_s0/CLK
1.776 0.247 tC2Q RR 4 R11C12[2][B] clkdiv_1/count_18_s0/Q
1.778 0.003 tNET RR 1 R11C12[2][B] clkdiv_1/n44_s4/I1
2.316 0.538 tINS RR 1 R11C12[2][B] clkdiv_1/n44_s4/F
2.316 0.000 tNET RR 1 R11C12[2][B] clkdiv_1/count_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[2][B] clkdiv_1/count_18_s0/CLK
1.529 0.000 tHld 1 R11C12[2][B] clkdiv_1/count_18_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.538, 68.305%; route: 0.003, 0.333%; tC2Q: 0.247, 31.361%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path22

Path Summary:

Slack 0.788
Data Arrival Time 2.317
Data Required Time 1.529
From clkdiv_1/count_19_s0
To clkdiv_1/count_19_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C13[1][B] clkdiv_1/count_19_s0/CLK
1.776 0.247 tC2Q RR 8 R8C13[1][B] clkdiv_1/count_19_s0/Q
1.780 0.004 tNET RR 1 R8C13[1][B] clkdiv_1/n43_s4/I2
2.317 0.536 tINS RR 1 R8C13[1][B] clkdiv_1/n43_s4/F
2.317 0.000 tNET RR 1 R8C13[1][B] clkdiv_1/count_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 21 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C13[1][B] clkdiv_1/count_19_s0/CLK
1.529 0.000 tHld 1 R8C13[1][B] clkdiv_1/count_19_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.094%; route: 0.004, 0.555%; tC2Q: 0.247, 31.351%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path23

Path Summary:

Slack 0.830
Data Arrival Time 1.389
Data Required Time 0.558
From matrix_key_1/tmp_4_s1
To matrix_key_1/key_4_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R9C9[1][A] matrix_key_1/tmp_4_s1/CLK
0.805 0.247 tC2Q RF 1 R9C9[1][A] matrix_key_1/tmp_4_s1/Q
0.977 0.171 tNET FF 1 R9C10[1][B] matrix_key_1/n113_s3/I0
1.389 0.412 tINS FR 1 R9C10[1][B] matrix_key_1/n113_s3/F
1.389 0.000 tNET RR 1 R9C10[1][B] matrix_key_1/key_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R9C10[1][B] matrix_key_1/key_4_s0/CLK
0.558 0.000 tHld 1 R9C10[1][B] matrix_key_1/key_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.412, 49.617%; route: 0.171, 20.637%; tC2Q: 0.247, 29.746%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path24

Path Summary:

Slack 0.830
Data Arrival Time 1.389
Data Required Time 0.558
From matrix_key_1/tmp_15_s1
To matrix_key_1/key_15_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R7C11[0][A] matrix_key_1/tmp_15_s1/CLK
0.805 0.247 tC2Q RF 1 R7C11[0][A] matrix_key_1/tmp_15_s1/Q
0.977 0.171 tNET FF 1 R7C10[1][B] matrix_key_1/n102_s3/I0
1.389 0.412 tINS FR 1 R7C10[1][B] matrix_key_1/n102_s3/F
1.389 0.000 tNET RR 1 R7C10[1][B] matrix_key_1/key_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R7C10[1][B] matrix_key_1/key_15_s0/CLK
0.558 0.000 tHld 1 R7C10[1][B] matrix_key_1/key_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.412, 49.617%; route: 0.171, 20.637%; tC2Q: 0.247, 29.746%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path25

Path Summary:

Slack 0.955
Data Arrival Time 1.513
Data Required Time 0.558
From matrix_key_1/tmp_1_s1
To matrix_key_1/key_1_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R9C9[2][A] matrix_key_1/tmp_1_s1/CLK
0.805 0.247 tC2Q RF 1 R9C9[2][A] matrix_key_1/tmp_1_s1/Q
0.977 0.171 tNET FF 1 R9C10[0][A] matrix_key_1/n116_s3/I0
1.513 0.536 tINS FR 1 R9C10[0][A] matrix_key_1/n116_s3/F
1.513 0.000 tNET RR 1 R9C10[0][A] matrix_key_1/key_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C13[1][A] clkdiv_1/clk_out_s0/Q
0.558 0.558 tNET RR 1 R9C10[0][A] matrix_key_1/key_1_s0/CLK
0.558 0.000 tHld 1 R9C10[0][A] matrix_key_1/key_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.536, 56.186%; route: 0.171, 17.946%; tC2Q: 0.247, 25.868%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_19_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_19_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_19_s0/CLK

MPW2

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_17_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_17_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_17_s0/CLK

MPW3

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_13_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_13_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_13_s0/CLK

MPW4

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_5_s0/CLK

MPW5

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_6_s0/CLK

MPW6

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_14_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_14_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_14_s0/CLK

MPW7

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_7_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_7_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_7_s0/CLK

MPW8

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_8_s0/CLK

MPW9

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_18_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_18_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_18_s0/CLK

MPW10

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_15_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_15_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_15_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
40 clk50hz 1481476.250 0.785
21 clk_d 30.786 0.195
17 key_15_5 1481476.500 1.818
15 n62_8 30.786 0.631
12 index[0] 1481476.375 0.627
11 count[4] 32.274 0.619
11 index[1] 1481476.500 0.327
11 n58_7 31.378 0.995
10 index[2] 1481476.750 0.322
8 count[19] 33.532 0.975

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R7C9 81.94%
R9C10 76.39%
R11C12 73.61%
R7C10 68.06%
R8C10 66.67%
R9C9 59.72%
R8C9 56.94%
R9C11 56.94%
R8C13 54.17%
R8C12 50.00%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk50hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 40000 [get_nets {clk50hz}]