Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\clkdiv.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\cntr4max.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\cntr4maxe.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\debounce.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\dec_lec.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\drv7seg.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\mux7seg.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\stopwatch.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\toggle.sv
GowinSynthesis Constraints File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Wed Dec 18 11:37:35 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module stopwatch
Synthesis Process Running parser:
    CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.064s, Peak memory usage = 157.285MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 157.730MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 157.793MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 157.875MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 158.062MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 158.168MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 158.215MB
    Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 158.293MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 158.320MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 158.324MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 158.324MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.593s, Elapsed time = 0h 0m 0.616s, Peak memory usage = 187.766MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.041s, Peak memory usage = 187.766MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.024s, Peak memory usage = 187.766MB
Total Time and Memory Usage CPU time = 0h 0m 0.73s, Elapsed time = 0h 0m 0.782s, Peak memory usage = 187.766MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 23
I/O Buf 23
    IBUF 3
    OBUF 20
Register 96
    DFFE 2
    DFFP 8
    DFFC 68
    DFFCE 18
LUT 231
    LUT2 27
    LUT3 97
    LUT4 107
INV 3
    INV 3

Resource Utilization Summary

Resource Usage Utilization
Logic 234(234 LUT, 0 ALU) / 1584 15%
Register 96 / 1704 6%
  --Register as Latch 0 / 1704 0%
  --Register as FF 96 / 1704 6%
BSRAM 0 / 4 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
2 clkdiv_2/clk400hz Base 20.000 50.0 0.000 10.000 clkdiv_2/clk400hz_s9/F
3 clkdiv_3/clk160hz Base 20.000 50.0 0.000 10.000 clkdiv_3/clk_out_s0/Q

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 134.223(MHz) 5 TOP
2 clkdiv_2/clk400hz 50.000(MHz) 348.056(MHz) 2 TOP
3 clkdiv_3/clk160hz 50.000(MHz) 306.479(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 7.974
Data Arrival Time 12.237
Data Required Time 20.212
From clkdiv_2/n62_s2
To clkdiv_2/count_0_s0
Launch Clk clkdiv_2/clk400hz[R]
Latch Clk clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clkdiv_2/clk400hz
10.000 0.000 tCL FF 22 clkdiv_2/clk400hz_s9/F
10.711 0.711 tNET FF 1 clkdiv_2/n62_s2/I1
11.526 0.814 tINS FF 1 clkdiv_2/n62_s2/F
12.237 0.711 tNET FF 1 clkdiv_2/count_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 77 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_2/count_0_s0/CLK
20.508 -0.030 tUnc clkdiv_2/count_0_s0
20.212 -0.296 tSu 1 clkdiv_2/count_0_s0
Path Statistics:
Clock Skew: 0.538
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay: cell: 0.814, 36.402%; route: 0.711, 31.799%; tC2Q: 0.711, 31.799%
Required Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%

Path 2

Path Summary:
Slack 8.024
Data Arrival Time 12.187
Data Required Time 20.212
From clkdiv_2/n61_s2
To clkdiv_2/count_1_s0
Launch Clk clkdiv_2/clk400hz[R]
Latch Clk clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clkdiv_2/clk400hz
10.000 0.000 tCL FF 22 clkdiv_2/clk400hz_s9/F
10.711 0.711 tNET FF 1 clkdiv_2/n61_s2/I0
11.476 0.765 tINS FF 1 clkdiv_2/n61_s2/F
12.187 0.711 tNET FF 1 clkdiv_2/count_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 77 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_2/count_1_s0/CLK
20.508 -0.030 tUnc clkdiv_2/count_1_s0
20.212 -0.296 tSu 1 clkdiv_2/count_1_s0
Path Statistics:
Clock Skew: 0.538
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay: cell: 0.765, 34.960%; route: 0.711, 32.520%; tC2Q: 0.711, 32.520%
Required Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%

Path 3

Path Summary:
Slack 8.024
Data Arrival Time 12.187
Data Required Time 20.212
From clkdiv_2/n60_s4
To clkdiv_2/count_2_s0
Launch Clk clkdiv_2/clk400hz[R]
Latch Clk clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clkdiv_2/clk400hz
10.000 0.000 tCL FF 22 clkdiv_2/clk400hz_s9/F
10.711 0.711 tNET FF 1 clkdiv_2/n60_s4/I0
11.476 0.765 tINS FF 1 clkdiv_2/n60_s4/F
12.187 0.711 tNET FF 1 clkdiv_2/count_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 77 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_2/count_2_s0/CLK
20.508 -0.030 tUnc clkdiv_2/count_2_s0
20.212 -0.296 tSu 1 clkdiv_2/count_2_s0
Path Statistics:
Clock Skew: 0.538
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay: cell: 0.765, 34.960%; route: 0.711, 32.520%; tC2Q: 0.711, 32.520%
Required Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%

Path 4

Path Summary:
Slack 8.024
Data Arrival Time 12.187
Data Required Time 20.212
From clkdiv_2/n58_s2
To clkdiv_2/count_4_s0
Launch Clk clkdiv_2/clk400hz[R]
Latch Clk clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clkdiv_2/clk400hz
10.000 0.000 tCL FF 22 clkdiv_2/clk400hz_s9/F
10.711 0.711 tNET FF 1 clkdiv_2/n58_s2/I0
11.476 0.765 tINS FF 1 clkdiv_2/n58_s2/F
12.187 0.711 tNET FF 1 clkdiv_2/count_4_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 77 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_2/count_4_s0/CLK
20.508 -0.030 tUnc clkdiv_2/count_4_s0
20.212 -0.296 tSu 1 clkdiv_2/count_4_s0
Path Statistics:
Clock Skew: 0.538
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay: cell: 0.765, 34.960%; route: 0.711, 32.520%; tC2Q: 0.711, 32.520%
Required Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%

Path 5

Path Summary:
Slack 8.024
Data Arrival Time 12.187
Data Required Time 20.212
From clkdiv_2/n55_s2
To clkdiv_2/count_7_s0
Launch Clk clkdiv_2/clk400hz[R]
Latch Clk clk[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clkdiv_2/clk400hz
10.000 0.000 tCL FF 22 clkdiv_2/clk400hz_s9/F
10.711 0.711 tNET FF 1 clkdiv_2/n55_s2/I0
11.476 0.765 tINS FF 1 clkdiv_2/n55_s2/F
12.187 0.711 tNET FF 1 clkdiv_2/count_7_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 77 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_2/count_7_s0/CLK
20.508 -0.030 tUnc clkdiv_2/count_7_s0
20.212 -0.296 tSu 1 clkdiv_2/count_7_s0
Path Statistics:
Clock Skew: 0.538
Setup Relationship: 10.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay: cell: 0.765, 34.960%; route: 0.711, 32.520%; tC2Q: 0.711, 32.520%
Required Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%