Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\src\clkdiv.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\src\dec16to4.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\src\drv7seg.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\src\matrix_key.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\src\mux7seg.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\src\test_matrix_key.sv
GowinSynthesis Constraints File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Mon Dec 16 16:48:44 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module test_matrix_key
Synthesis Process Running parser:
    CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 231.199MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 231.199MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 231.199MB
    Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 231.199MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 231.199MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 231.199MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 231.199MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.312s, Elapsed time = 0h 0m 0.425s, Peak memory usage = 231.199MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.031s, Peak memory usage = 231.199MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.011s, Peak memory usage = 231.199MB
Total Time and Memory Usage CPU time = 0h 0m 0.451s, Elapsed time = 0h 0m 0.544s, Peak memory usage = 231.199MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 23
I/O Buf 23
    IBUF 6
    OBUF 17
Register 61
    DFFE 6
    DFFPE 16
    DFFC 23
    DFFCE 16
LUT 105
    LUT2 16
    LUT3 32
    LUT4 57
INV 18
    INV 18

Resource Utilization Summary

Resource Usage Utilization
Logic 123(123 LUT, 0 ALU) / 1584 8%
Register 61 / 1704 4%
  --Register as Latch 0 / 1704 0%
  --Register as FF 61 / 1704 4%
BSRAM 0 / 4 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
2 clkdiv_1/clk50hz Base 20.000 50.0 0.000 10.000 clkdiv_1/clk_out_s0/Q

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 135.124(MHz) 5 TOP
2 clkdiv_1/clk50hz 50.000(MHz) 348.056(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 12.599
Data Arrival Time 7.642
Data Required Time 20.242
From clkdiv_1/count_0_s0
To clkdiv_1/count_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 21 clk_ibuf/O
0.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
0.878 0.340 tC2Q RF 5 clkdiv_1/count_0_s0/Q
1.589 0.711 tNET FF 1 clkdiv_1/n58_s3/I1
2.403 0.814 tINS FF 11 clkdiv_1/n58_s3/F
3.115 0.711 tNET FF 1 clkdiv_1/n62_s6/I1
3.929 0.814 tINS FF 1 clkdiv_1/n62_s6/F
4.640 0.711 tNET FF 1 clkdiv_1/n62_s4/I0
5.405 0.765 tINS FF 15 clkdiv_1/n62_s4/F
6.116 0.711 tNET FF 1 clkdiv_1/n62_s11/I1
6.931 0.814 tINS FF 1 clkdiv_1/n62_s11/F
7.642 0.711 tNET FF 1 clkdiv_1/count_0_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 21 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
20.242 -0.296 tSu 1 clkdiv_1/count_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 12.599
Data Arrival Time 7.642
Data Required Time 20.242
From clkdiv_1/count_0_s0
To clkdiv_1/count_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 21 clk_ibuf/O
0.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
0.878 0.340 tC2Q RF 5 clkdiv_1/count_0_s0/Q
1.589 0.711 tNET FF 1 clkdiv_1/n58_s3/I1
2.403 0.814 tINS FF 11 clkdiv_1/n58_s3/F
3.115 0.711 tNET FF 1 clkdiv_1/n62_s6/I1
3.929 0.814 tINS FF 1 clkdiv_1/n62_s6/F
4.640 0.711 tNET FF 1 clkdiv_1/n62_s4/I0
5.405 0.765 tINS FF 15 clkdiv_1/n62_s4/F
6.116 0.711 tNET FF 1 clkdiv_1/n61_s3/I1
6.931 0.814 tINS FF 1 clkdiv_1/n61_s3/F
7.642 0.711 tNET FF 1 clkdiv_1/count_1_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 21 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_1/count_1_s0/CLK
20.242 -0.296 tSu 1 clkdiv_1/count_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 12.599
Data Arrival Time 7.642
Data Required Time 20.242
From clkdiv_1/count_0_s0
To clkdiv_1/count_18_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 21 clk_ibuf/O
0.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
0.878 0.340 tC2Q RF 5 clkdiv_1/count_0_s0/Q
1.589 0.711 tNET FF 1 clkdiv_1/n58_s3/I1
2.403 0.814 tINS FF 11 clkdiv_1/n58_s3/F
3.115 0.711 tNET FF 1 clkdiv_1/n49_s3/I1
3.929 0.814 tINS FF 7 clkdiv_1/n49_s3/F
4.640 0.711 tNET FF 1 clkdiv_1/n44_s3/I1
5.455 0.814 tINS FF 1 clkdiv_1/n44_s3/F
6.166 0.711 tNET FF 1 clkdiv_1/n44_s4/I0
6.931 0.765 tINS FF 1 clkdiv_1/n44_s4/F
7.642 0.711 tNET FF 1 clkdiv_1/count_18_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 21 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_1/count_18_s0/CLK
20.242 -0.296 tSu 1 clkdiv_1/count_18_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 12.649
Data Arrival Time 7.593
Data Required Time 20.242
From clkdiv_1/count_0_s0
To clkdiv_1/clk_out_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 21 clk_ibuf/O
0.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
0.878 0.340 tC2Q RF 5 clkdiv_1/count_0_s0/Q
1.589 0.711 tNET FF 1 clkdiv_1/n58_s3/I1
2.403 0.814 tINS FF 11 clkdiv_1/n58_s3/F
3.115 0.711 tNET FF 1 clkdiv_1/n64_s83/I1
3.929 0.814 tINS FF 1 clkdiv_1/n64_s83/F
4.640 0.711 tNET FF 1 clkdiv_1/n64_s80/I0
5.405 0.765 tINS FF 1 clkdiv_1/n64_s80/F
6.116 0.711 tNET FF 1 clkdiv_1/n64_s88/I0
6.881 0.765 tINS FF 1 clkdiv_1/n64_s88/F
7.593 0.711 tNET FF 1 clkdiv_1/clk_out_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 21 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_1/clk_out_s0/CLK
20.242 -0.296 tSu 1 clkdiv_1/clk_out_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.158, 44.767%; route: 3.557, 50.419%; tC2Q: 0.340, 4.814%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 12.649
Data Arrival Time 7.593
Data Required Time 20.242
From clkdiv_1/count_0_s0
To clkdiv_1/count_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 21 clk_ibuf/O
0.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
0.878 0.340 tC2Q RF 5 clkdiv_1/count_0_s0/Q
1.589 0.711 tNET FF 1 clkdiv_1/n58_s3/I1
2.403 0.814 tINS FF 11 clkdiv_1/n58_s3/F
3.115 0.711 tNET FF 1 clkdiv_1/n62_s6/I1
3.929 0.814 tINS FF 1 clkdiv_1/n62_s6/F
4.640 0.711 tNET FF 1 clkdiv_1/n62_s4/I0
5.405 0.765 tINS FF 15 clkdiv_1/n62_s4/F
6.116 0.711 tNET FF 1 clkdiv_1/n60_s5/I0
6.881 0.765 tINS FF 1 clkdiv_1/n60_s5/F
7.593 0.711 tNET FF 1 clkdiv_1/count_2_s0/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 21 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_1/count_2_s0/CLK
20.242 -0.296 tSu 1 clkdiv_1/count_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 5
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.158, 44.767%; route: 3.557, 50.419%; tC2Q: 0.340, 4.814%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%