Timing Messages
| Report Title | Timing Analysis Report |
| Design File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\impl\gwsynthesis\uart.vg |
| Physical Constraints File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\src\uart.cst |
| Timing Constraint File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\src\uart.sdc |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW1N-UV1P5QN48XFC7/I6 |
| Device | GW1N-1P5 |
| Device Version | C |
| Created Time | Thu Dec 19 15:37:09 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 1.71V 85C C7/I6 |
| Hold Delay Model | Fast 3.6V 0C C7/I6 |
| Numbers of Paths Analyzed | 554 |
| Numbers of Endpoints Analyzed | 307 |
| Numbers of Falling Endpoints | 0 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 37.037 | 27.000 | 0.000 | 18.518 | clk | ||
| 2 | clk400hz | Generated | 2499997.500 | 0.000 | 0.000 | 1249998.750 | clk | clk | clk400hz |
| 3 | clk160hz | Generated | 6249993.500 | 0.000 | 0.000 | 3124996.750 | clk | clk | clk160hz |
| 4 | clkbaudhz | Generated | 8666.657 | 0.115 | 0.000 | 4333.329 | clk | clk | clkbaudhz |
| 5 | clkbaudx2hz | Generated | 4333.329 | 0.231 | 0.000 | 2166.664 | clk | clk | clkbaudx2hz |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 27.000(MHz) | 166.502(MHz) | 5 | TOP |
| 2 | clk400hz | 0.000(MHz) | 363.636(MHz) | 2 | TOP |
| 3 | clk160hz | 0.000(MHz) | 222.222(MHz) | 2 | TOP |
| 4 | clkbaudhz | 0.115(MHz) | 204.024(MHz) | 4 | TOP |
| 5 | clkbaudx2hz | 0.231(MHz) | 186.503(MHz) | 5 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| clk | Setup | 0.000 | 0 |
| clk | Hold | 0.000 | 0 |
| clk400hz | Setup | 0.000 | 0 |
| clk400hz | Hold | 0.000 | 0 |
| clk160hz | Setup | 0.000 | 0 |
| clk160hz | Hold | 0.000 | 0 |
| clkbaudhz | Setup | 0.000 | 0 |
| clkbaudhz | Hold | 0.000 | 0 |
| clkbaudx2hz | Setup | 0.000 | 0 |
| clkbaudx2hz | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 31.031 | clkdiv_4/count_11_s0/Q | clkdiv_4/count_16_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.710 |
| 2 | 31.031 | clkdiv_4/count_11_s0/Q | clkdiv_4/count_17_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.710 |
| 3 | 31.116 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_6_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.624 |
| 4 | 31.166 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_8_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.575 |
| 5 | 31.291 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_4_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.449 |
| 6 | 31.425 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_2_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.315 |
| 7 | 31.437 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_5_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.304 |
| 8 | 31.470 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_10_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.270 |
| 9 | 31.475 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_12_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.266 |
| 10 | 31.478 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_15_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.263 |
| 11 | 31.552 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_6_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.189 |
| 12 | 31.552 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_7_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.189 |
| 13 | 31.552 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_9_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.189 |
| 14 | 31.554 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_3_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.186 |
| 15 | 31.554 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_7_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.186 |
| 16 | 31.594 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_2_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.147 |
| 17 | 31.594 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_10_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.147 |
| 18 | 31.594 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_11_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.147 |
| 19 | 31.594 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_12_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.147 |
| 20 | 31.597 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_4_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.143 |
| 21 | 31.602 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_8_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.139 |
| 22 | 31.622 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_0_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.119 |
| 23 | 31.622 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_1_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.119 |
| 24 | 31.622 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_9_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 5.119 |
| 25 | 31.776 | clkdiv_4/count_5_s0/Q | clkdiv_4/count_11_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.965 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.524 | clkdiv_3/count_14_s0/Q | clkdiv_3/count_14_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.524 |
| 2 | 0.524 | clkdiv_3/count_16_s0/Q | clkdiv_3/count_16_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.524 |
| 3 | 0.524 | clkdiv_1/count_7_s0/Q | clkdiv_1/count_7_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.524 |
| 4 | 0.524 | rx_1/count_2_s0/Q | rx_1/count_2_s0/D | clkbaudx2hz:[R] | clkbaudx2hz:[R] | 0.000 | 0.000 | 0.524 |
| 5 | 0.524 | rx_1/count_4_s0/Q | rx_1/count_4_s0/D | clkbaudx2hz:[R] | clkbaudx2hz:[R] | 0.000 | 0.000 | 0.524 |
| 6 | 0.525 | clkdiv_4/count_17_s0/Q | clkdiv_4/count_17_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.525 |
| 7 | 0.525 | clkdiv_2/count_0_s0/Q | clkdiv_2/count_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.525 |
| 8 | 0.525 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_1_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.525 |
| 9 | 0.525 | clkdiv_1/count_4_s0/Q | clkdiv_1/count_4_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.525 |
| 10 | 0.525 | clkdiv_1/count_5_s0/Q | clkdiv_1/count_5_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.525 |
| 11 | 0.526 | clkdiv_4/count_0_s0/Q | clkdiv_4/count_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.526 |
| 12 | 0.526 | clkdiv_4/count_4_s0/Q | clkdiv_4/count_4_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.526 |
| 13 | 0.526 | clkdiv_3/count_0_s0/Q | clkdiv_3/count_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.526 |
| 14 | 0.526 | clkdiv_3/count_6_s0/Q | clkdiv_3/count_6_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.526 |
| 15 | 0.526 | clkdiv_2/count_6_s0/Q | clkdiv_2/count_6_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.526 |
| 16 | 0.526 | clkdiv_1/count_0_s0/Q | clkdiv_1/count_0_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.526 |
| 17 | 0.527 | rx_1/count_0_s0/Q | rx_1/count_0_s0/D | clkbaudx2hz:[R] | clkbaudx2hz:[R] | 0.000 | 0.000 | 0.527 |
| 18 | 0.527 | mux7seg_1/col_1_s0/Q | mux7seg_1/col_1_s0/D | clk160hz:[R] | clk160hz:[R] | 0.000 | 0.000 | 0.527 |
| 19 | 0.528 | rx_1/state_1_s3/Q | rx_1/state_1_s3/D | clkbaudx2hz:[R] | clkbaudx2hz:[R] | 0.000 | 0.000 | 0.528 |
| 20 | 0.662 | clkdiv_4/count_6_s0/Q | clkdiv_4/count_6_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.662 |
| 21 | 0.662 | clkdiv_3/count_11_s0/Q | clkdiv_3/count_11_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.662 |
| 22 | 0.662 | clkdiv_3/count_13_s0/Q | clkdiv_3/count_13_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.662 |
| 23 | 0.662 | clkdiv_4/count_11_s0/Q | clkdiv_4/count_11_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.662 |
| 24 | 0.662 | clkdiv_1/count_2_s0/Q | clkdiv_1/count_2_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.662 |
| 25 | 0.663 | clkdiv_4/count_2_s0/Q | clkdiv_4/count_2_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.663 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_1/count_7_s0 |
| 2 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_1/count_5_s0 |
| 3 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_1/count_1_s0 |
| 4 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_2/count_1_s0 |
| 5 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_3/count_3_s0 |
| 6 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_3/count_4_s0 |
| 7 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_2/count_2_s0 |
| 8 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_3/count_5_s0 |
| 9 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_3/count_6_s0 |
| 10 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_1/count_2_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 31.031 |
| Data Arrival Time | 7.978 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_11_s0 |
| To | clkdiv_4/count_16_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C10[2][A] | clkdiv_4/count_11_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R11C10[2][A] | clkdiv_4/count_11_s0/Q |
| 3.931 | 1.322 | tNET | FF | 1 | R11C10[1][B] | clkdiv_4/n49_s5/I2 |
| 4.745 | 0.814 | tINS | FF | 1 | R11C10[1][B] | clkdiv_4/n49_s5/F |
| 5.353 | 0.608 | tNET | FF | 1 | R12C10[0][A] | clkdiv_4/n49_s3/I3 |
| 5.962 | 0.609 | tINS | FF | 4 | R12C10[0][A] | clkdiv_4/n49_s3/F |
| 6.692 | 0.730 | tNET | FF | 1 | R11C8[0][B] | clkdiv_4/n46_s7/I1 |
| 7.156 | 0.464 | tINS | FF | 2 | R11C8[0][B] | clkdiv_4/n46_s7/F |
| 7.164 | 0.008 | tNET | FF | 1 | R11C8[3][A] | clkdiv_4/n46_s8/I2 |
| 7.978 | 0.814 | tINS | FF | 1 | R11C8[3][A] | clkdiv_4/n46_s8/F |
| 7.978 | 0.000 | tNET | FF | 1 | R11C8[3][A] | clkdiv_4/count_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C8[3][A] | clkdiv_4/count_16_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C8[3][A] | clkdiv_4/count_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.702, 47.319%; route: 2.668, 46.733%; tC2Q: 0.340, 5.948% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path2
Path Summary:
| Slack | 31.031 |
| Data Arrival Time | 7.978 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_11_s0 |
| To | clkdiv_4/count_17_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C10[2][A] | clkdiv_4/count_11_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R11C10[2][A] | clkdiv_4/count_11_s0/Q |
| 3.931 | 1.322 | tNET | FF | 1 | R11C10[1][B] | clkdiv_4/n49_s5/I2 |
| 4.745 | 0.814 | tINS | FF | 1 | R11C10[1][B] | clkdiv_4/n49_s5/F |
| 5.353 | 0.608 | tNET | FF | 1 | R12C10[0][A] | clkdiv_4/n49_s3/I3 |
| 5.962 | 0.609 | tINS | FF | 4 | R12C10[0][A] | clkdiv_4/n49_s3/F |
| 6.692 | 0.730 | tNET | FF | 1 | R11C8[0][B] | clkdiv_4/n46_s7/I1 |
| 7.156 | 0.464 | tINS | FF | 2 | R11C8[0][B] | clkdiv_4/n46_s7/F |
| 7.164 | 0.008 | tNET | FF | 1 | R11C8[1][A] | clkdiv_4/n45_s2/I1 |
| 7.978 | 0.814 | tINS | FF | 1 | R11C8[1][A] | clkdiv_4/n45_s2/F |
| 7.978 | 0.000 | tNET | FF | 1 | R11C8[1][A] | clkdiv_4/count_17_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C8[1][A] | clkdiv_4/count_17_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C8[1][A] | clkdiv_4/count_17_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.702, 47.319%; route: 2.668, 46.733%; tC2Q: 0.340, 5.948% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path3
Path Summary:
| Slack | 31.116 |
| Data Arrival Time | 7.893 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_6_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.451 | 0.765 | tINS | FF | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 7.079 | 0.628 | tNET | FF | 1 | R13C10[2][A] | clkdiv_4/n56_s2/I3 |
| 7.893 | 0.814 | tINS | FF | 1 | R13C10[2][A] | clkdiv_4/n56_s2/F |
| 7.893 | 0.000 | tNET | FF | 1 | R13C10[2][A] | clkdiv_4/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C10[2][A] | clkdiv_4/count_6_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C10[2][A] | clkdiv_4/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.857, 50.803%; route: 2.427, 43.159%; tC2Q: 0.340, 6.039% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path4
Path Summary:
| Slack | 31.166 |
| Data Arrival Time | 7.843 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_8_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.451 | 0.765 | tINS | FF | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 7.079 | 0.628 | tNET | FF | 1 | R13C10[1][B] | clkdiv_4/n54_s2/I3 |
| 7.843 | 0.765 | tINS | FF | 1 | R13C10[1][B] | clkdiv_4/n54_s2/F |
| 7.843 | 0.000 | tNET | FF | 1 | R13C10[1][B] | clkdiv_4/count_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C10[1][B] | clkdiv_4/count_8_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C10[1][B] | clkdiv_4/count_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.808, 50.365%; route: 2.427, 43.543%; tC2Q: 0.340, 6.092% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path5
Path Summary:
| Slack | 31.291 |
| Data Arrival Time | 7.718 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_4_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.451 | 0.765 | tINS | FF | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 7.109 | 0.658 | tNET | FF | 1 | R13C10[1][A] | clkdiv_4/n58_s2/I2 |
| 7.718 | 0.609 | tINS | FF | 1 | R13C10[1][A] | clkdiv_4/n58_s2/F |
| 7.718 | 0.000 | tNET | FF | 1 | R13C10[1][A] | clkdiv_4/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C10[1][A] | clkdiv_4/count_4_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C10[1][A] | clkdiv_4/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.652, 48.669%; route: 2.458, 45.099%; tC2Q: 0.340, 6.233% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path6
Path Summary:
| Slack | 31.425 |
| Data Arrival Time | 7.584 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_2_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.446 | 0.760 | tINS | FR | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 6.770 | 0.323 | tNET | RR | 1 | R12C9[2][A] | clkdiv_4/n60_s4/I3 |
| 7.584 | 0.814 | tINS | RF | 1 | R12C9[2][A] | clkdiv_4/n60_s4/F |
| 7.584 | 0.000 | tNET | FF | 1 | R12C9[2][A] | clkdiv_4/count_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C9[2][A] | clkdiv_4/count_2_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C9[2][A] | clkdiv_4/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.853, 53.672%; route: 2.123, 39.939%; tC2Q: 0.340, 6.389% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path7
Path Summary:
| Slack | 31.437 |
| Data Arrival Time | 7.573 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_5_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.451 | 0.765 | tINS | FF | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 7.109 | 0.658 | tNET | FF | 1 | R13C10[0][B] | clkdiv_4/n57_s2/I3 |
| 7.573 | 0.464 | tINS | FF | 1 | R13C10[0][B] | clkdiv_4/n57_s2/F |
| 7.573 | 0.000 | tNET | FF | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C10[0][B] | clkdiv_4/count_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.507, 47.263%; route: 2.458, 46.334%; tC2Q: 0.340, 6.403% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path8
Path Summary:
| Slack | 31.470 |
| Data Arrival Time | 7.539 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_10_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.451 | 0.765 | tINS | FF | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 7.075 | 0.624 | tNET | FF | 1 | R12C10[0][B] | clkdiv_4/n52_s2/I2 |
| 7.539 | 0.464 | tINS | FF | 1 | R12C10[0][B] | clkdiv_4/n52_s2/F |
| 7.539 | 0.000 | tNET | FF | 1 | R12C10[0][B] | clkdiv_4/count_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C10[0][B] | clkdiv_4/count_10_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C10[0][B] | clkdiv_4/count_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.507, 47.564%; route: 2.424, 45.992%; tC2Q: 0.340, 6.444% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path9
Path Summary:
| Slack | 31.475 |
| Data Arrival Time | 7.534 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_12_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.446 | 0.760 | tINS | FR | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 6.770 | 0.323 | tNET | RR | 1 | R11C8[1][B] | clkdiv_4/n50_s2/I2 |
| 7.534 | 0.765 | tINS | RF | 1 | R11C8[1][B] | clkdiv_4/n50_s2/F |
| 7.534 | 0.000 | tNET | FF | 1 | R11C8[1][B] | clkdiv_4/count_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C8[1][B] | clkdiv_4/count_12_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C8[1][B] | clkdiv_4/count_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.803, 53.235%; route: 2.123, 40.315%; tC2Q: 0.340, 6.450% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path10
Path Summary:
| Slack | 31.478 |
| Data Arrival Time | 7.532 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_15_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.446 | 0.760 | tINS | FR | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 6.767 | 0.320 | tNET | RR | 1 | R12C9[0][A] | clkdiv_4/n47_s2/I3 |
| 7.532 | 0.765 | tINS | RF | 1 | R12C9[0][A] | clkdiv_4/n47_s2/F |
| 7.532 | 0.000 | tNET | FF | 1 | R12C9[0][A] | clkdiv_4/count_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C9[0][A] | clkdiv_4/count_15_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C9[0][A] | clkdiv_4/count_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.803, 53.265%; route: 2.120, 40.282%; tC2Q: 0.340, 6.453% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path11
Path Summary:
| Slack | 31.552 |
| Data Arrival Time | 7.457 |
| Data Required Time | 39.009 |
| From | clkdiv_3/count_2_s0 |
| To | clkdiv_3/count_6_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R12C6[3][A] | clkdiv_3/count_2_s0/Q |
| 3.592 | 0.983 | tNET | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/I2 |
| 4.406 | 0.814 | tINS | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/F |
| 4.410 | 0.004 | tNET | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/I0 |
| 5.225 | 0.814 | tINS | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/F |
| 5.229 | 0.004 | tNET | FF | 1 | R11C7[3][A] | clkdiv_3/n62_s11/I1 |
| 5.993 | 0.765 | tINS | FF | 17 | R11C7[3][A] | clkdiv_3/n62_s11/F |
| 6.643 | 0.650 | tNET | FF | 1 | R13C7[1][A] | clkdiv_3/n56_s2/I3 |
| 7.457 | 0.814 | tINS | FF | 1 | R13C7[1][A] | clkdiv_3/n56_s2/F |
| 7.457 | 0.000 | tNET | FF | 1 | R13C7[1][A] | clkdiv_3/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C7[1][A] | clkdiv_3/count_6_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C7[1][A] | clkdiv_3/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 3.208, 61.824%; route: 1.641, 31.630%; tC2Q: 0.340, 6.546% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path12
Path Summary:
| Slack | 31.552 |
| Data Arrival Time | 7.457 |
| Data Required Time | 39.009 |
| From | clkdiv_3/count_2_s0 |
| To | clkdiv_3/count_7_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R12C6[3][A] | clkdiv_3/count_2_s0/Q |
| 3.592 | 0.983 | tNET | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/I2 |
| 4.406 | 0.814 | tINS | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/F |
| 4.410 | 0.004 | tNET | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/I0 |
| 5.225 | 0.814 | tINS | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/F |
| 5.229 | 0.004 | tNET | FF | 1 | R11C7[3][A] | clkdiv_3/n62_s11/I1 |
| 5.993 | 0.765 | tINS | FF | 17 | R11C7[3][A] | clkdiv_3/n62_s11/F |
| 6.643 | 0.650 | tNET | FF | 1 | R13C7[2][B] | clkdiv_3/n55_s2/I2 |
| 7.457 | 0.814 | tINS | FF | 1 | R13C7[2][B] | clkdiv_3/n55_s2/F |
| 7.457 | 0.000 | tNET | FF | 1 | R13C7[2][B] | clkdiv_3/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C7[2][B] | clkdiv_3/count_7_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C7[2][B] | clkdiv_3/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 3.208, 61.824%; route: 1.641, 31.630%; tC2Q: 0.340, 6.546% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path13
Path Summary:
| Slack | 31.552 |
| Data Arrival Time | 7.457 |
| Data Required Time | 39.009 |
| From | clkdiv_3/count_2_s0 |
| To | clkdiv_3/count_9_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R12C6[3][A] | clkdiv_3/count_2_s0/Q |
| 3.592 | 0.983 | tNET | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/I2 |
| 4.406 | 0.814 | tINS | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/F |
| 4.410 | 0.004 | tNET | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/I0 |
| 5.225 | 0.814 | tINS | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/F |
| 5.229 | 0.004 | tNET | FF | 1 | R11C7[3][A] | clkdiv_3/n62_s11/I1 |
| 5.993 | 0.765 | tINS | FF | 17 | R11C7[3][A] | clkdiv_3/n62_s11/F |
| 6.643 | 0.650 | tNET | FF | 1 | R13C7[1][B] | clkdiv_3/n53_s2/I2 |
| 7.457 | 0.814 | tINS | FF | 1 | R13C7[1][B] | clkdiv_3/n53_s2/F |
| 7.457 | 0.000 | tNET | FF | 1 | R13C7[1][B] | clkdiv_3/count_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C7[1][B] | clkdiv_3/count_9_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C7[1][B] | clkdiv_3/count_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 3.208, 61.824%; route: 1.641, 31.630%; tC2Q: 0.340, 6.546% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path14
Path Summary:
| Slack | 31.554 |
| Data Arrival Time | 7.455 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_3_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.451 | 0.765 | tINS | FF | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 6.846 | 0.395 | tNET | FF | 1 | R13C9[0][A] | clkdiv_4/n59_s2/I3 |
| 7.455 | 0.609 | tINS | FF | 1 | R13C9[0][A] | clkdiv_4/n59_s2/F |
| 7.455 | 0.000 | tNET | FF | 1 | R13C9[0][A] | clkdiv_4/count_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C9[0][A] | clkdiv_4/count_3_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C9[0][A] | clkdiv_4/count_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.652, 51.137%; route: 2.194, 42.314%; tC2Q: 0.340, 6.549% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path15
Path Summary:
| Slack | 31.554 |
| Data Arrival Time | 7.455 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_7_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.451 | 0.765 | tINS | FF | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 6.846 | 0.395 | tNET | FF | 1 | R13C9[0][B] | clkdiv_4/n55_s2/I2 |
| 7.455 | 0.609 | tINS | FF | 1 | R13C9[0][B] | clkdiv_4/n55_s2/F |
| 7.455 | 0.000 | tNET | FF | 1 | R13C9[0][B] | clkdiv_4/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C9[0][B] | clkdiv_4/count_7_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C9[0][B] | clkdiv_4/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.652, 51.137%; route: 2.194, 42.314%; tC2Q: 0.340, 6.549% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path16
Path Summary:
| Slack | 31.594 |
| Data Arrival Time | 7.416 |
| Data Required Time | 39.009 |
| From | clkdiv_3/count_2_s0 |
| To | clkdiv_3/count_2_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R12C6[3][A] | clkdiv_3/count_2_s0/Q |
| 3.592 | 0.983 | tNET | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/I2 |
| 4.406 | 0.814 | tINS | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/F |
| 4.410 | 0.004 | tNET | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/I0 |
| 5.225 | 0.814 | tINS | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/F |
| 5.229 | 0.004 | tNET | FF | 1 | R11C7[3][A] | clkdiv_3/n62_s11/I1 |
| 5.993 | 0.765 | tINS | FF | 17 | R11C7[3][A] | clkdiv_3/n62_s11/F |
| 6.651 | 0.658 | tNET | FF | 1 | R12C6[3][A] | clkdiv_3/n60_s4/I3 |
| 7.416 | 0.765 | tINS | FF | 1 | R12C6[3][A] | clkdiv_3/n60_s4/F |
| 7.416 | 0.000 | tNET | FF | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C6[3][A] | clkdiv_3/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 3.158, 61.361%; route: 1.649, 32.040%; tC2Q: 0.340, 6.599% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path17
Path Summary:
| Slack | 31.594 |
| Data Arrival Time | 7.416 |
| Data Required Time | 39.009 |
| From | clkdiv_3/count_2_s0 |
| To | clkdiv_3/count_10_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R12C6[3][A] | clkdiv_3/count_2_s0/Q |
| 3.592 | 0.983 | tNET | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/I2 |
| 4.406 | 0.814 | tINS | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/F |
| 4.410 | 0.004 | tNET | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/I0 |
| 5.225 | 0.814 | tINS | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/F |
| 5.229 | 0.004 | tNET | FF | 1 | R11C7[3][A] | clkdiv_3/n62_s11/I1 |
| 5.993 | 0.765 | tINS | FF | 17 | R11C7[3][A] | clkdiv_3/n62_s11/F |
| 6.651 | 0.658 | tNET | FF | 1 | R12C6[0][B] | clkdiv_3/n52_s2/I2 |
| 7.416 | 0.765 | tINS | FF | 1 | R12C6[0][B] | clkdiv_3/n52_s2/F |
| 7.416 | 0.000 | tNET | FF | 1 | R12C6[0][B] | clkdiv_3/count_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C6[0][B] | clkdiv_3/count_10_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C6[0][B] | clkdiv_3/count_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 3.158, 61.361%; route: 1.649, 32.040%; tC2Q: 0.340, 6.599% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path18
Path Summary:
| Slack | 31.594 |
| Data Arrival Time | 7.416 |
| Data Required Time | 39.009 |
| From | clkdiv_3/count_2_s0 |
| To | clkdiv_3/count_11_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R12C6[3][A] | clkdiv_3/count_2_s0/Q |
| 3.592 | 0.983 | tNET | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/I2 |
| 4.406 | 0.814 | tINS | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/F |
| 4.410 | 0.004 | tNET | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/I0 |
| 5.225 | 0.814 | tINS | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/F |
| 5.229 | 0.004 | tNET | FF | 1 | R11C7[3][A] | clkdiv_3/n62_s11/I1 |
| 5.993 | 0.765 | tINS | FF | 17 | R11C7[3][A] | clkdiv_3/n62_s11/F |
| 6.651 | 0.658 | tNET | FF | 1 | R12C6[2][A] | clkdiv_3/n51_s2/I3 |
| 7.416 | 0.765 | tINS | FF | 1 | R12C6[2][A] | clkdiv_3/n51_s2/F |
| 7.416 | 0.000 | tNET | FF | 1 | R12C6[2][A] | clkdiv_3/count_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C6[2][A] | clkdiv_3/count_11_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C6[2][A] | clkdiv_3/count_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 3.158, 61.361%; route: 1.649, 32.040%; tC2Q: 0.340, 6.599% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path19
Path Summary:
| Slack | 31.594 |
| Data Arrival Time | 7.416 |
| Data Required Time | 39.009 |
| From | clkdiv_3/count_2_s0 |
| To | clkdiv_3/count_12_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R12C6[3][A] | clkdiv_3/count_2_s0/Q |
| 3.592 | 0.983 | tNET | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/I2 |
| 4.406 | 0.814 | tINS | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/F |
| 4.410 | 0.004 | tNET | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/I0 |
| 5.225 | 0.814 | tINS | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/F |
| 5.229 | 0.004 | tNET | FF | 1 | R11C7[3][A] | clkdiv_3/n62_s11/I1 |
| 5.993 | 0.765 | tINS | FF | 17 | R11C7[3][A] | clkdiv_3/n62_s11/F |
| 6.651 | 0.658 | tNET | FF | 1 | R12C6[1][A] | clkdiv_3/n50_s2/I3 |
| 7.416 | 0.765 | tINS | FF | 1 | R12C6[1][A] | clkdiv_3/n50_s2/F |
| 7.416 | 0.000 | tNET | FF | 1 | R12C6[1][A] | clkdiv_3/count_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C6[1][A] | clkdiv_3/count_12_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C6[1][A] | clkdiv_3/count_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 3.158, 61.361%; route: 1.649, 32.040%; tC2Q: 0.340, 6.599% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path20
Path Summary:
| Slack | 31.597 |
| Data Arrival Time | 7.412 |
| Data Required Time | 39.009 |
| From | clkdiv_3/count_2_s0 |
| To | clkdiv_3/count_4_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R12C6[3][A] | clkdiv_3/count_2_s0/Q |
| 3.592 | 0.983 | tNET | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/I2 |
| 4.406 | 0.814 | tINS | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/F |
| 4.410 | 0.004 | tNET | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/I0 |
| 5.225 | 0.814 | tINS | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/F |
| 5.229 | 0.004 | tNET | FF | 1 | R11C7[3][A] | clkdiv_3/n62_s11/I1 |
| 5.993 | 0.765 | tINS | FF | 17 | R11C7[3][A] | clkdiv_3/n62_s11/F |
| 6.647 | 0.654 | tNET | FF | 1 | R13C6[0][B] | clkdiv_3/n58_s2/I2 |
| 7.412 | 0.765 | tINS | FF | 1 | R13C6[0][B] | clkdiv_3/n58_s2/F |
| 7.412 | 0.000 | tNET | FF | 1 | R13C6[0][B] | clkdiv_3/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C6[0][B] | clkdiv_3/count_4_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C6[0][B] | clkdiv_3/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 3.158, 61.402%; route: 1.646, 31.995%; tC2Q: 0.340, 6.603% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path21
Path Summary:
| Slack | 31.602 |
| Data Arrival Time | 7.408 |
| Data Required Time | 39.009 |
| From | clkdiv_3/count_2_s0 |
| To | clkdiv_3/count_8_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R12C6[3][A] | clkdiv_3/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R12C6[3][A] | clkdiv_3/count_2_s0/Q |
| 3.592 | 0.983 | tNET | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/I2 |
| 4.406 | 0.814 | tINS | FF | 1 | R11C7[1][B] | clkdiv_3/n62_s7/F |
| 4.410 | 0.004 | tNET | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/I0 |
| 5.225 | 0.814 | tINS | FF | 1 | R11C7[2][B] | clkdiv_3/n62_s5/F |
| 5.229 | 0.004 | tNET | FF | 1 | R11C7[3][A] | clkdiv_3/n62_s11/I1 |
| 5.993 | 0.765 | tINS | FF | 17 | R11C7[3][A] | clkdiv_3/n62_s11/F |
| 6.643 | 0.650 | tNET | FF | 1 | R13C7[0][B] | clkdiv_3/n54_s2/I3 |
| 7.408 | 0.765 | tINS | FF | 1 | R13C7[0][B] | clkdiv_3/n54_s2/F |
| 7.408 | 0.000 | tNET | FF | 1 | R13C7[0][B] | clkdiv_3/count_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C7[0][B] | clkdiv_3/count_8_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R13C7[0][B] | clkdiv_3/count_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 3.158, 61.455%; route: 1.641, 31.936%; tC2Q: 0.340, 6.609% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path22
Path Summary:
| Slack | 31.622 |
| Data Arrival Time | 7.388 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_0_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.446 | 0.760 | tINS | FR | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 6.779 | 0.332 | tNET | RR | 1 | R11C10[0][A] | clkdiv_4/n62_s2/I1 |
| 7.388 | 0.609 | tINS | RF | 1 | R11C10[0][A] | clkdiv_4/n62_s2/F |
| 7.388 | 0.000 | tNET | FF | 1 | R11C10[0][A] | clkdiv_4/count_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C10[0][A] | clkdiv_4/count_0_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C10[0][A] | clkdiv_4/count_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.648, 51.722%; route: 2.132, 41.644%; tC2Q: 0.340, 6.635% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path23
Path Summary:
| Slack | 31.622 |
| Data Arrival Time | 7.388 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_1_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.446 | 0.760 | tINS | FR | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 6.779 | 0.332 | tNET | RR | 1 | R11C10[0][B] | clkdiv_4/n61_s2/I2 |
| 7.388 | 0.609 | tINS | RF | 1 | R11C10[0][B] | clkdiv_4/n61_s2/F |
| 7.388 | 0.000 | tNET | FF | 1 | R11C10[0][B] | clkdiv_4/count_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C10[0][B] | clkdiv_4/count_1_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C10[0][B] | clkdiv_4/count_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.648, 51.722%; route: 2.132, 41.644%; tC2Q: 0.340, 6.635% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path24
Path Summary:
| Slack | 31.622 |
| Data Arrival Time | 7.388 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_9_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.446 | 0.760 | tINS | FR | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 6.779 | 0.332 | tNET | RR | 1 | R11C10[2][B] | clkdiv_4/n53_s2/I3 |
| 7.388 | 0.609 | tINS | RF | 1 | R11C10[2][B] | clkdiv_4/n53_s2/F |
| 7.388 | 0.000 | tNET | FF | 1 | R11C10[2][B] | clkdiv_4/count_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C10[2][B] | clkdiv_4/count_9_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C10[2][B] | clkdiv_4/count_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.648, 51.722%; route: 2.132, 41.644%; tC2Q: 0.340, 6.635% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path25
Path Summary:
| Slack | 31.776 |
| Data Arrival Time | 7.234 |
| Data Required Time | 39.009 |
| From | clkdiv_4/count_5_s0 |
| To | clkdiv_4/count_11_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R13C10[0][B] | clkdiv_4/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 6 | R13C10[0][B] | clkdiv_4/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/I0 |
| 4.030 | 0.814 | tINS | FF | 1 | R12C9[3][B] | clkdiv_4/n62_s9/F |
| 4.626 | 0.596 | tNET | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/I2 |
| 5.090 | 0.464 | tINS | FF | 1 | R12C10[3][A] | clkdiv_4/n62_s4/F |
| 5.686 | 0.596 | tNET | FF | 1 | R11C9[2][A] | clkdiv_4/n62_s13/I0 |
| 6.446 | 0.760 | tINS | FR | 17 | R11C9[2][A] | clkdiv_4/n62_s13/F |
| 6.770 | 0.323 | tNET | RR | 1 | R11C10[2][A] | clkdiv_4/n51_s2/I3 |
| 7.234 | 0.464 | tINS | RF | 1 | R11C10[2][A] | clkdiv_4/n51_s2/F |
| 7.234 | 0.000 | tNET | FF | 1 | R11C10[2][A] | clkdiv_4/count_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C10[2][A] | clkdiv_4/count_11_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C10[2][A] | clkdiv_4/count_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.502, 50.401%; route: 2.123, 42.758%; tC2Q: 0.340, 6.841% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_14_s0 |
| To | clkdiv_3/count_14_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C6[0][A] | clkdiv_3/count_14_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R11C6[0][A] | clkdiv_3/count_14_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R11C6[0][A] | clkdiv_3/n48_s2/I2 |
| 2.053 | 0.276 | tINS | RF | 1 | R11C6[0][A] | clkdiv_3/n48_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R11C6[0][A] | clkdiv_3/count_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C6[0][A] | clkdiv_3/count_14_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C6[0][A] | clkdiv_3/count_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path2
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_16_s0 |
| To | clkdiv_3/count_16_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C6[1][A] | clkdiv_3/count_16_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R11C6[1][A] | clkdiv_3/count_16_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R11C6[1][A] | clkdiv_3/n46_s2/I2 |
| 2.053 | 0.276 | tINS | RF | 1 | R11C6[1][A] | clkdiv_3/n46_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R11C6[1][A] | clkdiv_3/count_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C6[1][A] | clkdiv_3/count_16_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C6[1][A] | clkdiv_3/count_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path3
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_7_s0 |
| To | clkdiv_1/count_7_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[1][A] | clkdiv_1/count_7_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 4 | R8C10[1][A] | clkdiv_1/count_7_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R8C10[1][A] | clkdiv_1/n55_s2/I2 |
| 2.053 | 0.276 | tINS | RF | 1 | R8C10[1][A] | clkdiv_1/n55_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R8C10[1][A] | clkdiv_1/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[1][A] | clkdiv_1/count_7_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C10[1][A] | clkdiv_1/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path4
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 1.031 |
| Data Required Time | 0.506 |
| From | rx_1/count_2_s0 |
| To | rx_1/count_2_s0 |
| Launch Clk | clkbaudx2hz:[R] |
| Latch Clk | clkbaudx2hz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clkbaudx2hz | ||||
| 0.000 | 0.000 | tCL | RR | 33 | R8C11[0][A] | clkdiv_2/clk_out_s0/Q |
| 0.506 | 0.506 | tNET | RR | 1 | R11C11[1][A] | rx_1/count_2_s0/CLK |
| 0.753 | 0.247 | tC2Q | RR | 3 | R11C11[1][A] | rx_1/count_2_s0/Q |
| 0.755 | 0.002 | tNET | RR | 1 | R11C11[1][A] | rx_1/n143_s7/I3 |
| 1.031 | 0.276 | tINS | RF | 1 | R11C11[1][A] | rx_1/n143_s7/F |
| 1.031 | 0.000 | tNET | FF | 1 | R11C11[1][A] | rx_1/count_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clkbaudx2hz | ||||
| 0.000 | 0.000 | tCL | RR | 33 | R8C11[0][A] | clkdiv_2/clk_out_s0/Q |
| 0.506 | 0.506 | tNET | RR | 1 | R11C11[1][A] | rx_1/count_2_s0/CLK |
| 0.506 | 0.000 | tHld | 1 | R11C11[1][A] | rx_1/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.506, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.506, 100.000% |
Path5
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 1.031 |
| Data Required Time | 0.506 |
| From | rx_1/count_4_s0 |
| To | rx_1/count_4_s0 |
| Launch Clk | clkbaudx2hz:[R] |
| Latch Clk | clkbaudx2hz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clkbaudx2hz | ||||
| 0.000 | 0.000 | tCL | RR | 33 | R8C11[0][A] | clkdiv_2/clk_out_s0/Q |
| 0.506 | 0.506 | tNET | RR | 1 | R11C11[0][A] | rx_1/count_4_s0/CLK |
| 0.753 | 0.247 | tC2Q | RR | 2 | R11C11[0][A] | rx_1/count_4_s0/Q |
| 0.755 | 0.002 | tNET | RR | 1 | R11C11[0][A] | rx_1/n141_s8/I3 |
| 1.031 | 0.276 | tINS | RF | 1 | R11C11[0][A] | rx_1/n141_s8/F |
| 1.031 | 0.000 | tNET | FF | 1 | R11C11[0][A] | rx_1/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clkbaudx2hz | ||||
| 0.000 | 0.000 | tCL | RR | 33 | R8C11[0][A] | clkdiv_2/clk_out_s0/Q |
| 0.506 | 0.506 | tNET | RR | 1 | R11C11[0][A] | rx_1/count_4_s0/CLK |
| 0.506 | 0.000 | tHld | 1 | R11C11[0][A] | rx_1/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.506, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.506, 100.000% |
Path6
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_4/count_17_s0 |
| To | clkdiv_4/count_17_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C8[1][A] | clkdiv_4/count_17_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 4 | R11C8[1][A] | clkdiv_4/count_17_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R11C8[1][A] | clkdiv_4/n45_s2/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R11C8[1][A] | clkdiv_4/n45_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R11C8[1][A] | clkdiv_4/count_17_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C8[1][A] | clkdiv_4/count_17_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C8[1][A] | clkdiv_4/count_17_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path7
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_0_s0 |
| To | clkdiv_2/count_0_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C12[0][A] | clkdiv_2/count_0_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R8C12[0][A] | clkdiv_2/count_0_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R8C12[0][A] | clkdiv_2/n62_s7/I0 |
| 2.054 | 0.276 | tINS | RF | 1 | R8C12[0][A] | clkdiv_2/n62_s7/F |
| 2.054 | 0.000 | tNET | FF | 1 | R8C12[0][A] | clkdiv_2/count_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C12[0][A] | clkdiv_2/count_0_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C12[0][A] | clkdiv_2/count_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path8
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_1_s0 |
| To | clkdiv_1/count_1_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R6C9[0][A] | clkdiv_1/count_1_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R6C9[0][A] | clkdiv_1/count_1_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R6C9[0][A] | clkdiv_1/n61_s2/I1 |
| 2.054 | 0.276 | tINS | RF | 1 | R6C9[0][A] | clkdiv_1/n61_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R6C9[0][A] | clkdiv_1/count_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R6C9[0][A] | clkdiv_1/count_1_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R6C9[0][A] | clkdiv_1/count_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path9
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_4_s0 |
| To | clkdiv_1/count_4_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[0][A] | clkdiv_1/count_4_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R8C10[0][A] | clkdiv_1/count_4_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R8C10[0][A] | clkdiv_1/n58_s2/I0 |
| 2.054 | 0.276 | tINS | RF | 1 | R8C10[0][A] | clkdiv_1/n58_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R8C10[0][A] | clkdiv_1/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[0][A] | clkdiv_1/count_4_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C10[0][A] | clkdiv_1/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path10
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_5_s0 |
| To | clkdiv_1/count_5_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C9[1][A] | clkdiv_1/count_5_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R8C9[1][A] | clkdiv_1/count_5_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R8C9[1][A] | clkdiv_1/n57_s2/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R8C9[1][A] | clkdiv_1/n57_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R8C9[1][A] | clkdiv_1/count_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C9[1][A] | clkdiv_1/count_5_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C9[1][A] | clkdiv_1/count_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path11
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_4/count_0_s0 |
| To | clkdiv_4/count_0_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C10[0][A] | clkdiv_4/count_0_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R11C10[0][A] | clkdiv_4/count_0_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R11C10[0][A] | clkdiv_4/n62_s2/I0 |
| 2.055 | 0.276 | tINS | RF | 1 | R11C10[0][A] | clkdiv_4/n62_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R11C10[0][A] | clkdiv_4/count_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C10[0][A] | clkdiv_4/count_0_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C10[0][A] | clkdiv_4/count_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path12
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_4/count_4_s0 |
| To | clkdiv_4/count_4_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R13C10[1][A] | clkdiv_4/count_4_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 7 | R13C10[1][A] | clkdiv_4/count_4_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R13C10[1][A] | clkdiv_4/n58_s2/I0 |
| 2.055 | 0.276 | tINS | RF | 1 | R13C10[1][A] | clkdiv_4/n58_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R13C10[1][A] | clkdiv_4/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R13C10[1][A] | clkdiv_4/count_4_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R13C10[1][A] | clkdiv_4/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path13
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_0_s0 |
| To | clkdiv_3/count_0_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C7[1][A] | clkdiv_3/count_0_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 7 | R11C7[1][A] | clkdiv_3/count_0_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R11C7[1][A] | clkdiv_3/n62_s3/I0 |
| 2.055 | 0.276 | tINS | RF | 1 | R11C7[1][A] | clkdiv_3/n62_s3/F |
| 2.055 | 0.000 | tNET | FF | 1 | R11C7[1][A] | clkdiv_3/count_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C7[1][A] | clkdiv_3/count_0_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C7[1][A] | clkdiv_3/count_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path14
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_6_s0 |
| To | clkdiv_3/count_6_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R13C7[1][A] | clkdiv_3/count_6_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 4 | R13C7[1][A] | clkdiv_3/count_6_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R13C7[1][A] | clkdiv_3/n56_s2/I2 |
| 2.055 | 0.276 | tINS | RF | 1 | R13C7[1][A] | clkdiv_3/n56_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R13C7[1][A] | clkdiv_3/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R13C7[1][A] | clkdiv_3/count_6_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R13C7[1][A] | clkdiv_3/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path15
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_6_s0 |
| To | clkdiv_2/count_6_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C11[1][A] | clkdiv_2/count_6_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 7 | R8C11[1][A] | clkdiv_2/count_6_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R8C11[1][A] | clkdiv_2/n56_s2/I2 |
| 2.055 | 0.276 | tINS | RF | 1 | R8C11[1][A] | clkdiv_2/n56_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R8C11[1][A] | clkdiv_2/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C11[1][A] | clkdiv_2/count_6_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C11[1][A] | clkdiv_2/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path16
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_0_s0 |
| To | clkdiv_1/count_0_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R6C9[1][A] | clkdiv_1/count_0_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R6C9[1][A] | clkdiv_1/count_0_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R6C9[1][A] | clkdiv_1/n62_s8/I1 |
| 2.055 | 0.276 | tINS | RF | 1 | R6C9[1][A] | clkdiv_1/n62_s8/F |
| 2.055 | 0.000 | tNET | FF | 1 | R6C9[1][A] | clkdiv_1/count_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R6C9[1][A] | clkdiv_1/count_0_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R6C9[1][A] | clkdiv_1/count_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path17
Path Summary:
| Slack | 0.527 |
| Data Arrival Time | 1.033 |
| Data Required Time | 0.506 |
| From | rx_1/count_0_s0 |
| To | rx_1/count_0_s0 |
| Launch Clk | clkbaudx2hz:[R] |
| Latch Clk | clkbaudx2hz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clkbaudx2hz | ||||
| 0.000 | 0.000 | tCL | RR | 33 | R8C11[0][A] | clkdiv_2/clk_out_s0/Q |
| 0.506 | 0.506 | tNET | RR | 1 | R12C11[0][A] | rx_1/count_0_s0/CLK |
| 0.753 | 0.247 | tC2Q | RR | 9 | R12C11[0][A] | rx_1/count_0_s0/Q |
| 0.758 | 0.004 | tNET | RR | 1 | R12C11[0][A] | rx_1/n145_s9/I0 |
| 1.033 | 0.276 | tINS | RF | 1 | R12C11[0][A] | rx_1/n145_s9/F |
| 1.033 | 0.000 | tNET | FF | 1 | R12C11[0][A] | rx_1/count_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clkbaudx2hz | ||||
| 0.000 | 0.000 | tCL | RR | 33 | R8C11[0][A] | clkdiv_2/clk_out_s0/Q |
| 0.506 | 0.506 | tNET | RR | 1 | R12C11[0][A] | rx_1/count_0_s0/CLK |
| 0.506 | 0.000 | tHld | 1 | R12C11[0][A] | rx_1/count_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.506, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.506, 100.000% |
Path18
Path Summary:
| Slack | 0.527 |
| Data Arrival Time | 1.243 |
| Data Required Time | 0.716 |
| From | mux7seg_1/col_1_s0 |
| To | mux7seg_1/col_1_s0 |
| Launch Clk | clk160hz:[R] |
| Latch Clk | clk160hz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk160hz | ||||
| 0.000 | 0.000 | tCL | RR | 13 | R11C9[0][A] | clkdiv_4/clk_out_s0/Q |
| 0.716 | 0.716 | tNET | RR | 1 | R6C11[0][A] | mux7seg_1/col_1_s0/CLK |
| 0.963 | 0.247 | tC2Q | RR | 12 | R6C11[0][A] | mux7seg_1/col_1_s0/Q |
| 0.967 | 0.004 | tNET | RR | 1 | R6C11[0][A] | mux7seg_1/n11_s2/I0 |
| 1.243 | 0.276 | tINS | RF | 1 | R6C11[0][A] | mux7seg_1/n11_s2/F |
| 1.243 | 0.000 | tNET | FF | 1 | R6C11[0][A] | mux7seg_1/col_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk160hz | ||||
| 0.000 | 0.000 | tCL | RR | 13 | R11C9[0][A] | clkdiv_4/clk_out_s0/Q |
| 0.716 | 0.716 | tNET | RR | 1 | R6C11[0][A] | mux7seg_1/col_1_s0/CLK |
| 0.716 | 0.000 | tHld | 1 | R6C11[0][A] | mux7seg_1/col_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.716, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.716, 100.000% |
Path19
Path Summary:
| Slack | 0.528 |
| Data Arrival Time | 1.034 |
| Data Required Time | 0.506 |
| From | rx_1/state_1_s3 |
| To | rx_1/state_1_s3 |
| Launch Clk | clkbaudx2hz:[R] |
| Latch Clk | clkbaudx2hz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clkbaudx2hz | ||||
| 0.000 | 0.000 | tCL | RR | 33 | R8C11[0][A] | clkdiv_2/clk_out_s0/Q |
| 0.506 | 0.506 | tNET | RR | 1 | R13C14[0][A] | rx_1/state_1_s3/CLK |
| 0.753 | 0.247 | tC2Q | RR | 11 | R13C14[0][A] | rx_1/state_1_s3/Q |
| 0.758 | 0.005 | tNET | RR | 1 | R13C14[0][A] | rx_1/n130_s12/I1 |
| 1.034 | 0.276 | tINS | RF | 1 | R13C14[0][A] | rx_1/n130_s12/F |
| 1.034 | 0.000 | tNET | FF | 1 | R13C14[0][A] | rx_1/state_1_s3/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clkbaudx2hz | ||||
| 0.000 | 0.000 | tCL | RR | 33 | R8C11[0][A] | clkdiv_2/clk_out_s0/Q |
| 0.506 | 0.506 | tNET | RR | 1 | R13C14[0][A] | rx_1/state_1_s3/CLK |
| 0.506 | 0.000 | tHld | 1 | R13C14[0][A] | rx_1/state_1_s3 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.506, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.217%; route: 0.005, 0.994%; tC2Q: 0.247, 46.789% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.506, 100.000% |
Path20
Path Summary:
| Slack | 0.662 |
| Data Arrival Time | 2.190 |
| Data Required Time | 1.529 |
| From | clkdiv_4/count_6_s0 |
| To | clkdiv_4/count_6_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R13C10[2][A] | clkdiv_4/count_6_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R13C10[2][A] | clkdiv_4/count_6_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R13C10[2][A] | clkdiv_4/n56_s2/I2 |
| 2.190 | 0.412 | tINS | RR | 1 | R13C10[2][A] | clkdiv_4/n56_s2/F |
| 2.190 | 0.000 | tNET | RR | 1 | R13C10[2][A] | clkdiv_4/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R13C10[2][A] | clkdiv_4/count_6_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R13C10[2][A] | clkdiv_4/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path21
Path Summary:
| Slack | 0.662 |
| Data Arrival Time | 2.190 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_11_s0 |
| To | clkdiv_3/count_11_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R12C6[2][A] | clkdiv_3/count_11_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 4 | R12C6[2][A] | clkdiv_3/count_11_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R12C6[2][A] | clkdiv_3/n51_s2/I2 |
| 2.190 | 0.412 | tINS | RR | 1 | R12C6[2][A] | clkdiv_3/n51_s2/F |
| 2.190 | 0.000 | tNET | RR | 1 | R12C6[2][A] | clkdiv_3/count_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R12C6[2][A] | clkdiv_3/count_11_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R12C6[2][A] | clkdiv_3/count_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path22
Path Summary:
| Slack | 0.662 |
| Data Arrival Time | 2.190 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_13_s0 |
| To | clkdiv_3/count_13_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C6[2][A] | clkdiv_3/count_13_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 4 | R11C6[2][A] | clkdiv_3/count_13_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R11C6[2][A] | clkdiv_3/n49_s2/I0 |
| 2.190 | 0.412 | tINS | RR | 1 | R11C6[2][A] | clkdiv_3/n49_s2/F |
| 2.190 | 0.000 | tNET | RR | 1 | R11C6[2][A] | clkdiv_3/count_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C6[2][A] | clkdiv_3/count_13_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C6[2][A] | clkdiv_3/count_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path23
Path Summary:
| Slack | 0.662 |
| Data Arrival Time | 2.191 |
| Data Required Time | 1.529 |
| From | clkdiv_4/count_11_s0 |
| To | clkdiv_4/count_11_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C10[2][A] | clkdiv_4/count_11_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R11C10[2][A] | clkdiv_4/count_11_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R11C10[2][A] | clkdiv_4/n51_s2/I2 |
| 2.191 | 0.412 | tINS | RR | 1 | R11C10[2][A] | clkdiv_4/n51_s2/F |
| 2.191 | 0.000 | tNET | RR | 1 | R11C10[2][A] | clkdiv_4/count_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C10[2][A] | clkdiv_4/count_11_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C10[2][A] | clkdiv_4/count_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.412, 62.189%; route: 0.003, 0.528%; tC2Q: 0.247, 37.283% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path24
Path Summary:
| Slack | 0.662 |
| Data Arrival Time | 2.191 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_2_s0 |
| To | clkdiv_1/count_2_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[2][A] | clkdiv_1/count_2_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R8C10[2][A] | clkdiv_1/count_2_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R8C10[2][A] | clkdiv_1/n60_s4/I0 |
| 2.191 | 0.412 | tINS | RR | 1 | R8C10[2][A] | clkdiv_1/n60_s4/F |
| 2.191 | 0.000 | tNET | RR | 1 | R8C10[2][A] | clkdiv_1/count_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[2][A] | clkdiv_1/count_2_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C10[2][A] | clkdiv_1/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.412, 62.189%; route: 0.003, 0.528%; tC2Q: 0.247, 37.283% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path25
Path Summary:
| Slack | 0.663 |
| Data Arrival Time | 2.192 |
| Data Required Time | 1.529 |
| From | clkdiv_4/count_2_s0 |
| To | clkdiv_4/count_2_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R12C9[2][A] | clkdiv_4/count_2_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R12C9[2][A] | clkdiv_4/count_2_s0/Q |
| 1.780 | 0.004 | tNET | RR | 1 | R12C9[2][A] | clkdiv_4/n60_s4/I0 |
| 2.192 | 0.412 | tINS | RR | 1 | R12C9[2][A] | clkdiv_4/n60_s4/F |
| 2.192 | 0.000 | tNET | RR | 1 | R12C9[2][A] | clkdiv_4/count_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 54 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R12C9[2][A] | clkdiv_4/count_2_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R12C9[2][A] | clkdiv_4/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.412, 62.107%; route: 0.004, 0.659%; tC2Q: 0.247, 37.234% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_1/count_7_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_7_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_7_s0/CLK |
MPW2
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_1/count_5_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_5_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_5_s0/CLK |
MPW3
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_1/count_1_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_1_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_1_s0/CLK |
MPW4
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_2/count_1_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_2/count_1_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_2/count_1_s0/CLK |
MPW5
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_3/count_3_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_3/count_3_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_3/count_3_s0/CLK |
MPW6
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_3/count_4_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_3/count_4_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_3/count_4_s0/CLK |
MPW7
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_2/count_2_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_2/count_2_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_2/count_2_s0/CLK |
MPW8
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_3/count_5_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_3/count_5_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_3/count_5_s0/CLK |
MPW9
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_3/count_6_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_3/count_6_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_3/count_6_s0/CLK |
MPW10
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_1/count_2_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_2_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_2_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 54 | clk_d | 31.031 | 0.195 |
| 35 | state[0] | 4328.187 | 1.805 |
| 33 | clkbaudx2hz | 4327.966 | 0.798 |
| 21 | clkbaudhz | 8661.756 | 0.785 |
| 20 | col[0] | 6249989.000 | 1.332 |
| 17 | n62_19 | 31.116 | 0.658 |
| 17 | n62_17 | 31.552 | 0.658 |
| 15 | state[0] | 8663.260 | 0.326 |
| 13 | clk160hz | 6249988.500 | 1.279 |
| 12 | col[1] | 6249988.500 | 1.456 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R6C13 | 80.56% |
| R11C10 | 79.17% |
| R11C14 | 73.61% |
| R7C13 | 72.22% |
| R11C12 | 72.22% |
| R8C10 | 68.06% |
| R11C6 | 68.06% |
| R13C7 | 66.67% |
| R13C13 | 66.67% |
| R13C14 | 65.28% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name clk -period 37.037 -waveform {0 18.518} [get_ports {clk}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk400hz -source [get_ports {clk}] -master_clock clk -divide_by 67500 [get_nets {clk400hz}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk160hz -source [get_ports {clk}] -master_clock clk -divide_by 168750 [get_nets {clk160hz}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name clkbaudhz -source [get_ports {clk}] -master_clock clk -divide_by 234 [get_nets {clkbaudhz}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name clkbaudx2hz -source [get_ports {clk}] -master_clock clk -divide_by 117 [get_nets {clkbaudx2hz}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk400hz}] -to [get_clocks {clkbaudhz}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clkbaudx2hz}] -to [get_clocks {clk160hz}] |