Timing Messages
| Report Title | Timing Analysis Report |
| Design File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\pwm_servo\impl\gwsynthesis\pwm_servo.vg |
| Physical Constraints File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\pwm_servo\src\pwm_servo.cst |
| Timing Constraint File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\pwm_servo\src\pwm_servo.sdc |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW1N-UV1P5QN48XFC7/I6 |
| Device | GW1N-1P5 |
| Device Version | C |
| Created Time | Thu Dec 19 16:37:38 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 1.71V 85C C7/I6 |
| Hold Delay Model | Fast 3.6V 0C C7/I6 |
| Numbers of Paths Analyzed | 137 |
| Numbers of Endpoints Analyzed | 80 |
| Numbers of Falling Endpoints | 0 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 37.037 | 27.000 | 0.000 | 18.518 | clk | ||
| 2 | clk100khz | Generated | 9999.989 | 0.100 | 0.000 | 4999.995 | clk | clk | clk100khz |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 27.000(MHz) | 221.851(MHz) | 4 | TOP |
| 2 | clk100khz | 0.100(MHz) | 150.965(MHz) | 6 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| clk | Setup | 0.000 | 0 |
| clk | Hold | 0.000 | 0 |
| clk100khz | Setup | 0.000 | 0 |
| clk100khz | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 32.529 | clkdiv_1/count_3_s0/Q | clkdiv_1/clk_out_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 4.211 |
| 2 | 32.782 | clkdiv_1/count_2_s0/Q | clkdiv_1/count_6_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 3.959 |
| 3 | 32.960 | clkdiv_1/count_7_s0/Q | clkdiv_1/count_1_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 3.781 |
| 4 | 32.960 | clkdiv_1/count_7_s0/Q | clkdiv_1/count_2_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 3.781 |
| 5 | 32.960 | clkdiv_1/count_7_s0/Q | clkdiv_1/count_4_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 3.781 |
| 6 | 32.960 | clkdiv_1/count_7_s0/Q | clkdiv_1/count_5_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 3.781 |
| 7 | 33.037 | clkdiv_1/count_2_s0/Q | clkdiv_1/count_8_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 3.704 |
| 8 | 33.495 | clkdiv_1/count_5_s0/Q | clkdiv_1/count_7_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 3.246 |
| 9 | 33.625 | clkdiv_1/count_3_s0/Q | clkdiv_1/count_3_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 3.116 |
| 10 | 33.741 | clkdiv_1/count_7_s0/Q | clkdiv_1/count_0_s0/D | clk:[R] | clk:[R] | 37.037 | 0.000 | 3.000 |
| 11 | 9993.365 | pwm_1/count_0_s0/Q | pwm_1/line_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 6.327 |
| 12 | 9995.657 | pwm_1/count_1_s0/Q | pwm_1/count_15_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 4.036 |
| 13 | 9995.765 | pwm_1/count_1_s0/Q | pwm_1/count_11_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 3.928 |
| 14 | 9995.955 | pwm_1/count_1_s0/Q | pwm_1/count_9_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 3.737 |
| 15 | 9996.005 | pwm_1/count_1_s0/Q | pwm_1/count_13_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 3.688 |
| 16 | 9996.005 | pwm_1/count_1_s0/Q | pwm_1/count_14_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 3.688 |
| 17 | 9996.115 | pwm_1/count_1_s0/Q | pwm_1/count_12_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 3.577 |
| 18 | 9996.304 | pwm_1/count_1_s0/Q | pwm_1/count_10_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 3.389 |
| 19 | 9996.314 | pwm_1/count_1_s0/Q | pwm_1/tc_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 3.378 |
| 20 | 9996.659 | pwm_1/count_1_s0/Q | pwm_1/count_7_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 3.034 |
| 21 | 9996.659 | pwm_1/count_1_s0/Q | pwm_1/count_8_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 3.034 |
| 22 | 9996.782 | pwm_1/count_1_s0/Q | pwm_1/count_4_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 2.911 |
| 23 | 9997.436 | pwm_1/count_1_s0/Q | pwm_1/count_5_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 2.257 |
| 24 | 9997.436 | pwm_1/count_1_s0/Q | pwm_1/count_6_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 2.257 |
| 25 | 9997.604 | pwm_1/count_1_s0/Q | pwm_1/count_3_s0/D | clk100khz:[R] | clk100khz:[R] | 9999.989 | 0.000 | 2.089 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.524 | pwm_1/count_15_s0/Q | pwm_1/count_15_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.524 |
| 2 | 0.525 | clkdiv_1/count_1_s0/Q | clkdiv_1/count_1_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.525 |
| 3 | 0.525 | pwm_1/count_3_s0/Q | pwm_1/count_3_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.525 |
| 4 | 0.525 | pwm_1/count_7_s0/Q | pwm_1/count_7_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.525 |
| 5 | 0.525 | pwm_1/count_11_s0/Q | pwm_1/count_11_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.525 |
| 6 | 0.526 | pwm_1/count_0_s0/Q | pwm_1/count_0_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.526 |
| 7 | 0.526 | pwm_1/count_4_s0/Q | pwm_1/count_4_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.526 |
| 8 | 0.526 | pwm_1/count_9_s0/Q | pwm_1/count_9_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.526 |
| 9 | 0.528 | clkdiv_1/count_8_s0/Q | clkdiv_1/count_8_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.528 |
| 10 | 0.662 | pwm_1/count_5_s0/Q | pwm_1/count_5_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.662 |
| 11 | 0.663 | clkdiv_1/count_4_s0/Q | clkdiv_1/count_4_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.663 |
| 12 | 0.701 | pwm_1/count_9_s0/Q | pwm_1/count_10_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.701 |
| 13 | 0.701 | clkdiv_1/count_4_s0/Q | clkdiv_1/count_5_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.701 |
| 14 | 0.706 | pwm_1/count_0_s0/Q | pwm_1/count_1_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.706 |
| 15 | 0.708 | clkdiv_1/count_0_s0/Q | clkdiv_1/count_2_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.708 |
| 16 | 0.726 | clkdiv_1/count_8_s0/Q | clkdiv_1/count_3_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.726 |
| 17 | 0.726 | clkdiv_1/count_8_s0/Q | clkdiv_1/count_7_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.726 |
| 18 | 0.785 | pwm_1/count_14_s0/Q | pwm_1/count_14_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.785 |
| 19 | 0.786 | pwm_1/count_12_s0/Q | pwm_1/count_12_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.786 |
| 20 | 0.787 | pwm_1/count_2_s0/Q | pwm_1/count_2_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.787 |
| 21 | 0.787 | pwm_1/count_6_s0/Q | pwm_1/count_6_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.787 |
| 22 | 0.788 | pwm_1/count_8_s0/Q | pwm_1/count_8_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.788 |
| 23 | 0.861 | pwm_1/tc_s0/Q | pwm_1/count_13_s0/D | clk100khz:[R] | clk100khz:[R] | 0.000 | 0.000 | 0.861 |
| 24 | 0.950 | clkdiv_1/count_8_s0/Q | clkdiv_1/clk_out_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.950 |
| 25 | 0.968 | clkdiv_1/count_8_s0/Q | clkdiv_1/count_6_s0/D | clk:[R] | clk:[R] | 0.000 | 0.000 | 0.968 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | compare_7_s1 |
| 2 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | compare_2_s1 |
| 3 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_1/count_7_s0 |
| 4 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_1/clk_out_s0 |
| 5 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_1/count_0_s0 |
| 6 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_1/count_8_s0 |
| 7 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_1/count_1_s0 |
| 8 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | clkdiv_1/count_2_s0 |
| 9 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | compare_4_s1 |
| 10 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk | compare_6_s1 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 32.529 |
| Data Arrival Time | 6.480 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_3_s0 |
| To | clkdiv_1/clk_out_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C8[1][A] | clkdiv_1/count_3_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R11C8[1][A] | clkdiv_1/count_3_s0/Q |
| 3.925 | 1.316 | tNET | FF | 1 | R11C8[3][B] | clkdiv_1/n64_s81/I0 |
| 4.739 | 0.814 | tINS | FF | 1 | R11C8[3][B] | clkdiv_1/n64_s81/F |
| 4.743 | 0.004 | tNET | FF | 1 | R11C8[2][A] | clkdiv_1/n64_s78/I2 |
| 5.508 | 0.765 | tINS | FF | 1 | R11C8[2][A] | clkdiv_1/n64_s78/F |
| 5.871 | 0.363 | tNET | FF | 1 | R11C7[0][A] | clkdiv_1/n64_s86/I1 |
| 6.480 | 0.609 | tINS | FF | 1 | R11C7[0][A] | clkdiv_1/n64_s86/F |
| 6.480 | 0.000 | tNET | FF | 1 | R11C7[0][A] | clkdiv_1/clk_out_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C7[0][A] | clkdiv_1/clk_out_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C7[0][A] | clkdiv_1/clk_out_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.188, 51.962%; route: 1.683, 39.973%; tC2Q: 0.340, 8.065% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path2
Path Summary:
| Slack | 32.782 |
| Data Arrival Time | 6.228 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_2_s0 |
| To | clkdiv_1/count_6_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C9[1][B] | clkdiv_1/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R11C9[1][B] | clkdiv_1/count_2_s0/Q |
| 3.222 | 0.614 | tNET | FF | 1 | R11C8[2][B] | clkdiv_1/n58_s4/I2 |
| 3.987 | 0.765 | tINS | FF | 5 | R11C8[2][B] | clkdiv_1/n58_s4/F |
| 4.595 | 0.608 | tNET | FF | 1 | R9C9[0][B] | clkdiv_1/n56_s5/I0 |
| 5.409 | 0.814 | tINS | FF | 1 | R9C9[0][B] | clkdiv_1/n56_s5/F |
| 5.413 | 0.004 | tNET | FF | 1 | R9C9[0][A] | clkdiv_1/n56_s7/I3 |
| 6.228 | 0.814 | tINS | FF | 1 | R9C9[0][A] | clkdiv_1/n56_s7/F |
| 6.228 | 0.000 | tNET | FF | 1 | R9C9[0][A] | clkdiv_1/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R9C9[0][A] | clkdiv_1/count_6_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R9C9[0][A] | clkdiv_1/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.393, 60.456%; route: 1.226, 30.966%; tC2Q: 0.340, 8.579% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path3
Path Summary:
| Slack | 32.960 |
| Data Arrival Time | 6.049 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_7_s0 |
| To | clkdiv_1/count_1_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C8[0][A] | clkdiv_1/count_7_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R11C8[0][A] | clkdiv_1/count_7_s0/Q |
| 3.229 | 0.621 | tNET | FF | 1 | R9C8[2][B] | clkdiv_1/n62_s4/I3 |
| 4.043 | 0.814 | tINS | FF | 6 | R9C8[2][B] | clkdiv_1/n62_s4/F |
| 4.659 | 0.616 | tNET | FF | 1 | R11C9[3][B] | clkdiv_1/n62_s3/I0 |
| 5.268 | 0.609 | tINS | FF | 4 | R11C9[3][B] | clkdiv_1/n62_s3/F |
| 5.285 | 0.016 | tNET | FF | 1 | R11C9[1][A] | clkdiv_1/n61_s5/I0 |
| 6.049 | 0.765 | tINS | FF | 1 | R11C9[1][A] | clkdiv_1/n61_s5/F |
| 6.049 | 0.000 | tNET | FF | 1 | R11C9[1][A] | clkdiv_1/count_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C9[1][A] | clkdiv_1/count_1_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C9[1][A] | clkdiv_1/count_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.188, 57.880%; route: 1.253, 33.136%; tC2Q: 0.340, 8.984% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path4
Path Summary:
| Slack | 32.960 |
| Data Arrival Time | 6.049 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_7_s0 |
| To | clkdiv_1/count_2_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C8[0][A] | clkdiv_1/count_7_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R11C8[0][A] | clkdiv_1/count_7_s0/Q |
| 3.229 | 0.621 | tNET | FF | 1 | R9C8[2][B] | clkdiv_1/n62_s4/I3 |
| 4.043 | 0.814 | tINS | FF | 6 | R9C8[2][B] | clkdiv_1/n62_s4/F |
| 4.659 | 0.616 | tNET | FF | 1 | R11C9[3][B] | clkdiv_1/n62_s3/I0 |
| 5.268 | 0.609 | tINS | FF | 4 | R11C9[3][B] | clkdiv_1/n62_s3/F |
| 5.285 | 0.016 | tNET | FF | 1 | R11C9[1][B] | clkdiv_1/n60_s5/I0 |
| 6.049 | 0.765 | tINS | FF | 1 | R11C9[1][B] | clkdiv_1/n60_s5/F |
| 6.049 | 0.000 | tNET | FF | 1 | R11C9[1][B] | clkdiv_1/count_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C9[1][B] | clkdiv_1/count_2_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C9[1][B] | clkdiv_1/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.188, 57.880%; route: 1.253, 33.136%; tC2Q: 0.340, 8.984% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path5
Path Summary:
| Slack | 32.960 |
| Data Arrival Time | 6.049 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_7_s0 |
| To | clkdiv_1/count_4_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C8[0][A] | clkdiv_1/count_7_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R11C8[0][A] | clkdiv_1/count_7_s0/Q |
| 3.229 | 0.621 | tNET | FF | 1 | R9C8[2][B] | clkdiv_1/n62_s4/I3 |
| 4.043 | 0.814 | tINS | FF | 6 | R9C8[2][B] | clkdiv_1/n62_s4/F |
| 4.659 | 0.616 | tNET | FF | 1 | R11C9[3][B] | clkdiv_1/n62_s3/I0 |
| 5.268 | 0.609 | tINS | FF | 4 | R11C9[3][B] | clkdiv_1/n62_s3/F |
| 5.285 | 0.016 | tNET | FF | 1 | R11C9[2][A] | clkdiv_1/n58_s6/I0 |
| 6.049 | 0.765 | tINS | FF | 1 | R11C9[2][A] | clkdiv_1/n58_s6/F |
| 6.049 | 0.000 | tNET | FF | 1 | R11C9[2][A] | clkdiv_1/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C9[2][A] | clkdiv_1/count_4_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C9[2][A] | clkdiv_1/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.188, 57.880%; route: 1.253, 33.136%; tC2Q: 0.340, 8.984% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path6
Path Summary:
| Slack | 32.960 |
| Data Arrival Time | 6.049 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_7_s0 |
| To | clkdiv_1/count_5_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C8[0][A] | clkdiv_1/count_7_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R11C8[0][A] | clkdiv_1/count_7_s0/Q |
| 3.229 | 0.621 | tNET | FF | 1 | R9C8[2][B] | clkdiv_1/n62_s4/I3 |
| 4.043 | 0.814 | tINS | FF | 6 | R9C8[2][B] | clkdiv_1/n62_s4/F |
| 4.659 | 0.616 | tNET | FF | 1 | R11C9[3][B] | clkdiv_1/n62_s3/I0 |
| 5.268 | 0.609 | tINS | FF | 4 | R11C9[3][B] | clkdiv_1/n62_s3/F |
| 5.285 | 0.016 | tNET | FF | 1 | R11C9[2][B] | clkdiv_1/n57_s5/I0 |
| 6.049 | 0.765 | tINS | FF | 1 | R11C9[2][B] | clkdiv_1/n57_s5/F |
| 6.049 | 0.000 | tNET | FF | 1 | R11C9[2][B] | clkdiv_1/count_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C9[2][B] | clkdiv_1/count_5_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C9[2][B] | clkdiv_1/count_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.188, 57.880%; route: 1.253, 33.136%; tC2Q: 0.340, 8.984% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path7
Path Summary:
| Slack | 33.037 |
| Data Arrival Time | 5.973 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_2_s0 |
| To | clkdiv_1/count_8_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C9[1][B] | clkdiv_1/count_2_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R11C9[1][B] | clkdiv_1/count_2_s0/Q |
| 3.222 | 0.614 | tNET | FF | 1 | R11C8[2][B] | clkdiv_1/n58_s4/I2 |
| 3.987 | 0.765 | tINS | FF | 5 | R11C8[2][B] | clkdiv_1/n58_s4/F |
| 4.595 | 0.608 | tNET | FF | 1 | R9C8[2][A] | clkdiv_1/n54_s3/I0 |
| 5.360 | 0.765 | tINS | FF | 1 | R9C8[2][A] | clkdiv_1/n54_s3/F |
| 5.364 | 0.004 | tNET | FF | 1 | R9C8[0][A] | clkdiv_1/n54_s6/I3 |
| 5.973 | 0.609 | tINS | FF | 1 | R9C8[0][A] | clkdiv_1/n54_s6/F |
| 5.973 | 0.000 | tNET | FF | 1 | R9C8[0][A] | clkdiv_1/count_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/count_8_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R9C8[0][A] | clkdiv_1/count_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.139, 57.735%; route: 1.226, 33.096%; tC2Q: 0.340, 9.169% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path8
Path Summary:
| Slack | 33.495 |
| Data Arrival Time | 5.514 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_5_s0 |
| To | clkdiv_1/count_7_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C9[2][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 5 | R11C9[2][B] | clkdiv_1/count_5_s0/Q |
| 3.216 | 0.607 | tNET | FF | 1 | R9C8[1][B] | clkdiv_1/n56_s4/I1 |
| 3.825 | 0.609 | tINS | FF | 2 | R9C8[1][B] | clkdiv_1/n56_s4/F |
| 4.437 | 0.612 | tNET | FF | 1 | R11C8[3][A] | clkdiv_1/n55_s3/I2 |
| 4.901 | 0.464 | tINS | FF | 1 | R11C8[3][A] | clkdiv_1/n55_s3/F |
| 4.905 | 0.004 | tNET | FF | 1 | R11C8[0][A] | clkdiv_1/n55_s5/I3 |
| 5.514 | 0.609 | tINS | FF | 1 | R11C8[0][A] | clkdiv_1/n55_s5/F |
| 5.514 | 0.000 | tNET | FF | 1 | R11C8[0][A] | clkdiv_1/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C8[0][A] | clkdiv_1/count_7_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C8[0][A] | clkdiv_1/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 1.682, 51.827%; route: 1.224, 37.709%; tC2Q: 0.340, 10.464% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path9
Path Summary:
| Slack | 33.625 |
| Data Arrival Time | 5.385 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_3_s0 |
| To | clkdiv_1/count_3_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C8[1][A] | clkdiv_1/count_3_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R11C8[1][A] | clkdiv_1/count_3_s0/Q |
| 3.936 | 1.328 | tNET | FF | 1 | R11C8[1][B] | clkdiv_1/n62_s5/I3 |
| 4.400 | 0.464 | tINS | FF | 6 | R11C8[1][B] | clkdiv_1/n62_s5/F |
| 4.775 | 0.375 | tNET | FF | 1 | R11C8[1][A] | clkdiv_1/n59_s5/I1 |
| 5.385 | 0.609 | tINS | FF | 1 | R11C8[1][A] | clkdiv_1/n59_s5/F |
| 5.385 | 0.000 | tNET | FF | 1 | R11C8[1][A] | clkdiv_1/count_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C8[1][A] | clkdiv_1/count_3_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C8[1][A] | clkdiv_1/count_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 1.073, 34.436%; route: 1.703, 54.664%; tC2Q: 0.340, 10.900% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path10
Path Summary:
| Slack | 33.741 |
| Data Arrival Time | 5.268 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_7_s0 |
| To | clkdiv_1/count_0_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R11C8[0][A] | clkdiv_1/count_7_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R11C8[0][A] | clkdiv_1/count_7_s0/Q |
| 3.229 | 0.621 | tNET | FF | 1 | R9C8[2][B] | clkdiv_1/n62_s4/I3 |
| 4.043 | 0.814 | tINS | FF | 6 | R9C8[2][B] | clkdiv_1/n62_s4/F |
| 4.659 | 0.616 | tNET | FF | 1 | R11C9[3][A] | clkdiv_1/n62_s7/I1 |
| 5.268 | 0.609 | tINS | FF | 1 | R11C9[3][A] | clkdiv_1/n62_s7/F |
| 5.268 | 0.000 | tNET | FF | 1 | R11C9[3][A] | clkdiv_1/count_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C9[3][A] | clkdiv_1/count_0_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C9[3][A] | clkdiv_1/count_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 1.423, 47.456%; route: 1.236, 41.222%; tC2Q: 0.340, 11.322% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path11
Path Summary:
| Slack | 9993.365 |
| Data Arrival Time | 7.361 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_0_s0 |
| To | pwm_1/line_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C9[0][A] | pwm_1/count_0_s0/CLK |
| 1.374 | 0.340 | tC2Q | RF | 6 | R11C9[0][A] | pwm_1/count_0_s0/Q |
| 2.340 | 0.967 | tNET | FF | 2 | R9C12[0][B] | pwm_1/n40_s42/I0 |
| 3.050 | 0.710 | tINS | FF | 1 | R9C12[0][B] | pwm_1/n40_s42/COUT |
| 3.050 | 0.000 | tNET | FF | 2 | R9C12[1][A] | pwm_1/n40_s43/CIN |
| 3.092 | 0.042 | tINS | FF | 1 | R9C12[1][A] | pwm_1/n40_s43/COUT |
| 3.092 | 0.000 | tNET | FF | 2 | R9C12[1][B] | pwm_1/n40_s44/CIN |
| 3.135 | 0.042 | tINS | FF | 1 | R9C12[1][B] | pwm_1/n40_s44/COUT |
| 3.135 | 0.000 | tNET | FF | 2 | R9C12[2][A] | pwm_1/n40_s45/CIN |
| 3.177 | 0.042 | tINS | FF | 1 | R9C12[2][A] | pwm_1/n40_s45/COUT |
| 3.598 | 0.421 | tNET | FF | 1 | R9C12[3][A] | pwm_1/n61_s5/I3 |
| 4.363 | 0.765 | tINS | FF | 1 | R9C12[3][A] | pwm_1/n61_s5/F |
| 4.367 | 0.004 | tNET | FF | 1 | R9C12[3][B] | pwm_1/n61_s2/I2 |
| 4.961 | 0.594 | tINS | FR | 1 | R9C12[3][B] | pwm_1/n61_s2/F |
| 5.272 | 0.310 | tNET | RR | 1 | R9C11[3][B] | pwm_1/n61_s7/I0 |
| 6.036 | 0.765 | tINS | RF | 1 | R9C11[3][B] | pwm_1/n61_s7/F |
| 7.361 | 1.325 | tNET | FF | 1 | IOR1[A] | pwm_1/line_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | IOR1[A] | pwm_1/line_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | IOR1[A] | pwm_1/line_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 6 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 2.960, 46.786%; route: 3.027, 47.846%; tC2Q: 0.340, 5.368% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path12
Path Summary:
| Slack | 9995.657 |
| Data Arrival Time | 5.069 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_15_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 3.481 | 0.979 | tNET | FF | 1 | R9C10[0][A] | pwm_1/n26_s3/I1 |
| 3.944 | 0.463 | tINS | FR | 3 | R9C10[0][A] | pwm_1/n26_s3/F |
| 4.256 | 0.312 | tNET | RR | 1 | R9C11[0][A] | pwm_1/n24_s2/I0 |
| 5.070 | 0.814 | tINS | RF | 1 | R9C11[0][A] | pwm_1/n24_s2/F |
| 5.070 | 0.000 | tNET | FF | 1 | R9C11[0][A] | pwm_1/count_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R9C11[0][A] | pwm_1/count_15_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R9C11[0][A] | pwm_1/count_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 2.092, 51.834%; route: 1.604, 39.751%; tC2Q: 0.340, 8.416% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path13
Path Summary:
| Slack | 9995.765 |
| Data Arrival Time | 4.962 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_11_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 2.526 | 0.024 | tNET | FF | 1 | R11C11[2][B] | pwm_1/n32_s5/I0 |
| 3.291 | 0.765 | tINS | FF | 4 | R11C11[2][B] | pwm_1/n32_s5/F |
| 4.147 | 0.857 | tNET | FF | 1 | R11C12[1][A] | pwm_1/n28_s2/I0 |
| 4.962 | 0.814 | tINS | FF | 1 | R11C12[1][A] | pwm_1/n28_s2/F |
| 4.962 | 0.000 | tNET | FF | 1 | R11C12[1][A] | pwm_1/count_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R11C12[1][A] | pwm_1/count_11_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R11C12[1][A] | pwm_1/count_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 2.393, 60.939%; route: 1.195, 30.414%; tC2Q: 0.340, 8.647% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path14
Path Summary:
| Slack | 9995.955 |
| Data Arrival Time | 4.771 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_9_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 2.885 | 0.383 | tNET | FF | 1 | R11C12[3][B] | pwm_1/n30_s5/I0 |
| 3.645 | 0.760 | tINS | FR | 2 | R11C12[3][B] | pwm_1/n30_s5/F |
| 3.957 | 0.312 | tNET | RR | 1 | R11C11[0][A] | pwm_1/n30_s2/I2 |
| 4.772 | 0.814 | tINS | RF | 1 | R11C11[0][A] | pwm_1/n30_s2/F |
| 4.772 | 0.000 | tNET | FF | 1 | R11C11[0][A] | pwm_1/count_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R11C11[0][A] | pwm_1/count_9_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R11C11[0][A] | pwm_1/count_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 2.389, 63.920%; route: 1.009, 26.993%; tC2Q: 0.340, 9.087% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path15
Path Summary:
| Slack | 9996.005 |
| Data Arrival Time | 4.722 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_13_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 3.481 | 0.979 | tNET | FF | 1 | R9C10[0][A] | pwm_1/n26_s3/I1 |
| 3.944 | 0.463 | tINS | FR | 3 | R9C10[0][A] | pwm_1/n26_s3/F |
| 4.258 | 0.315 | tNET | RR | 1 | R9C11[3][A] | pwm_1/n26_s2/I2 |
| 4.722 | 0.464 | tINS | RF | 1 | R9C11[3][A] | pwm_1/n26_s2/F |
| 4.722 | 0.000 | tNET | FF | 1 | R9C11[3][A] | pwm_1/count_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R9C11[3][A] | pwm_1/count_13_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R9C11[3][A] | pwm_1/count_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 1.741, 47.215%; route: 1.607, 43.576%; tC2Q: 0.340, 9.209% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path16
Path Summary:
| Slack | 9996.005 |
| Data Arrival Time | 4.722 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_14_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 3.481 | 0.979 | tNET | FF | 1 | R9C10[0][A] | pwm_1/n26_s3/I1 |
| 3.944 | 0.463 | tINS | FR | 3 | R9C10[0][A] | pwm_1/n26_s3/F |
| 4.258 | 0.315 | tNET | RR | 1 | R9C11[0][B] | pwm_1/n25_s2/I1 |
| 4.722 | 0.464 | tINS | RF | 1 | R9C11[0][B] | pwm_1/n25_s2/F |
| 4.722 | 0.000 | tNET | FF | 1 | R9C11[0][B] | pwm_1/count_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R9C11[0][B] | pwm_1/count_14_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R9C11[0][B] | pwm_1/count_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 1.741, 47.215%; route: 1.607, 43.576%; tC2Q: 0.340, 9.209% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path17
Path Summary:
| Slack | 9996.115 |
| Data Arrival Time | 4.611 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_12_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 2.526 | 0.024 | tNET | FF | 1 | R11C11[2][B] | pwm_1/n32_s5/I0 |
| 3.291 | 0.765 | tINS | FF | 4 | R11C11[2][B] | pwm_1/n32_s5/F |
| 4.147 | 0.857 | tNET | FF | 1 | R11C12[0][B] | pwm_1/n27_s2/I0 |
| 4.611 | 0.464 | tINS | FF | 1 | R11C12[0][B] | pwm_1/n27_s2/F |
| 4.611 | 0.000 | tNET | FF | 1 | R11C12[0][B] | pwm_1/count_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R11C12[0][B] | pwm_1/count_12_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R11C12[0][B] | pwm_1/count_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 2.043, 57.112%; route: 1.195, 33.394%; tC2Q: 0.340, 9.494% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path18
Path Summary:
| Slack | 9996.304 |
| Data Arrival Time | 4.423 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_10_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 2.885 | 0.383 | tNET | FF | 1 | R11C12[3][B] | pwm_1/n30_s5/I0 |
| 3.650 | 0.765 | tINS | FF | 2 | R11C12[3][B] | pwm_1/n30_s5/F |
| 3.658 | 0.008 | tNET | FF | 1 | R11C12[1][B] | pwm_1/n29_s2/I1 |
| 4.423 | 0.765 | tINS | FF | 1 | R11C12[1][B] | pwm_1/n29_s2/F |
| 4.423 | 0.000 | tNET | FF | 1 | R11C12[1][B] | pwm_1/count_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R11C12[1][B] | pwm_1/count_10_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R11C12[1][B] | pwm_1/count_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 2.344, 69.167%; route: 0.705, 20.810%; tC2Q: 0.340, 10.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path19
Path Summary:
| Slack | 9996.314 |
| Data Arrival Time | 4.412 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/tc_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 3.481 | 0.979 | tNET | FF | 1 | R9C10[1][A] | pwm_1/n43_s49/I1 |
| 3.944 | 0.464 | tINS | FF | 1 | R9C10[1][A] | pwm_1/n43_s49/F |
| 3.948 | 0.004 | tNET | FF | 1 | R9C10[1][B] | pwm_1/n43_s51/I1 |
| 4.412 | 0.464 | tINS | FF | 1 | R9C10[1][B] | pwm_1/n43_s51/F |
| 4.412 | 0.000 | tNET | FF | 1 | R9C10[1][B] | pwm_1/tc_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R9C10[1][B] | pwm_1/tc_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R9C10[1][B] | pwm_1/tc_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 1.742, 51.569%; route: 1.296, 38.377%; tC2Q: 0.340, 10.054% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path20
Path Summary:
| Slack | 9996.659 |
| Data Arrival Time | 4.067 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_7_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 2.526 | 0.024 | tNET | FF | 1 | R11C11[2][B] | pwm_1/n32_s5/I0 |
| 3.291 | 0.765 | tINS | FF | 4 | R11C11[2][B] | pwm_1/n32_s5/F |
| 3.303 | 0.012 | tNET | FF | 1 | R11C11[1][A] | pwm_1/n32_s2/I2 |
| 4.068 | 0.765 | tINS | FF | 1 | R11C11[1][A] | pwm_1/n32_s2/F |
| 4.068 | 0.000 | tNET | FF | 1 | R11C11[1][A] | pwm_1/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R11C11[1][A] | pwm_1/count_7_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R11C11[1][A] | pwm_1/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 2.344, 77.261%; route: 0.350, 11.543%; tC2Q: 0.340, 11.196% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path21
Path Summary:
| Slack | 9996.659 |
| Data Arrival Time | 4.067 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_8_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 2.526 | 0.024 | tNET | FF | 1 | R11C11[2][B] | pwm_1/n32_s5/I0 |
| 3.291 | 0.765 | tINS | FF | 4 | R11C11[2][B] | pwm_1/n32_s5/F |
| 3.303 | 0.012 | tNET | FF | 1 | R11C11[0][B] | pwm_1/n31_s2/I1 |
| 4.068 | 0.765 | tINS | FF | 1 | R11C11[0][B] | pwm_1/n31_s2/F |
| 4.068 | 0.000 | tNET | FF | 1 | R11C11[0][B] | pwm_1/count_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R11C11[0][B] | pwm_1/count_8_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R11C11[0][B] | pwm_1/count_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 4 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 2.344, 77.261%; route: 0.350, 11.543%; tC2Q: 0.340, 11.196% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path22
Path Summary:
| Slack | 9996.782 |
| Data Arrival Time | 3.944 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_4_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 3.130 | 0.629 | tNET | FF | 1 | R11C10[0][A] | pwm_1/n35_s2/I2 |
| 3.945 | 0.814 | tINS | FF | 1 | R11C10[0][A] | pwm_1/n35_s2/F |
| 3.945 | 0.000 | tNET | FF | 1 | R11C10[0][A] | pwm_1/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R11C10[0][A] | pwm_1/count_4_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R11C10[0][A] | pwm_1/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 1.629, 55.960%; route: 0.942, 32.371%; tC2Q: 0.340, 11.669% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path23
Path Summary:
| Slack | 9997.436 |
| Data Arrival Time | 3.291 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_5_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 2.526 | 0.024 | tNET | FF | 1 | R11C11[2][A] | pwm_1/n34_s2/I1 |
| 3.291 | 0.765 | tINS | FF | 1 | R11C11[2][A] | pwm_1/n34_s2/F |
| 3.291 | 0.000 | tNET | FF | 1 | R11C11[2][A] | pwm_1/count_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R11C11[2][A] | pwm_1/count_5_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R11C11[2][A] | pwm_1/count_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 1.579, 69.973%; route: 0.338, 14.977%; tC2Q: 0.340, 15.050% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path24
Path Summary:
| Slack | 9997.436 |
| Data Arrival Time | 3.291 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_6_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RR | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.687 | 0.314 | tNET | RR | 1 | R11C11[3][B] | pwm_1/n35_s3/I0 |
| 2.502 | 0.814 | tINS | RF | 7 | R11C11[3][B] | pwm_1/n35_s3/F |
| 2.526 | 0.024 | tNET | FF | 1 | R11C11[1][B] | pwm_1/n33_s2/I0 |
| 3.291 | 0.765 | tINS | FF | 1 | R11C11[1][B] | pwm_1/n33_s2/F |
| 3.291 | 0.000 | tNET | FF | 1 | R11C11[1][B] | pwm_1/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R11C11[1][B] | pwm_1/count_6_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R11C11[1][B] | pwm_1/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 1.579, 69.973%; route: 0.338, 14.977%; tC2Q: 0.340, 15.050% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Path25
Path Summary:
| Slack | 9997.604 |
| Data Arrival Time | 3.123 |
| Data Required Time | 10000.727 |
| From | pwm_1/count_1_s0 |
| To | pwm_1/count_3_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 1.034 | 1.034 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 1.374 | 0.340 | tC2Q | RF | 5 | R11C10[1][B] | pwm_1/count_1_s0/Q |
| 1.745 | 0.371 | tNET | FF | 1 | R11C10[2][B] | pwm_1/n37_s3/I0 |
| 2.354 | 0.609 | tINS | FF | 1 | R11C10[2][B] | pwm_1/n37_s3/F |
| 2.358 | 0.004 | tNET | FF | 1 | R11C10[1][A] | pwm_1/n36_s2/I1 |
| 3.123 | 0.765 | tINS | FF | 1 | R11C10[1][A] | pwm_1/n36_s2/F |
| 3.123 | 0.000 | tNET | FF | 1 | R11C10[1][A] | pwm_1/count_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 9999.989 | 9999.989 | active clock edge time | ||||
| 9999.989 | 0.000 | clk100khz | ||||
| 9999.989 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 10001.023 | 1.034 | tNET | RR | 1 | R11C10[1][A] | pwm_1/count_3_s0/CLK |
| 10000.727 | -0.296 | tSu | 1 | R11C10[1][A] | pwm_1/count_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 9999.989 |
| Logic Level | 3 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
| Arrival Data Path Delay | cell: 1.374, 65.774%; route: 0.375, 17.966%; tC2Q: 0.340, 16.260% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.034, 100.000% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 1.278 |
| Data Required Time | 0.754 |
| From | pwm_1/count_15_s0 |
| To | pwm_1/count_15_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R9C11[0][A] | pwm_1/count_15_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 2 | R9C11[0][A] | pwm_1/count_15_s0/Q |
| 1.002 | 0.002 | tNET | RR | 1 | R9C11[0][A] | pwm_1/n24_s2/I3 |
| 1.278 | 0.276 | tINS | RF | 1 | R9C11[0][A] | pwm_1/n24_s2/F |
| 1.278 | 0.000 | tNET | FF | 1 | R9C11[0][A] | pwm_1/count_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R9C11[0][A] | pwm_1/count_15_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R9C11[0][A] | pwm_1/count_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path2
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_1_s0 |
| To | clkdiv_1/count_1_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C9[1][A] | clkdiv_1/count_1_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R11C9[1][A] | clkdiv_1/count_1_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R11C9[1][A] | clkdiv_1/n61_s5/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R11C9[1][A] | clkdiv_1/n61_s5/F |
| 2.054 | 0.000 | tNET | FF | 1 | R11C9[1][A] | clkdiv_1/count_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C9[1][A] | clkdiv_1/count_1_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C9[1][A] | clkdiv_1/count_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path3
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 1.279 |
| Data Required Time | 0.754 |
| From | pwm_1/count_3_s0 |
| To | pwm_1/count_3_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C10[1][A] | pwm_1/count_3_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 3 | R11C10[1][A] | pwm_1/count_3_s0/Q |
| 1.003 | 0.003 | tNET | RR | 1 | R11C10[1][A] | pwm_1/n36_s2/I3 |
| 1.279 | 0.276 | tINS | RF | 1 | R11C10[1][A] | pwm_1/n36_s2/F |
| 1.279 | 0.000 | tNET | FF | 1 | R11C10[1][A] | pwm_1/count_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C10[1][A] | pwm_1/count_3_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C10[1][A] | pwm_1/count_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path4
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 1.279 |
| Data Required Time | 0.754 |
| From | pwm_1/count_7_s0 |
| To | pwm_1/count_7_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[1][A] | pwm_1/count_7_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 7 | R11C11[1][A] | pwm_1/count_7_s0/Q |
| 1.003 | 0.003 | tNET | RR | 1 | R11C11[1][A] | pwm_1/n32_s2/I1 |
| 1.279 | 0.276 | tINS | RF | 1 | R11C11[1][A] | pwm_1/n32_s2/F |
| 1.279 | 0.000 | tNET | FF | 1 | R11C11[1][A] | pwm_1/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[1][A] | pwm_1/count_7_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C11[1][A] | pwm_1/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path5
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 1.279 |
| Data Required Time | 0.754 |
| From | pwm_1/count_11_s0 |
| To | pwm_1/count_11_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C12[1][A] | pwm_1/count_11_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 5 | R11C12[1][A] | pwm_1/count_11_s0/Q |
| 1.003 | 0.003 | tNET | RR | 1 | R11C12[1][A] | pwm_1/n28_s2/I3 |
| 1.279 | 0.276 | tINS | RF | 1 | R11C12[1][A] | pwm_1/n28_s2/F |
| 1.279 | 0.000 | tNET | FF | 1 | R11C12[1][A] | pwm_1/count_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C12[1][A] | pwm_1/count_11_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C12[1][A] | pwm_1/count_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path6
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 1.280 |
| Data Required Time | 0.754 |
| From | pwm_1/count_0_s0 |
| To | pwm_1/count_0_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C9[0][A] | pwm_1/count_0_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 6 | R11C9[0][A] | pwm_1/count_0_s0/Q |
| 1.004 | 0.003 | tNET | RR | 1 | R11C9[0][A] | pwm_1/n39_s2/I0 |
| 1.280 | 0.276 | tINS | RF | 1 | R11C9[0][A] | pwm_1/n39_s2/F |
| 1.280 | 0.000 | tNET | FF | 1 | R11C9[0][A] | pwm_1/count_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C9[0][A] | pwm_1/count_0_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C9[0][A] | pwm_1/count_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path7
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 1.280 |
| Data Required Time | 0.754 |
| From | pwm_1/count_4_s0 |
| To | pwm_1/count_4_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C10[0][A] | pwm_1/count_4_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 8 | R11C10[0][A] | pwm_1/count_4_s0/Q |
| 1.004 | 0.003 | tNET | RR | 1 | R11C10[0][A] | pwm_1/n35_s2/I1 |
| 1.280 | 0.276 | tINS | RF | 1 | R11C10[0][A] | pwm_1/n35_s2/F |
| 1.280 | 0.000 | tNET | FF | 1 | R11C10[0][A] | pwm_1/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C10[0][A] | pwm_1/count_4_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C10[0][A] | pwm_1/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path8
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 1.280 |
| Data Required Time | 0.754 |
| From | pwm_1/count_9_s0 |
| To | pwm_1/count_9_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[0][A] | pwm_1/count_9_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 6 | R11C11[0][A] | pwm_1/count_9_s0/Q |
| 1.004 | 0.003 | tNET | RR | 1 | R11C11[0][A] | pwm_1/n30_s2/I1 |
| 1.280 | 0.276 | tINS | RF | 1 | R11C11[0][A] | pwm_1/n30_s2/F |
| 1.280 | 0.000 | tNET | FF | 1 | R11C11[0][A] | pwm_1/count_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[0][A] | pwm_1/count_9_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C11[0][A] | pwm_1/count_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path9
Path Summary:
| Slack | 0.528 |
| Data Arrival Time | 2.057 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_8_s0 |
| To | clkdiv_1/count_8_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/count_8_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 8 | R9C8[0][A] | clkdiv_1/count_8_s0/Q |
| 1.781 | 0.005 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/n54_s6/I2 |
| 2.057 | 0.276 | tINS | RF | 1 | R9C8[0][A] | clkdiv_1/n54_s6/F |
| 2.057 | 0.000 | tNET | FF | 1 | R9C8[0][A] | clkdiv_1/count_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/count_8_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C8[0][A] | clkdiv_1/count_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.217%; route: 0.005, 0.994%; tC2Q: 0.247, 46.789% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path10
Path Summary:
| Slack | 0.662 |
| Data Arrival Time | 1.416 |
| Data Required Time | 0.754 |
| From | pwm_1/count_5_s0 |
| To | pwm_1/count_5_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[2][A] | pwm_1/count_5_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 7 | R11C11[2][A] | pwm_1/count_5_s0/Q |
| 1.004 | 0.003 | tNET | RR | 1 | R11C11[2][A] | pwm_1/n34_s2/I3 |
| 1.416 | 0.412 | tINS | RR | 1 | R11C11[2][A] | pwm_1/n34_s2/F |
| 1.416 | 0.000 | tNET | RR | 1 | R11C11[2][A] | pwm_1/count_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[2][A] | pwm_1/count_5_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C11[2][A] | pwm_1/count_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.412, 62.189%; route: 0.003, 0.528%; tC2Q: 0.247, 37.283% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path11
Path Summary:
| Slack | 0.663 |
| Data Arrival Time | 2.192 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_4_s0 |
| To | clkdiv_1/count_4_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C9[2][A] | clkdiv_1/count_4_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R11C9[2][A] | clkdiv_1/count_4_s0/Q |
| 1.780 | 0.004 | tNET | RR | 1 | R11C9[2][A] | clkdiv_1/n58_s6/I1 |
| 2.192 | 0.412 | tINS | RR | 1 | R11C9[2][A] | clkdiv_1/n58_s6/F |
| 2.192 | 0.000 | tNET | RR | 1 | R11C9[2][A] | clkdiv_1/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C9[2][A] | clkdiv_1/count_4_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C9[2][A] | clkdiv_1/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.412, 62.107%; route: 0.004, 0.659%; tC2Q: 0.247, 37.234% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path12
Path Summary:
| Slack | 0.701 |
| Data Arrival Time | 1.455 |
| Data Required Time | 0.754 |
| From | pwm_1/count_9_s0 |
| To | pwm_1/count_10_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[0][A] | pwm_1/count_9_s0/CLK |
| 1.001 | 0.247 | tC2Q | RF | 6 | R11C11[0][A] | pwm_1/count_9_s0/Q |
| 1.179 | 0.179 | tNET | FF | 1 | R11C12[1][B] | pwm_1/n29_s2/I0 |
| 1.455 | 0.276 | tINS | FF | 1 | R11C12[1][B] | pwm_1/n29_s2/F |
| 1.455 | 0.000 | tNET | FF | 1 | R11C12[1][B] | pwm_1/count_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C12[1][B] | pwm_1/count_10_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C12[1][B] | pwm_1/count_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 39.312%; route: 0.179, 25.462%; tC2Q: 0.247, 35.226% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path13
Path Summary:
| Slack | 0.701 |
| Data Arrival Time | 2.230 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_4_s0 |
| To | clkdiv_1/count_5_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C9[2][A] | clkdiv_1/count_4_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R11C9[2][A] | clkdiv_1/count_4_s0/Q |
| 1.954 | 0.179 | tNET | RR | 1 | R11C9[2][B] | clkdiv_1/n57_s5/I1 |
| 2.230 | 0.276 | tINS | RF | 1 | R11C9[2][B] | clkdiv_1/n57_s5/F |
| 2.230 | 0.000 | tNET | FF | 1 | R11C9[2][B] | clkdiv_1/count_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C9[2][B] | clkdiv_1/count_5_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C9[2][B] | clkdiv_1/count_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 39.305%; route: 0.179, 25.476%; tC2Q: 0.247, 35.219% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path14
Path Summary:
| Slack | 0.706 |
| Data Arrival Time | 1.460 |
| Data Required Time | 0.754 |
| From | pwm_1/count_0_s0 |
| To | pwm_1/count_1_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C9[0][A] | pwm_1/count_0_s0/CLK |
| 1.001 | 0.247 | tC2Q | RF | 6 | R11C9[0][A] | pwm_1/count_0_s0/Q |
| 1.184 | 0.184 | tNET | FF | 1 | R11C10[1][B] | pwm_1/n38_s2/I2 |
| 1.460 | 0.276 | tINS | FF | 1 | R11C10[1][B] | pwm_1/n38_s2/F |
| 1.460 | 0.000 | tNET | FF | 1 | R11C10[1][B] | pwm_1/count_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C10[1][B] | pwm_1/count_1_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C10[1][B] | pwm_1/count_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 39.022%; route: 0.184, 26.011%; tC2Q: 0.247, 34.966% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path15
Path Summary:
| Slack | 0.708 |
| Data Arrival Time | 2.237 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_0_s0 |
| To | clkdiv_1/count_2_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C9[3][A] | clkdiv_1/count_0_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R11C9[3][A] | clkdiv_1/count_0_s0/Q |
| 1.961 | 0.185 | tNET | RR | 1 | R11C9[1][B] | clkdiv_1/n60_s5/I1 |
| 2.237 | 0.276 | tINS | RF | 1 | R11C9[1][B] | clkdiv_1/n60_s5/F |
| 2.237 | 0.000 | tNET | FF | 1 | R11C9[1][B] | clkdiv_1/count_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C9[1][B] | clkdiv_1/count_2_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C9[1][B] | clkdiv_1/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 38.939%; route: 0.185, 26.169%; tC2Q: 0.247, 34.892% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path16
Path Summary:
| Slack | 0.726 |
| Data Arrival Time | 2.255 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_8_s0 |
| To | clkdiv_1/count_3_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/count_8_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 8 | R9C8[0][A] | clkdiv_1/count_8_s0/Q |
| 1.979 | 0.203 | tNET | RR | 1 | R11C8[1][A] | clkdiv_1/n59_s5/I2 |
| 2.255 | 0.276 | tINS | RF | 1 | R11C8[1][A] | clkdiv_1/n59_s5/F |
| 2.255 | 0.000 | tNET | FF | 1 | R11C8[1][A] | clkdiv_1/count_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C8[1][A] | clkdiv_1/count_3_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C8[1][A] | clkdiv_1/count_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 37.962%; route: 0.203, 28.021%; tC2Q: 0.247, 34.016% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path17
Path Summary:
| Slack | 0.726 |
| Data Arrival Time | 2.255 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_8_s0 |
| To | clkdiv_1/count_7_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/count_8_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 8 | R9C8[0][A] | clkdiv_1/count_8_s0/Q |
| 1.979 | 0.203 | tNET | RR | 1 | R11C8[0][A] | clkdiv_1/n55_s5/I2 |
| 2.255 | 0.276 | tINS | RF | 1 | R11C8[0][A] | clkdiv_1/n55_s5/F |
| 2.255 | 0.000 | tNET | FF | 1 | R11C8[0][A] | clkdiv_1/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C8[0][A] | clkdiv_1/count_7_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C8[0][A] | clkdiv_1/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 37.962%; route: 0.203, 28.021%; tC2Q: 0.247, 34.016% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path18
Path Summary:
| Slack | 0.785 |
| Data Arrival Time | 1.539 |
| Data Required Time | 0.754 |
| From | pwm_1/count_14_s0 |
| To | pwm_1/count_14_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R9C11[0][B] | pwm_1/count_14_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 3 | R9C11[0][B] | pwm_1/count_14_s0/Q |
| 1.002 | 0.002 | tNET | RR | 1 | R9C11[0][B] | pwm_1/n25_s2/I3 |
| 1.539 | 0.536 | tINS | RR | 1 | R9C11[0][B] | pwm_1/n25_s2/F |
| 1.539 | 0.000 | tNET | RR | 1 | R9C11[0][B] | pwm_1/count_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R9C11[0][B] | pwm_1/count_14_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R9C11[0][B] | pwm_1/count_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.536, 68.322%; route: 0.002, 0.223%; tC2Q: 0.247, 31.456% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path19
Path Summary:
| Slack | 0.786 |
| Data Arrival Time | 1.540 |
| Data Required Time | 0.754 |
| From | pwm_1/count_12_s0 |
| To | pwm_1/count_12_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C12[0][B] | pwm_1/count_12_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 3 | R11C12[0][B] | pwm_1/count_12_s0/Q |
| 1.003 | 0.003 | tNET | RR | 1 | R11C12[0][B] | pwm_1/n27_s2/I3 |
| 1.540 | 0.536 | tINS | RR | 1 | R11C12[0][B] | pwm_1/n27_s2/F |
| 1.540 | 0.000 | tNET | RR | 1 | R11C12[0][B] | pwm_1/count_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C12[0][B] | pwm_1/count_12_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C12[0][B] | pwm_1/count_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path20
Path Summary:
| Slack | 0.787 |
| Data Arrival Time | 1.541 |
| Data Required Time | 0.754 |
| From | pwm_1/count_2_s0 |
| To | pwm_1/count_2_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C10[0][B] | pwm_1/count_2_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 4 | R11C10[0][B] | pwm_1/count_2_s0/Q |
| 1.004 | 0.003 | tNET | RR | 1 | R11C10[0][B] | pwm_1/n37_s4/I1 |
| 1.541 | 0.536 | tINS | RR | 1 | R11C10[0][B] | pwm_1/n37_s4/F |
| 1.541 | 0.000 | tNET | RR | 1 | R11C10[0][B] | pwm_1/count_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C10[0][B] | pwm_1/count_2_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C10[0][B] | pwm_1/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.536, 68.170%; route: 0.003, 0.445%; tC2Q: 0.247, 31.386% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path21
Path Summary:
| Slack | 0.787 |
| Data Arrival Time | 1.541 |
| Data Required Time | 0.754 |
| From | pwm_1/count_6_s0 |
| To | pwm_1/count_6_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[1][B] | pwm_1/count_6_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 5 | R11C11[1][B] | pwm_1/count_6_s0/Q |
| 1.004 | 0.003 | tNET | RR | 1 | R11C11[1][B] | pwm_1/n33_s2/I3 |
| 1.541 | 0.536 | tINS | RR | 1 | R11C11[1][B] | pwm_1/n33_s2/F |
| 1.541 | 0.000 | tNET | RR | 1 | R11C11[1][B] | pwm_1/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[1][B] | pwm_1/count_6_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C11[1][B] | pwm_1/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.536, 68.170%; route: 0.003, 0.445%; tC2Q: 0.247, 31.386% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path22
Path Summary:
| Slack | 0.788 |
| Data Arrival Time | 1.542 |
| Data Required Time | 0.754 |
| From | pwm_1/count_8_s0 |
| To | pwm_1/count_8_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[0][B] | pwm_1/count_8_s0/CLK |
| 1.001 | 0.247 | tC2Q | RR | 7 | R11C11[0][B] | pwm_1/count_8_s0/Q |
| 1.005 | 0.004 | tNET | RR | 1 | R11C11[0][B] | pwm_1/n31_s2/I3 |
| 1.542 | 0.536 | tINS | RR | 1 | R11C11[0][B] | pwm_1/n31_s2/F |
| 1.542 | 0.000 | tNET | RR | 1 | R11C11[0][B] | pwm_1/count_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R11C11[0][B] | pwm_1/count_8_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R11C11[0][B] | pwm_1/count_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.536, 68.094%; route: 0.004, 0.555%; tC2Q: 0.247, 31.351% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path23
Path Summary:
| Slack | 0.861 |
| Data Arrival Time | 1.614 |
| Data Required Time | 0.754 |
| From | pwm_1/tc_s0 |
| To | pwm_1/count_13_s0 |
| Launch Clk | clk100khz:[R] |
| Latch Clk | clk100khz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R9C10[1][B] | pwm_1/tc_s0/CLK |
| 1.001 | 0.247 | tC2Q | RF | 16 | R9C10[1][B] | pwm_1/tc_s0/Q |
| 1.202 | 0.202 | tNET | FF | 1 | R9C11[3][A] | pwm_1/n26_s2/I0 |
| 1.614 | 0.412 | tINS | FR | 1 | R9C11[3][A] | pwm_1/n26_s2/F |
| 1.614 | 0.000 | tNET | RR | 1 | R9C11[3][A] | pwm_1/count_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk100khz | ||||
| 0.000 | 0.000 | tCL | RR | 18 | R11C7[0][A] | clkdiv_1/clk_out_s0/Q |
| 0.754 | 0.754 | tNET | RR | 1 | R9C11[3][A] | pwm_1/count_13_s0/CLK |
| 0.754 | 0.000 | tHld | 1 | R9C11[3][A] | pwm_1/count_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
| Arrival Data Path Delay | cell: 0.412, 47.865%; route: 0.202, 23.439%; tC2Q: 0.247, 28.696% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.754, 100.000% |
Path24
Path Summary:
| Slack | 0.950 |
| Data Arrival Time | 2.478 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_8_s0 |
| To | clkdiv_1/clk_out_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/count_8_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 8 | R9C8[0][A] | clkdiv_1/count_8_s0/Q |
| 2.203 | 0.427 | tNET | RR | 1 | R11C7[0][A] | clkdiv_1/n64_s86/I0 |
| 2.478 | 0.276 | tINS | RF | 1 | R11C7[0][A] | clkdiv_1/n64_s86/F |
| 2.478 | 0.000 | tNET | FF | 1 | R11C7[0][A] | clkdiv_1/clk_out_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C7[0][A] | clkdiv_1/clk_out_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C7[0][A] | clkdiv_1/clk_out_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 29.026%; route: 0.427, 44.966%; tC2Q: 0.247, 26.009% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path25
Path Summary:
| Slack | 0.968 |
| Data Arrival Time | 2.497 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_8_s0 |
| To | clkdiv_1/count_6_s0 |
| Launch Clk | clk:[R] |
| Latch Clk | clk:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/count_8_s0/CLK |
| 1.776 | 0.247 | tC2Q | RF | 8 | R9C8[0][A] | clkdiv_1/count_8_s0/Q |
| 1.959 | 0.183 | tNET | FF | 1 | R9C9[0][A] | clkdiv_1/n56_s7/I2 |
| 2.497 | 0.538 | tINS | FR | 1 | R9C9[0][A] | clkdiv_1/n56_s7/F |
| 2.497 | 0.000 | tNET | RR | 1 | R9C9[0][A] | clkdiv_1/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 15 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C9[0][A] | clkdiv_1/count_6_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C9[0][A] | clkdiv_1/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.538, 55.558%; route: 0.183, 18.933%; tC2Q: 0.247, 25.509% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | compare_7_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | compare_7_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | compare_7_s1/CLK |
MPW2
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | compare_2_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | compare_2_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | compare_2_s1/CLK |
MPW3
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_1/count_7_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_7_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_7_s0/CLK |
MPW4
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_1/clk_out_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/clk_out_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/clk_out_s0/CLK |
MPW5
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_1/count_0_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_0_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_0_s0/CLK |
MPW6
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_1/count_8_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_8_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_8_s0/CLK |
MPW7
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_1/count_1_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_1_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_1_s0/CLK |
MPW8
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | clkdiv_1/count_2_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_2_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_2_s0/CLK |
MPW9
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | compare_4_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | compare_4_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | compare_4_s1/CLK |
MPW10
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk |
| Objects: | compare_6_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | compare_6_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | compare_6_s1/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 18 | clk100khz | 9993.365 | 1.144 |
| 16 | tc | 9997.613 | 0.976 |
| 15 | clk_d | 32.529 | 0.195 |
| 8 | count[4] | 9993.479 | 0.979 |
| 8 | count[8] | 34.192 | 0.614 |
| 7 | count[8] | 9996.021 | 0.611 |
| 7 | count[7] | 9994.831 | 1.335 |
| 7 | count[5] | 9994.927 | 0.963 |
| 7 | n35_7 | 9995.657 | 0.979 |
| 6 | count[9] | 9995.977 | 0.624 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R11C11 | 77.78% |
| R11C9 | 73.61% |
| R8C13 | 68.06% |
| R11C10 | 61.11% |
| R9C11 | 55.56% |
| R11C8 | 43.06% |
| R11C12 | 41.67% |
| R9C8 | 38.89% |
| R9C9 | 30.56% |
| R11C7 | 27.78% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name clk -period 37.037 -waveform {0 18.518} [get_ports {clk}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk100khz -source [get_ports {clk}] -master_clock clk -divide_by 270 [get_nets {clk100khz}] |
| TC_FALSE_PATH | Actived | set_false_path -from [get_clocks {clk}] -to [get_clocks {clk100khz}] |