PnR Messages

Report Title PnR Report
Design File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\simple_io\impl\gwsynthesis\simple_io.vg
Physical Constraints File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\simple_io\src\simple_io.cst
Timing Constraints File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Wed Dec 18 11:33:57 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s Placement Phase 1: CPU time = 0h 0m 0.027s, Elapsed time = 0h 0m 0.027s Placement Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Placement Phase 3: CPU time = 0h 0m 0.61s, Elapsed time = 0h 0m 0.61s Total Placement: CPU time = 0h 0m 0.637s, Elapsed time = 0h 0m 0.638s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.028s, Elapsed time = 0h 0m 0.028s Routing Phase 2: CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.009s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.037s, Elapsed time = 0h 0m 0.037s Generate output files: CPU time = 0h 0m 0.182s, Elapsed time = 0h 0m 0.182s
Total Time and Memory Usage CPU time = 0h 0m 0.856s, Elapsed time = 0h 0m 0.857s, Peak memory usage = 210MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 0/1584 0%
    --LUT,ALU,ROM16 0(0 LUT, 0 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 0/1704 0%
    --Logic Register as Latch 0/1584 0%
    --Logic Register as FF 0/1584 0%
    --I/O Register as Latch 0/120 0%
    --I/O Register as FF 0/120 0%
I/O Port 2/40 5%
I/O Buf 2 -
    --Input Buf 1 -
    --Output Buf 1 -
    --Inout Buf 0 -

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 0/100%
bank 1 1/1010%
bank 2 0/100%
bank 3 1/250%
bank 4 0/40%
bank 5 0/40%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 0/8 0%
LW 0/8 0%
GCLK_PIN 0/6 0%

Global Clock Signals:

Signal Global Clock Location

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
ts0 - 11/3 Y in IOL17[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
led0 - 28/1 Y out IOR15[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
48/0 - out IOT7[A] LVCMOS18 8 NONE NA NA OFF NA NA NA 1.8
47/0 - in IOT7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
45/0 - in IOT9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
44/0 - in IOT9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
43/0 - in IOT14[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
42/0 - in IOT14[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
41/0 - in IOT15[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
40/0 - in IOT15[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
38/0 - in IOT18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
37/0 - in IOT18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
14/2 - in IOB2[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
15/2 - in IOB2[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
16/2 - in IOB5[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
17/2 - in IOB5[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
18/2 - in IOB7[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
19/2 - in IOB7[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
20/2 - in IOB9[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
21/2 - in IOB9[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
23/2 - in IOB18[A] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
24/2 - in IOB18[B] LVCMOS18 NA UP ON NONE NA NA NA NA 1.8
2/5 - in IOL4[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
3/5 - in IOL4[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
4/5 - in IOL6[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
5/5 - in IOL6[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
7/4 - in IOL11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
8/4 - in IOL11[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
9/4 - in IOL12[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
10/4 - in IOL12[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
11/3 ts0 in IOL17[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
12/3 - in IOL17[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
36/1 - in IOR1[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
35/1 - in IOR1[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
34/1 - in IOR11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
33/1 - in IOR11[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
32/1 - in IOR13[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
31/1 - in IOR13[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
29/1 - in IOR15[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
28/1 led0 out IOR15[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
27/1 - in IOR17[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
26/1 - in IOR17[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3