Synthesis Messages

Report Title GowinSynthesis Report
Design File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\add4bit\src\add4bit.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\add4bit\src\clkdiv.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\add4bit\src\drv7seg.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\add4bit\src\mux7seg.sv
C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\add4bit\src\test_add4bit.sv
GowinSynthesis Constraints File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Mon Dec 16 16:44:42 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module test_add4bit
Synthesis Process Running parser:
    CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.059s, Peak memory usage = 231.199MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 231.199MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 231.199MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 231.199MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 231.199MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 231.199MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 231.199MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.734s, Elapsed time = 0h 0m 0.764s, Peak memory usage = 231.199MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 231.199MB
Generate output files:
    CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 231.199MB
Total Time and Memory Usage CPU time = 0h 0m 0.827s, Elapsed time = 0h 0m 0.849s, Peak memory usage = 231.199MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 21
I/O Buf 21
    IBUF 9
    OBUF 12
Register 40
    DFF 7
    DFFS 4
    DFFR 29
LUT 63
    LUT2 7
    LUT3 11
    LUT4 45
ALU 25
    ALU 25
INV 4
    INV 4

Resource Utilization Summary

Resource Usage Utilization
Logic 92(67 LUT, 25 ALU) / 1584 6%
Register 40 / 1704 3%
  --Register as Latch 0 / 1704 0%
  --Register as FF 40 / 1704 3%
BSRAM 0 / 4 0%

Timing

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
1 clk Base 20.000 50.0 0.000 10.000 clk_ibuf/I
2 clkdiv_1/clk_160hz Base 20.000 50.0 0.000 10.000 clkdiv_1/clk_out_s1/Q

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk 50.000(MHz) 118.894(MHz) 6 TOP
2 clkdiv_1/clk_160hz 50.000(MHz) 227.334(MHz) 3 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 11.589
Data Arrival Time 8.917
Data Required Time 20.506
From clkdiv_1/count_0_s0
To clkdiv_1/count_25_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 27 clk_ibuf/O
0.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
0.878 0.340 tC2Q RF 3 clkdiv_1/count_0_s0/Q
1.589 0.711 tNET FF 1 clkdiv_1/tc_s87/I1
2.403 0.814 tINS FF 1 clkdiv_1/tc_s87/F
3.115 0.711 tNET FF 1 clkdiv_1/tc_s84/I1
3.929 0.814 tINS FF 1 clkdiv_1/tc_s84/F
4.640 0.711 tNET FF 1 clkdiv_1/tc_s81/I0
5.405 0.765 tINS FF 1 clkdiv_1/tc_s81/F
6.116 0.711 tNET FF 1 clkdiv_1/tc_s79/I0
6.881 0.765 tINS FF 1 clkdiv_1/tc_s79/F
7.593 0.711 tNET FF 1 clkdiv_1/tc_s78/I1
8.379 0.786 tINS FR 26 clkdiv_1/tc_s78/F
8.917 0.538 tNET RR 1 clkdiv_1/count_25_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 27 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_1/count_25_s0/CLK
20.506 -0.032 tSu 1 clkdiv_1/count_25_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.944, 47.076%; route: 4.095, 48.871%; tC2Q: 0.340, 4.053%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 2

Path Summary:
Slack 11.589
Data Arrival Time 8.917
Data Required Time 20.506
From clkdiv_1/count_0_s0
To clkdiv_1/count_0_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 27 clk_ibuf/O
0.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
0.878 0.340 tC2Q RF 3 clkdiv_1/count_0_s0/Q
1.589 0.711 tNET FF 1 clkdiv_1/tc_s87/I1
2.403 0.814 tINS FF 1 clkdiv_1/tc_s87/F
3.115 0.711 tNET FF 1 clkdiv_1/tc_s84/I1
3.929 0.814 tINS FF 1 clkdiv_1/tc_s84/F
4.640 0.711 tNET FF 1 clkdiv_1/tc_s81/I0
5.405 0.765 tINS FF 1 clkdiv_1/tc_s81/F
6.116 0.711 tNET FF 1 clkdiv_1/tc_s79/I0
6.881 0.765 tINS FF 1 clkdiv_1/tc_s79/F
7.593 0.711 tNET FF 1 clkdiv_1/tc_s78/I1
8.379 0.786 tINS FR 26 clkdiv_1/tc_s78/F
8.917 0.538 tNET RR 1 clkdiv_1/count_0_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 27 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
20.506 -0.032 tSu 1 clkdiv_1/count_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.944, 47.076%; route: 4.095, 48.871%; tC2Q: 0.340, 4.053%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 3

Path Summary:
Slack 11.589
Data Arrival Time 8.917
Data Required Time 20.506
From clkdiv_1/count_0_s0
To clkdiv_1/count_1_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 27 clk_ibuf/O
0.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
0.878 0.340 tC2Q RF 3 clkdiv_1/count_0_s0/Q
1.589 0.711 tNET FF 1 clkdiv_1/tc_s87/I1
2.403 0.814 tINS FF 1 clkdiv_1/tc_s87/F
3.115 0.711 tNET FF 1 clkdiv_1/tc_s84/I1
3.929 0.814 tINS FF 1 clkdiv_1/tc_s84/F
4.640 0.711 tNET FF 1 clkdiv_1/tc_s81/I0
5.405 0.765 tINS FF 1 clkdiv_1/tc_s81/F
6.116 0.711 tNET FF 1 clkdiv_1/tc_s79/I0
6.881 0.765 tINS FF 1 clkdiv_1/tc_s79/F
7.593 0.711 tNET FF 1 clkdiv_1/tc_s78/I1
8.379 0.786 tINS FR 26 clkdiv_1/tc_s78/F
8.917 0.538 tNET RR 1 clkdiv_1/count_1_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 27 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_1/count_1_s0/CLK
20.506 -0.032 tSu 1 clkdiv_1/count_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.944, 47.076%; route: 4.095, 48.871%; tC2Q: 0.340, 4.053%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 4

Path Summary:
Slack 11.589
Data Arrival Time 8.917
Data Required Time 20.506
From clkdiv_1/count_0_s0
To clkdiv_1/count_2_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 27 clk_ibuf/O
0.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
0.878 0.340 tC2Q RF 3 clkdiv_1/count_0_s0/Q
1.589 0.711 tNET FF 1 clkdiv_1/tc_s87/I1
2.403 0.814 tINS FF 1 clkdiv_1/tc_s87/F
3.115 0.711 tNET FF 1 clkdiv_1/tc_s84/I1
3.929 0.814 tINS FF 1 clkdiv_1/tc_s84/F
4.640 0.711 tNET FF 1 clkdiv_1/tc_s81/I0
5.405 0.765 tINS FF 1 clkdiv_1/tc_s81/F
6.116 0.711 tNET FF 1 clkdiv_1/tc_s79/I0
6.881 0.765 tINS FF 1 clkdiv_1/tc_s79/F
7.593 0.711 tNET FF 1 clkdiv_1/tc_s78/I1
8.379 0.786 tINS FR 26 clkdiv_1/tc_s78/F
8.917 0.538 tNET RR 1 clkdiv_1/count_2_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 27 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_1/count_2_s0/CLK
20.506 -0.032 tSu 1 clkdiv_1/count_2_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.944, 47.076%; route: 4.095, 48.871%; tC2Q: 0.340, 4.053%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%

Path 5

Path Summary:
Slack 11.589
Data Arrival Time 8.917
Data Required Time 20.506
From clkdiv_1/count_0_s0
To clkdiv_1/count_3_s0
Launch Clk clk[R]
Latch Clk clk[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clk
0.000 0.000 tCL RR 1 clk_ibuf/I
0.000 0.000 tINS RR 27 clk_ibuf/O
0.538 0.538 tNET RR 1 clkdiv_1/count_0_s0/CLK
0.878 0.340 tC2Q RF 3 clkdiv_1/count_0_s0/Q
1.589 0.711 tNET FF 1 clkdiv_1/tc_s87/I1
2.403 0.814 tINS FF 1 clkdiv_1/tc_s87/F
3.115 0.711 tNET FF 1 clkdiv_1/tc_s84/I1
3.929 0.814 tINS FF 1 clkdiv_1/tc_s84/F
4.640 0.711 tNET FF 1 clkdiv_1/tc_s81/I0
5.405 0.765 tINS FF 1 clkdiv_1/tc_s81/F
6.116 0.711 tNET FF 1 clkdiv_1/tc_s79/I0
6.881 0.765 tINS FF 1 clkdiv_1/tc_s79/F
7.593 0.711 tNET FF 1 clkdiv_1/tc_s78/I1
8.379 0.786 tINS FR 26 clkdiv_1/tc_s78/F
8.917 0.538 tNET RR 1 clkdiv_1/count_3_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
20.000 0.000 clk
20.000 0.000 tCL RR 1 clk_ibuf/I
20.000 0.000 tINS RR 27 clk_ibuf/O
20.538 0.538 tNET RR 1 clkdiv_1/count_3_s0/CLK
20.506 -0.032 tSu 1 clkdiv_1/count_3_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 20.000
Logic Level: 6
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%
Arrival Data Path Delay: cell: 3.944, 47.076%; route: 4.095, 48.871%; tC2Q: 0.340, 4.053%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.538, 100.000%