PnR Messages

Report Title PnR Report
Design File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stump\impl\gwsynthesis\stump.vg
Physical Constraints File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stump\src\stump.cst
Timing Constraints File ---
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Thu Nov 28 14:43:19 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.017s, Elapsed time = 0h 0m 0.017s Placement Phase 1: CPU time = 0h 0m 0.035s, Elapsed time = 0h 0m 0.036s Placement Phase 2: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s Placement Phase 3: CPU time = 0h 0m 0.652s, Elapsed time = 0h 0m 0.652s Total Placement: CPU time = 0h 0m 0.706s, Elapsed time = 0h 0m 0.707s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.038s, Elapsed time = 0h 0m 0.038s Routing Phase 2: CPU time = 0h 0m 0.021s, Elapsed time = 0h 0m 0.021s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.059s, Elapsed time = 0h 0m 0.059s Generate output files: CPU time = 0h 0m 0.186s, Elapsed time = 0h 0m 0.186s
Total Time and Memory Usage CPU time = 0h 0m 0.951s, Elapsed time = 0h 0m 0.952s, Peak memory usage = 207MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 12/1584 <1%
    --LUT,ALU,ROM16 12(12 LUT, 0 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 0/1704 0%
    --Logic Register as Latch 0/1584 0%
    --Logic Register as FF 0/1584 0%
    --I/O Register as Latch 0/120 0%
    --I/O Register as FF 0/120 0%
I/O Port 32/40 80%
I/O Buf 29 -
    --Input Buf 9 -
    --Output Buf 20 -
    --Inout Buf 0 -

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 4/1040%
bank 1 9/1090%
bank 2 10/10100%
bank 3 2/2100%
bank 4 4/4100%
bank 5 3/475%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 0/8 0%
LW 0/8 0%
GCLK_PIN 5/6 84%

Global Clock Signals:

Signal Global Clock Location

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
tsw[0] - 11/3 Y in IOL17[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tsw[1] - 10/4 Y in IOL12[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tsw[2] - 9/4 Y in IOL12[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tsw[3] - 8/4 Y in IOL11[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tsw[4] - 7/4 Y in IOL11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tsw[5] - 5/5 Y in IOL6[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tsw[6] - 3/5 Y in IOL4[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
tsw[7] - 2/5 Y in IOL4[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
psw[0] - 32/1 Y in IOR13[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
psw[1] - 33/1 Y in IOR11[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
psw[2] - 34/1 Y in IOR11[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
psw[3] - 35/1 Y in IOR1[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
led[0] - 28/1 Y out IOR15[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
led[1] - 27/1 Y out IOR17[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
led[2] - 42/0 Y out IOT14[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
led[3] - 43/0 Y out IOT14[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
led[4] - 16/2 Y out IOB5[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
led[5] - 17/2 Y out IOB5[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
led[6] - 24/2 Y out IOB18[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
led[7] - 23/2 Y out IOB18[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[0] - 26/1 Y out IOR17[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[1] - 21/2 Y out IOB9[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[2] - 20/2 Y out IOB9[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[3] - 19/2 Y out IOB7[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[4] - 18/2 Y out IOB7[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[5] - 15/2 Y out IOB2[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[6] - 14/2 Y out IOB2[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[7] - 12/3 Y out IOL17[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
dig[0] - 31/1 Y out IOR13[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
dig[1] - 29/1 Y out IOR15[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
dig[2] - 40/0 Y out IOT15[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
dig[3] - 41/0 Y out IOT15[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
48/0 - out IOT7[A] LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
47/0 - in IOT7[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
45/0 - in IOT9[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
44/0 - in IOT9[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
43/0 led[3] out IOT14[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
42/0 led[2] out IOT14[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
41/0 dig[3] out IOT15[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
40/0 dig[2] out IOT15[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
38/0 - in IOT18[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
37/0 - in IOT18[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
14/2 seg[6] out IOB2[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
15/2 seg[5] out IOB2[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
16/2 led[4] out IOB5[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
17/2 led[5] out IOB5[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
18/2 seg[4] out IOB7[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
19/2 seg[3] out IOB7[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
20/2 seg[2] out IOB9[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
21/2 seg[1] out IOB9[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
23/2 led[7] out IOB18[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
24/2 led[6] out IOB18[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
2/5 tsw[7] in IOL4[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
3/5 tsw[6] in IOL4[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
4/5 - in IOL6[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
5/5 tsw[5] in IOL6[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
7/4 tsw[4] in IOL11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
8/4 tsw[3] in IOL11[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
9/4 tsw[2] in IOL12[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
10/4 tsw[1] in IOL12[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
11/3 tsw[0] in IOL17[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
12/3 seg[7] out IOL17[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
36/1 - in IOR1[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
35/1 psw[3] in IOR1[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
34/1 psw[2] in IOR11[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
33/1 psw[1] in IOR11[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
32/1 psw[0] in IOR13[A] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
31/1 dig[0] out IOR13[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
29/1 dig[1] out IOR15[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
28/1 led[0] out IOR15[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
27/1 led[1] out IOR17[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
26/1 seg[0] out IOR17[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3