Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\pwm_servo\src\clkdiv.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\pwm_servo\src\pwm.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\pwm_servo\src\test_pwm_servo.sv |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW1N-UV1P5QN48XFC7/I6 |
| Device | GW1N-1P5 |
| Device Version | C |
| Created Time | Wed Dec 18 11:22:34 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | test_pwm_servo |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.096s, Peak memory usage = 146.012MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 146.012MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 146.012MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.004s, Peak memory usage = 146.012MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 146.012MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 146.012MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 146.012MB Inferring Phase 3: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0s, Peak memory usage = 146.012MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 146.012MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 146.012MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 146.012MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.203s, Elapsed time = 0h 0m 0.295s, Peak memory usage = 174.254MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.02s, Peak memory usage = 174.254MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.025s, Peak memory usage = 174.254MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.294s, Elapsed time = 0h 0m 0.456s, Peak memory usage = 174.254MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 15 |
| I/O Buf | 15 |
|     IBUF | 6 |
|     OBUF | 9 |
| Register | 33 |
|     DFFE | 3 |
|     DFFPE | 2 |
|     DFFC | 25 |
|     DFFCE | 3 |
| LUT | 64 |
|     LUT2 | 9 |
|     LUT3 | 11 |
|     LUT4 | 44 |
| ALU | 4 |
|     ALU | 4 |
| INV | 1 |
|     INV | 1 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 69(65 LUT, 4 ALU) / 1584 | 5% |
| Register | 33 / 1704 | 2% |
|   --Register as Latch | 0 / 1704 | 0% |
|   --Register as FF | 33 / 1704 | 2% |
| BSRAM | 0 / 4 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | clkdiv_1/clk100khz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_1/clk_out_s0/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 170.216(MHz) | 4 | TOP |
| 2 | clkdiv_1/clk100khz | 50.000(MHz) | 145.622(MHz) | 6 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 13.038 |
| Data Arrival Time | 7.173 |
| Data Required Time | 20.212 |
| From | compare_1_s1 |
| To | pwm_1/line_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clkdiv_1/clk100khz[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 15 | clk_ibuf/O |
| 0.538 | 0.538 | tNET | RR | 1 | compare_1_s1/CLK |
| 0.878 | 0.340 | tC2Q | RF | 1 | compare_1_s1/Q |
| 1.589 | 0.711 | tNET | FF | 2 | pwm_1/n40_s42/I1 |
| 2.363 | 0.774 | tINS | FF | 1 | pwm_1/n40_s42/COUT |
| 2.363 | 0.000 | tNET | FF | 2 | pwm_1/n40_s43/CIN |
| 2.406 | 0.042 | tINS | FF | 1 | pwm_1/n40_s43/COUT |
| 2.406 | 0.000 | tNET | FF | 2 | pwm_1/n40_s44/CIN |
| 2.448 | 0.042 | tINS | FF | 1 | pwm_1/n40_s44/COUT |
| 2.448 | 0.000 | tNET | FF | 2 | pwm_1/n40_s45/CIN |
| 2.490 | 0.042 | tINS | FF | 1 | pwm_1/n40_s45/COUT |
| 3.201 | 0.711 | tNET | FF | 1 | pwm_1/n61_s5/I3 |
| 3.665 | 0.464 | tINS | FF | 1 | pwm_1/n61_s5/F |
| 4.377 | 0.711 | tNET | FF | 1 | pwm_1/n61_s2/I2 |
| 4.986 | 0.609 | tINS | FF | 1 | pwm_1/n61_s2/F |
| 5.697 | 0.711 | tNET | FF | 1 | pwm_1/n61_s7/I0 |
| 6.462 | 0.765 | tINS | FF | 1 | pwm_1/n61_s7/F |
| 7.173 | 0.711 | tNET | FF | 1 | pwm_1/line_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clkdiv_1/clk100khz | |||
| 20.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
| 20.538 | 0.538 | tNET | RR | 1 | pwm_1/line_s0/CLK |
| 20.508 | -0.030 | tUnc | pwm_1/line_s0 | ||
| 20.212 | -0.296 | tSu | 1 | pwm_1/line_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 6 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 2.739, 41.276%; route: 3.557, 53.605%; tC2Q: 0.340, 5.119% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 2
Path Summary:| Slack | 14.075 |
| Data Arrival Time | 6.166 |
| Data Required Time | 20.242 |
| From | pwm_1/count_0_s0 |
| To | pwm_1/tc_s0 |
| Launch Clk | clkdiv_1/clk100khz[R] |
| Latch Clk | clkdiv_1/clk100khz[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clkdiv_1/clk100khz | |||
| 0.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
| 0.538 | 0.538 | tNET | RR | 1 | pwm_1/count_0_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 6 | pwm_1/count_0_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | pwm_1/n35_s3/I1 |
| 2.403 | 0.814 | tINS | FF | 7 | pwm_1/n35_s3/F |
| 3.115 | 0.711 | tNET | FF | 1 | pwm_1/n43_s49/I1 |
| 3.929 | 0.814 | tINS | FF | 1 | pwm_1/n43_s49/F |
| 4.640 | 0.711 | tNET | FF | 1 | pwm_1/n43_s51/I1 |
| 5.455 | 0.814 | tINS | FF | 1 | pwm_1/n43_s51/F |
| 6.166 | 0.711 | tNET | FF | 1 | pwm_1/tc_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clkdiv_1/clk100khz | |||
| 20.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
| 20.538 | 0.538 | tNET | RR | 1 | pwm_1/tc_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | pwm_1/tc_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 3
Path Summary:| Slack | 14.075 |
| Data Arrival Time | 6.166 |
| Data Required Time | 20.242 |
| From | pwm_1/count_5_s0 |
| To | pwm_1/count_10_s0 |
| Launch Clk | clkdiv_1/clk100khz[R] |
| Latch Clk | clkdiv_1/clk100khz[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clkdiv_1/clk100khz | |||
| 0.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
| 0.538 | 0.538 | tNET | RR | 1 | pwm_1/count_5_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 7 | pwm_1/count_5_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | pwm_1/n32_s4/I1 |
| 2.403 | 0.814 | tINS | FF | 1 | pwm_1/n32_s4/F |
| 3.115 | 0.711 | tNET | FF | 1 | pwm_1/n30_s5/I1 |
| 3.929 | 0.814 | tINS | FF | 2 | pwm_1/n30_s5/F |
| 4.640 | 0.711 | tNET | FF | 1 | pwm_1/n29_s2/I1 |
| 5.455 | 0.814 | tINS | FF | 1 | pwm_1/n29_s2/F |
| 6.166 | 0.711 | tNET | FF | 1 | pwm_1/count_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clkdiv_1/clk100khz | |||
| 20.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
| 20.538 | 0.538 | tNET | RR | 1 | pwm_1/count_10_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | pwm_1/count_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 4
Path Summary:| Slack | 14.075 |
| Data Arrival Time | 6.166 |
| Data Required Time | 20.242 |
| From | pwm_1/count_0_s0 |
| To | pwm_1/count_14_s0 |
| Launch Clk | clkdiv_1/clk100khz[R] |
| Latch Clk | clkdiv_1/clk100khz[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clkdiv_1/clk100khz | |||
| 0.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
| 0.538 | 0.538 | tNET | RR | 1 | pwm_1/count_0_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 6 | pwm_1/count_0_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | pwm_1/n35_s3/I1 |
| 2.403 | 0.814 | tINS | FF | 7 | pwm_1/n35_s3/F |
| 3.115 | 0.711 | tNET | FF | 1 | pwm_1/n26_s3/I1 |
| 3.929 | 0.814 | tINS | FF | 3 | pwm_1/n26_s3/F |
| 4.640 | 0.711 | tNET | FF | 1 | pwm_1/n25_s2/I1 |
| 5.455 | 0.814 | tINS | FF | 1 | pwm_1/n25_s2/F |
| 6.166 | 0.711 | tNET | FF | 1 | pwm_1/count_14_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clkdiv_1/clk100khz | |||
| 20.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
| 20.538 | 0.538 | tNET | RR | 1 | pwm_1/count_14_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | pwm_1/count_14_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 2.443, 43.408%; route: 2.845, 50.558%; tC2Q: 0.340, 6.034% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 5
Path Summary:| Slack | 14.125 |
| Data Arrival Time | 6.116 |
| Data Required Time | 20.242 |
| From | pwm_1/count_0_s0 |
| To | pwm_1/count_15_s0 |
| Launch Clk | clkdiv_1/clk100khz[R] |
| Latch Clk | clkdiv_1/clk100khz[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clkdiv_1/clk100khz | |||
| 0.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
| 0.538 | 0.538 | tNET | RR | 1 | pwm_1/count_0_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 6 | pwm_1/count_0_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | pwm_1/n35_s3/I1 |
| 2.403 | 0.814 | tINS | FF | 7 | pwm_1/n35_s3/F |
| 3.115 | 0.711 | tNET | FF | 1 | pwm_1/n26_s3/I1 |
| 3.929 | 0.814 | tINS | FF | 3 | pwm_1/n26_s3/F |
| 4.640 | 0.711 | tNET | FF | 1 | pwm_1/n24_s2/I0 |
| 5.405 | 0.765 | tINS | FF | 1 | pwm_1/n24_s2/F |
| 6.116 | 0.711 | tNET | FF | 1 | pwm_1/count_15_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clkdiv_1/clk100khz | |||
| 20.000 | 0.000 | tCL | RR | 18 | clkdiv_1/clk_out_s0/Q |
| 20.538 | 0.538 | tNET | RR | 1 | pwm_1/count_15_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | pwm_1/count_15_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 4 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 2.393, 42.905%; route: 2.845, 51.007%; tC2Q: 0.340, 6.088% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |