Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\clkdiv.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\cntr4max.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\cntr4maxe.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\debounce.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\drv7seg.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\mux7seg.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\run_led.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\stopwatch.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\toggle.sv |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW1N-UV1P5QN48XFC7/I6 |
| Device | GW1N-1P5 |
| Device Version | C |
| Created Time | Thu Nov 28 14:46:18 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | stopwatch |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.074s, Peak memory usage = 207.746MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.01s, Peak memory usage = 207.746MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 207.746MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 207.746MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 207.746MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 207.746MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 207.746MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 207.746MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.013s, Peak memory usage = 207.746MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 207.746MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 207.746MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.625s, Elapsed time = 0h 0m 0.698s, Peak memory usage = 207.746MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 207.746MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.022s, Peak memory usage = 207.746MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.763s, Elapsed time = 0h 0m 0.885s, Peak memory usage = 207.746MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 25 |
| I/O Buf | 25 |
|     IBUF | 5 |
|     OBUF | 20 |
| Register | 103 |
|     DFFE | 2 |
|     DFFP | 8 |
|     DFFPE | 8 |
|     DFFC | 68 |
|     DFFCE | 17 |
| LUT | 244 |
|     LUT2 | 28 |
|     LUT3 | 107 |
|     LUT4 | 109 |
| INV | 3 |
|     INV | 3 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 247(247 LUT, 0 ALU) / 1584 | 16% |
| Register | 103 / 1704 | 7% |
|   --Register as Latch | 0 / 1704 | 0% |
|   --Register as FF | 103 / 1704 | 7% |
| BSRAM | 0 / 4 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | clkdiv_2/clk400hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_2/clk400hz_s10/F | ||
| 3 | clkdiv_3/clk160hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_3/clk_out_s0/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 134.223(MHz) | 5 | TOP |
| 2 | clkdiv_2/clk400hz | 50.000(MHz) | 348.056(MHz) | 2 | TOP |
| 3 | clkdiv_3/clk160hz | 50.000(MHz) | 306.479(MHz) | 2 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 7.974 |
| Data Arrival Time | 12.237 |
| Data Required Time | 20.212 |
| From | clkdiv_2/n62_s2 |
| To | clkdiv_2/count_0_s0 |
| Launch Clk | clkdiv_2/clk400hz[R] |
| Latch Clk | clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clkdiv_2/clk400hz | |||
| 10.000 | 0.000 | tCL | FF | 22 | clkdiv_2/clk400hz_s10/F |
| 10.711 | 0.711 | tNET | FF | 1 | clkdiv_2/n62_s2/I1 |
| 11.526 | 0.814 | tINS | FF | 1 | clkdiv_2/n62_s2/F |
| 12.237 | 0.711 | tNET | FF | 1 | clkdiv_2/count_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 84 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | clkdiv_2/count_0_s0/CLK |
| 20.508 | -0.030 | tUnc | clkdiv_2/count_0_s0 | ||
| 20.212 | -0.296 | tSu | 1 | clkdiv_2/count_0_s0 |
| Clock Skew: | 0.538 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 0.814, 36.402%; route: 0.711, 31.799%; tC2Q: 0.711, 31.799% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 2
Path Summary:| Slack | 8.024 |
| Data Arrival Time | 12.187 |
| Data Required Time | 20.212 |
| From | clkdiv_2/n61_s2 |
| To | clkdiv_2/count_1_s0 |
| Launch Clk | clkdiv_2/clk400hz[R] |
| Latch Clk | clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clkdiv_2/clk400hz | |||
| 10.000 | 0.000 | tCL | FF | 22 | clkdiv_2/clk400hz_s10/F |
| 10.711 | 0.711 | tNET | FF | 1 | clkdiv_2/n61_s2/I0 |
| 11.476 | 0.765 | tINS | FF | 1 | clkdiv_2/n61_s2/F |
| 12.187 | 0.711 | tNET | FF | 1 | clkdiv_2/count_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 84 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | clkdiv_2/count_1_s0/CLK |
| 20.508 | -0.030 | tUnc | clkdiv_2/count_1_s0 | ||
| 20.212 | -0.296 | tSu | 1 | clkdiv_2/count_1_s0 |
| Clock Skew: | 0.538 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 0.765, 34.960%; route: 0.711, 32.520%; tC2Q: 0.711, 32.520% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 3
Path Summary:| Slack | 8.024 |
| Data Arrival Time | 12.187 |
| Data Required Time | 20.212 |
| From | clkdiv_2/n60_s4 |
| To | clkdiv_2/count_2_s0 |
| Launch Clk | clkdiv_2/clk400hz[R] |
| Latch Clk | clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clkdiv_2/clk400hz | |||
| 10.000 | 0.000 | tCL | FF | 22 | clkdiv_2/clk400hz_s10/F |
| 10.711 | 0.711 | tNET | FF | 1 | clkdiv_2/n60_s4/I0 |
| 11.476 | 0.765 | tINS | FF | 1 | clkdiv_2/n60_s4/F |
| 12.187 | 0.711 | tNET | FF | 1 | clkdiv_2/count_2_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 84 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | clkdiv_2/count_2_s0/CLK |
| 20.508 | -0.030 | tUnc | clkdiv_2/count_2_s0 | ||
| 20.212 | -0.296 | tSu | 1 | clkdiv_2/count_2_s0 |
| Clock Skew: | 0.538 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 0.765, 34.960%; route: 0.711, 32.520%; tC2Q: 0.711, 32.520% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 4
Path Summary:| Slack | 8.024 |
| Data Arrival Time | 12.187 |
| Data Required Time | 20.212 |
| From | clkdiv_2/n58_s2 |
| To | clkdiv_2/count_4_s0 |
| Launch Clk | clkdiv_2/clk400hz[R] |
| Latch Clk | clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clkdiv_2/clk400hz | |||
| 10.000 | 0.000 | tCL | FF | 22 | clkdiv_2/clk400hz_s10/F |
| 10.711 | 0.711 | tNET | FF | 1 | clkdiv_2/n58_s2/I0 |
| 11.476 | 0.765 | tINS | FF | 1 | clkdiv_2/n58_s2/F |
| 12.187 | 0.711 | tNET | FF | 1 | clkdiv_2/count_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 84 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | clkdiv_2/count_4_s0/CLK |
| 20.508 | -0.030 | tUnc | clkdiv_2/count_4_s0 | ||
| 20.212 | -0.296 | tSu | 1 | clkdiv_2/count_4_s0 |
| Clock Skew: | 0.538 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 0.765, 34.960%; route: 0.711, 32.520%; tC2Q: 0.711, 32.520% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
Path 5
Path Summary:| Slack | 8.024 |
| Data Arrival Time | 12.187 |
| Data Required Time | 20.212 |
| From | clkdiv_2/n55_s2 |
| To | clkdiv_2/count_7_s0 |
| Launch Clk | clkdiv_2/clk400hz[R] |
| Latch Clk | clk[F] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 10.000 | 0.000 | clkdiv_2/clk400hz | |||
| 10.000 | 0.000 | tCL | FF | 22 | clkdiv_2/clk400hz_s10/F |
| 10.711 | 0.711 | tNET | FF | 1 | clkdiv_2/n55_s2/I0 |
| 11.476 | 0.765 | tINS | FF | 1 | clkdiv_2/n55_s2/F |
| 12.187 | 0.711 | tNET | FF | 1 | clkdiv_2/count_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 84 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | clkdiv_2/count_7_s0/CLK |
| 20.508 | -0.030 | tUnc | clkdiv_2/count_7_s0 | ||
| 20.212 | -0.296 | tSu | 1 | clkdiv_2/count_7_s0 |
| Clock Skew: | 0.538 |
| Setup Relationship: | 10.000 |
| Logic Level: | 2 |
| Arrival Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |
| Arrival Data Path Delay: | cell: 0.765, 34.960%; route: 0.711, 32.520%; tC2Q: 0.711, 32.520% |
| Required Clock Path Delay: | cell: 0.000, 100.000%; route: 0.000, 0.000% |