Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\src\clkdiv.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\src\debounce.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\src\drv7seg.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\src\mux7seg.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\src\rx.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\src\test_uart.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\src\toggle.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\uart\src\tx.sv |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW1N-UV1P5QN48XFC7/I6 |
| Device | GW1N-1P5 |
| Device Version | C |
| Created Time | Thu Dec 19 14:41:27 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | test_uart |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.107s, Peak memory usage = 134.598MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 134.598MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 134.598MB Optimizing Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.014s, Peak memory usage = 134.598MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 134.598MB Inferring Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 134.598MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 134.598MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 134.598MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 134.598MB Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 134.598MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 134.598MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.703s, Elapsed time = 0h 0m 0.769s, Peak memory usage = 164.215MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.069s, Peak memory usage = 164.215MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.04s, Peak memory usage = 164.215MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.871s, Elapsed time = 0h 0m 1s, Peak memory usage = 164.215MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 33 |
| I/O Buf | 33 |
|     IBUF | 12 |
|     OBUF | 21 |
| Register | 126 |
|     DFFE | 18 |
|     DFFP | 10 |
|     DFFPE | 1 |
|     DFFC | 64 |
|     DFFCE | 33 |
| LUT | 236 |
|     LUT2 | 44 |
|     LUT3 | 95 |
|     LUT4 | 97 |
| INV | 5 |
|     INV | 5 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 241(241 LUT, 0 ALU) / 1584 | 16% |
| Register | 126 / 1704 | 8% |
|   --Register as Latch | 0 / 1704 | 0% |
|   --Register as FF | 126 / 1704 | 8% |
| BSRAM | 0 / 4 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | clkdiv_3/clk400hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_3/clk_out_s0/Q | ||
| 3 | clkdiv_1/clkbaudhz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_1/clk_out_s0/Q | ||
| 4 | clkdiv_2/clkbaudx2hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_2/clk_out_s0/Q | ||
| 5 | clkdiv_4/clk160hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_4/clk_out_s0/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 134.223(MHz) | 5 | TOP |
| 2 | clkdiv_3/clk400hz | 50.000(MHz) | 348.056(MHz) | 2 | TOP |
| 3 | clkdiv_1/clkbaudhz | 50.000(MHz) | 168.789(MHz) | 4 | TOP |
| 4 | clkdiv_2/clkbaudx2hz | 50.000(MHz) | 146.317(MHz) | 5 | TOP |
| 5 | clkdiv_4/clk160hz | 50.000(MHz) | 306.479(MHz) | 2 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 12.550 |
| Data Arrival Time | 7.692 |
| Data Required Time | 20.242 |
| From | clkdiv_4/count_1_s0 |
| To | clkdiv_4/count_17_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 54 | clk_ibuf/O |
| 0.538 | 0.538 | tNET | RR | 1 | clkdiv_4/count_1_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 6 | clkdiv_4/count_1_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | clkdiv_4/n58_s3/I1 |
| 2.403 | 0.814 | tINS | FF | 5 | clkdiv_4/n58_s3/F |
| 3.115 | 0.711 | tNET | FF | 1 | clkdiv_4/n49_s3/I1 |
| 3.929 | 0.814 | tINS | FF | 4 | clkdiv_4/n49_s3/F |
| 4.640 | 0.711 | tNET | FF | 1 | clkdiv_4/n46_s7/I1 |
| 5.455 | 0.814 | tINS | FF | 2 | clkdiv_4/n46_s7/F |
| 6.166 | 0.711 | tNET | FF | 1 | clkdiv_4/n45_s2/I1 |
| 6.980 | 0.814 | tINS | FF | 1 | clkdiv_4/n45_s2/F |
| 7.692 | 0.711 | tNET | FF | 1 | clkdiv_4/count_17_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 54 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | clkdiv_4/count_17_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | clkdiv_4/count_17_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 3.257, 45.534%; route: 3.557, 49.719%; tC2Q: 0.340, 4.747% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 2
Path Summary:| Slack | 12.550 |
| Data Arrival Time | 7.692 |
| Data Required Time | 20.242 |
| From | clkdiv_3/count_3_s0 |
| To | clkdiv_3/count_0_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 54 | clk_ibuf/O |
| 0.538 | 0.538 | tNET | RR | 1 | clkdiv_3/count_3_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 4 | clkdiv_3/count_3_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | clkdiv_3/n62_s8/I1 |
| 2.403 | 0.814 | tINS | FF | 1 | clkdiv_3/n62_s8/F |
| 3.115 | 0.711 | tNET | FF | 1 | clkdiv_3/n62_s5/I1 |
| 3.929 | 0.814 | tINS | FF | 1 | clkdiv_3/n62_s5/F |
| 4.640 | 0.711 | tNET | FF | 1 | clkdiv_3/n62_s11/I1 |
| 5.455 | 0.814 | tINS | FF | 17 | clkdiv_3/n62_s11/F |
| 6.166 | 0.711 | tNET | FF | 1 | clkdiv_3/n62_s3/I1 |
| 6.980 | 0.814 | tINS | FF | 1 | clkdiv_3/n62_s3/F |
| 7.692 | 0.711 | tNET | FF | 1 | clkdiv_3/count_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 54 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | clkdiv_3/count_0_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | clkdiv_3/count_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 3.257, 45.534%; route: 3.557, 49.719%; tC2Q: 0.340, 4.747% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 3
Path Summary:| Slack | 12.599 |
| Data Arrival Time | 7.642 |
| Data Required Time | 20.242 |
| From | clkdiv_4/count_0_s0 |
| To | clkdiv_4/count_0_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 54 | clk_ibuf/O |
| 0.538 | 0.538 | tNET | RR | 1 | clkdiv_4/count_0_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 6 | clkdiv_4/count_0_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | clkdiv_4/n62_s8/I1 |
| 2.403 | 0.814 | tINS | FF | 1 | clkdiv_4/n62_s8/F |
| 3.115 | 0.711 | tNET | FF | 1 | clkdiv_4/n62_s4/I1 |
| 3.929 | 0.814 | tINS | FF | 1 | clkdiv_4/n62_s4/F |
| 4.640 | 0.711 | tNET | FF | 1 | clkdiv_4/n62_s13/I0 |
| 5.405 | 0.765 | tINS | FF | 17 | clkdiv_4/n62_s13/F |
| 6.116 | 0.711 | tNET | FF | 1 | clkdiv_4/n62_s2/I1 |
| 6.931 | 0.814 | tINS | FF | 1 | clkdiv_4/n62_s2/F |
| 7.642 | 0.711 | tNET | FF | 1 | clkdiv_4/count_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 54 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | clkdiv_4/count_0_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | clkdiv_4/count_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 4
Path Summary:| Slack | 12.599 |
| Data Arrival Time | 7.642 |
| Data Required Time | 20.242 |
| From | clkdiv_3/count_1_s0 |
| To | clkdiv_3/clk_out_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 54 | clk_ibuf/O |
| 0.538 | 0.538 | tNET | RR | 1 | clkdiv_3/count_1_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 6 | clkdiv_3/count_1_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | clkdiv_3/n64_s86/I1 |
| 2.403 | 0.814 | tINS | FF | 1 | clkdiv_3/n64_s86/F |
| 3.115 | 0.711 | tNET | FF | 1 | clkdiv_3/n64_s82/I0 |
| 3.879 | 0.765 | tINS | FF | 1 | clkdiv_3/n64_s82/F |
| 4.591 | 0.711 | tNET | FF | 1 | clkdiv_3/n64_s80/I1 |
| 5.405 | 0.814 | tINS | FF | 1 | clkdiv_3/n64_s80/F |
| 6.116 | 0.711 | tNET | FF | 1 | clkdiv_3/n64_s87/I1 |
| 6.931 | 0.814 | tINS | FF | 1 | clkdiv_3/n64_s87/F |
| 7.642 | 0.711 | tNET | FF | 1 | clkdiv_3/clk_out_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 54 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | clkdiv_3/clk_out_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | clkdiv_3/clk_out_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 3.208, 45.153%; route: 3.557, 50.066%; tC2Q: 0.340, 4.781% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 5
Path Summary:| Slack | 12.649 |
| Data Arrival Time | 7.593 |
| Data Required Time | 20.242 |
| From | clkdiv_4/count_1_s0 |
| To | clkdiv_4/count_10_s0 |
| Launch Clk | clk[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clk | |||
| 0.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 0.000 | 0.000 | tINS | RR | 54 | clk_ibuf/O |
| 0.538 | 0.538 | tNET | RR | 1 | clkdiv_4/count_1_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 6 | clkdiv_4/count_1_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | clkdiv_4/n58_s3/I1 |
| 2.403 | 0.814 | tINS | FF | 5 | clkdiv_4/n58_s3/F |
| 3.115 | 0.711 | tNET | FF | 1 | clkdiv_4/n55_s5/I0 |
| 3.879 | 0.765 | tINS | FF | 5 | clkdiv_4/n55_s5/F |
| 4.591 | 0.711 | tNET | FF | 1 | clkdiv_4/n52_s6/I0 |
| 5.355 | 0.765 | tINS | FF | 2 | clkdiv_4/n52_s6/F |
| 6.067 | 0.711 | tNET | FF | 1 | clkdiv_4/n52_s2/I1 |
| 6.881 | 0.814 | tINS | FF | 1 | clkdiv_4/n52_s2/F |
| 7.593 | 0.711 | tNET | FF | 1 | clkdiv_4/count_10_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 54 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | clkdiv_4/count_10_s0/CLK |
| 20.242 | -0.296 | tSu | 1 | clkdiv_4/count_10_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 5 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 3.158, 44.767%; route: 3.557, 50.419%; tC2Q: 0.340, 4.814% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |