Timing Messages

Report Title Timing Analysis Report
Design File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\impl\gwsynthesis\leg4.vg
Physical Constraints File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\leg4.cst
Timing Constraint File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\leg4\src\leg4.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Mon Dec 16 17:40:17 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.71V 85C C7/I6
Hold Delay Model Fast 3.6V 0C C7/I6
Numbers of Paths Analyzed 598
Numbers of Endpoints Analyzed 305
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk27mhz Base 37.037 27.000 0.000 18.518 clk
2 clk1khz Generated 999998.938 0.001 0.000 499999.469 clk clk27mhz clk1khz
3 clk400hz Generated 2499997.500 0.000 0.000 1249998.750 clk clk27mhz clk400hz
4 clk1hz Generated 99999896.000 0.000 0.000 49999948.000 clk clk27mhz clk1hz
5 clk160hz Generated 6249993.500 0.000 0.000 3124996.750 clk clk27mhz clk160hz
6 clk10hz Generated 99999896.000 0.000 0.000 49999948.000 clk clk27mhz clk10hz
7 leg4_clk Generated 999998.938 0.001 0.000 499999.469 clk1khz clk1khz leg4_clk

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk27mhz 27.000(MHz) 138.518(MHz) 5 TOP
2 clk400hz 0.000(MHz) 363.636(MHz) 2 TOP
3 clk160hz 0.000(MHz) 181.818(MHz) 3 TOP
4 leg4_clk 0.001(MHz) 103.896(MHz) 8 TOP

No timing paths to get frequency of clk1khz!

No timing paths to get frequency of clk1hz!

No timing paths to get frequency of clk10hz!

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk27mhz Setup 0.000 0
clk27mhz Hold 0.000 0
clk1khz Setup 0.000 0
clk1khz Hold 0.000 0
clk400hz Setup 0.000 0
clk400hz Hold 0.000 0
clk1hz Setup 0.000 0
clk1hz Hold 0.000 0
clk160hz Setup 0.000 0
clk160hz Hold 0.000 0
clk10hz Setup 0.000 0
clk10hz Hold 0.000 0
leg4_clk Setup 0.000 0
leg4_clk Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 29.818 clkdiv_3/count_0_s0/Q clkdiv_3/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.923
2 29.847 clkdiv_3/count_0_s0/Q clkdiv_3/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.893
3 29.847 clkdiv_3/count_0_s0/Q clkdiv_3/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.893
4 29.847 clkdiv_3/count_0_s0/Q clkdiv_3/count_23_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.893
5 29.847 clkdiv_3/count_0_s0/Q clkdiv_3/count_24_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.893
6 29.854 clkdiv_3/count_0_s0/Q clkdiv_3/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.887
7 29.854 clkdiv_3/count_0_s0/Q clkdiv_3/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.887
8 29.854 clkdiv_3/count_0_s0/Q clkdiv_3/count_19_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.887
9 29.910 clkdiv_3/count_0_s0/Q clkdiv_3/count_18_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.831
10 29.914 clkdiv_3/count_0_s0/Q clkdiv_3/count_21_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.826
11 29.922 clkdiv_3/count_0_s0/Q clkdiv_3/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.819
12 29.922 clkdiv_3/count_0_s0/Q clkdiv_3/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.819
13 29.922 clkdiv_3/count_0_s0/Q clkdiv_3/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.819
14 29.922 clkdiv_3/count_0_s0/Q clkdiv_3/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.819
15 29.936 clkdiv_3/count_0_s0/Q clkdiv_3/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.805
16 30.120 clkdiv_3/count_0_s0/Q clkdiv_3/count_22_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.621
17 30.134 clkdiv_3/count_0_s0/Q clkdiv_3/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.607
18 30.134 clkdiv_3/count_0_s0/Q clkdiv_3/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.607
19 30.141 clkdiv_3/count_0_s0/Q clkdiv_3/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.600
20 30.141 clkdiv_3/count_0_s0/Q clkdiv_3/count_8_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.600
21 30.216 clkdiv_3/count_0_s0/Q clkdiv_3/count_20_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.524
22 30.226 clkdiv_3/count_0_s0/Q clkdiv_3/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.514
23 30.268 clkdiv_3/count_0_s0/Q clkdiv_3/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.473
24 30.473 clkdiv_3/count_0_s0/Q clkdiv_3/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.267
25 30.618 clkdiv_3/count_0_s0/Q clkdiv_3/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.122

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.423 debounce_1/key_n_2_s0/Q debounce_1/key_n_3_s0/D clk400hz:[R] clk400hz:[R] 0.000 0.000 0.423
2 0.524 clkdiv_5/count_15_s0/Q clkdiv_5/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.524
3 0.524 clkdiv_3/count_2_s0/Q clkdiv_3/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.524
4 0.524 clkdiv_3/count_16_s0/Q clkdiv_3/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.524
5 0.524 clkdiv_2/count_17_s0/Q clkdiv_2/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.524
6 0.525 clkdiv_5/count_7_s0/Q clkdiv_5/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
7 0.525 clkdiv_5/count_16_s0/Q clkdiv_5/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
8 0.525 clkdiv_4/count_7_s0/Q clkdiv_4/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
9 0.525 clkdiv_4/count_11_s0/Q clkdiv_4/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
10 0.525 clkdiv_4/count_13_s0/Q clkdiv_4/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
11 0.525 leg4_1/inst1/adr_0_s0/Q leg4_1/inst1/adr_0_s0/D leg4_clk:[R] leg4_clk:[R] 0.000 0.000 0.525
12 0.525 clkdiv_3/count_9_s0/Q clkdiv_3/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
13 0.525 clkdiv_2/count_16_s0/Q clkdiv_2/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
14 0.525 clkdiv_2/count_19_s0/Q clkdiv_2/count_19_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
15 0.525 clkdiv_2/count_21_s0/Q clkdiv_2/count_21_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
16 0.525 clkdiv_1/count_10_s0/Q clkdiv_1/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
17 0.526 clkdiv_5/count_0_s0/Q clkdiv_5/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
18 0.526 clkdiv_4/count_5_s0/Q clkdiv_4/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
19 0.526 clkdiv_3/count_4_s0/Q clkdiv_3/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
20 0.526 clkdiv_3/count_19_s0/Q clkdiv_3/count_19_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
21 0.526 clkdiv_3/count_21_s0/Q clkdiv_3/count_21_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
22 0.526 clkdiv_2/count_20_s0/Q clkdiv_2/count_20_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
23 0.526 clkdiv_1/count_4_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
24 0.526 clkdiv_1/count_11_s0/Q clkdiv_1/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
25 0.527 clkdiv_5/count_5_s0/Q clkdiv_5/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.527

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_16_s0
2 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_14_s0
3 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_10_s0
4 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_2_s0
5 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_2/count_9_s0
6 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_3/count_3_s0
7 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_3/count_4_s0
8 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_2/count_10_s0
9 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_3/count_5_s0
10 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_3/count_6_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 29.818
Data Arrival Time 9.192
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.377 0.742 tNET FF 1 R9C14[2][B] clkdiv_3/n50_s4/I3
9.192 0.814 tINS FF 1 R9C14[2][B] clkdiv_3/n50_s4/F
9.192 0.000 tNET FF 1 R9C14[2][B] clkdiv_3/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C14[2][B] clkdiv_3/count_12_s0/CLK
39.009 -0.296 tSu 1 R9C14[2][B] clkdiv_3/count_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.158, 45.619%; route: 3.425, 49.475%; tC2Q: 0.340, 4.906%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path2

Path Summary:

Slack 29.847
Data Arrival Time 9.162
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.398 0.763 tNET FF 1 R9C14[0][A] clkdiv_3/n53_s2/I2
9.162 0.765 tINS FF 1 R9C14[0][A] clkdiv_3/n53_s2/F
9.162 0.000 tNET FF 1 R9C14[0][A] clkdiv_3/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C14[0][A] clkdiv_3/count_9_s0/CLK
39.009 -0.296 tSu 1 R9C14[0][A] clkdiv_3/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.108, 45.093%; route: 3.445, 49.980%; tC2Q: 0.340, 4.927%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path3

Path Summary:

Slack 29.847
Data Arrival Time 9.162
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.398 0.763 tNET FF 1 R9C14[2][A] clkdiv_3/n51_s2/I2
9.162 0.765 tINS FF 1 R9C14[2][A] clkdiv_3/n51_s2/F
9.162 0.000 tNET FF 1 R9C14[2][A] clkdiv_3/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C14[2][A] clkdiv_3/count_11_s0/CLK
39.009 -0.296 tSu 1 R9C14[2][A] clkdiv_3/count_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.108, 45.093%; route: 3.445, 49.980%; tC2Q: 0.340, 4.927%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path4

Path Summary:

Slack 29.847
Data Arrival Time 9.162
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_23_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.398 0.763 tNET FF 1 R9C14[1][B] clkdiv_3/n39_s2/I2
9.162 0.765 tINS FF 1 R9C14[1][B] clkdiv_3/n39_s2/F
9.162 0.000 tNET FF 1 R9C14[1][B] clkdiv_3/count_23_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C14[1][B] clkdiv_3/count_23_s0/CLK
39.009 -0.296 tSu 1 R9C14[1][B] clkdiv_3/count_23_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.108, 45.093%; route: 3.445, 49.980%; tC2Q: 0.340, 4.927%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path5

Path Summary:

Slack 29.847
Data Arrival Time 9.162
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_24_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.398 0.763 tNET FF 1 R9C14[3][A] clkdiv_3/n38_s2/I3
9.162 0.765 tINS FF 1 R9C14[3][A] clkdiv_3/n38_s2/F
9.162 0.000 tNET FF 1 R9C14[3][A] clkdiv_3/count_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C14[3][A] clkdiv_3/count_24_s0/CLK
39.009 -0.296 tSu 1 R9C14[3][A] clkdiv_3/count_24_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.108, 45.093%; route: 3.445, 49.980%; tC2Q: 0.340, 4.927%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path6

Path Summary:

Slack 29.854
Data Arrival Time 9.155
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.391 0.756 tNET FF 1 R9C13[1][A] clkdiv_3/n59_s2/I0
9.155 0.765 tINS FF 1 R9C13[1][A] clkdiv_3/n59_s2/F
9.155 0.000 tNET FF 1 R9C13[1][A] clkdiv_3/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C13[1][A] clkdiv_3/count_3_s0/CLK
39.009 -0.296 tSu 1 R9C13[1][A] clkdiv_3/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.108, 45.138%; route: 3.439, 49.931%; tC2Q: 0.340, 4.932%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path7

Path Summary:

Slack 29.854
Data Arrival Time 9.155
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.391 0.756 tNET FF 1 R9C13[0][B] clkdiv_3/n49_s2/I3
9.155 0.765 tINS FF 1 R9C13[0][B] clkdiv_3/n49_s2/F
9.155 0.000 tNET FF 1 R9C13[0][B] clkdiv_3/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C13[0][B] clkdiv_3/count_13_s0/CLK
39.009 -0.296 tSu 1 R9C13[0][B] clkdiv_3/count_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.108, 45.138%; route: 3.439, 49.931%; tC2Q: 0.340, 4.932%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path8

Path Summary:

Slack 29.854
Data Arrival Time 9.155
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_19_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.391 0.756 tNET FF 1 R9C11[0][A] clkdiv_3/n43_s2/I2
9.155 0.765 tINS FF 1 R9C11[0][A] clkdiv_3/n43_s2/F
9.155 0.000 tNET FF 1 R9C11[0][A] clkdiv_3/count_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C11[0][A] clkdiv_3/count_19_s0/CLK
39.009 -0.296 tSu 1 R9C11[0][A] clkdiv_3/count_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.108, 45.138%; route: 3.439, 49.931%; tC2Q: 0.340, 4.932%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path9

Path Summary:

Slack 29.910
Data Arrival Time 9.100
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_18_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.636 1.001 tNET FF 1 R9C11[0][B] clkdiv_3/n44_s2/I3
9.100 0.464 tINS FF 1 R9C11[0][B] clkdiv_3/n44_s2/F
9.100 0.000 tNET FF 1 R9C11[0][B] clkdiv_3/count_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C11[0][B] clkdiv_3/count_18_s0/CLK
39.009 -0.296 tSu 1 R9C11[0][B] clkdiv_3/count_18_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.808, 41.102%; route: 3.684, 53.927%; tC2Q: 0.340, 4.972%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path10

Path Summary:

Slack 29.914
Data Arrival Time 9.095
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_21_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.281 0.646 tNET FF 1 R9C12[1][A] clkdiv_3/n41_s2/I2
9.095 0.814 tINS FF 1 R9C12[1][A] clkdiv_3/n41_s2/F
9.095 0.000 tNET FF 1 R9C12[1][A] clkdiv_3/count_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C12[1][A] clkdiv_3/count_21_s0/CLK
39.009 -0.296 tSu 1 R9C12[1][A] clkdiv_3/count_21_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.158, 46.264%; route: 3.329, 48.761%; tC2Q: 0.340, 4.975%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path11

Path Summary:

Slack 29.922
Data Arrival Time 9.087
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.273 0.638 tNET FF 1 R12C11[2][B] clkdiv_3/n62_s3/I1
9.087 0.814 tINS FF 1 R12C11[2][B] clkdiv_3/n62_s3/F
9.087 0.000 tNET FF 1 R12C11[2][B] clkdiv_3/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
39.009 -0.296 tSu 1 R12C11[2][B] clkdiv_3/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.158, 46.317%; route: 3.321, 48.702%; tC2Q: 0.340, 4.981%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path12

Path Summary:

Slack 29.922
Data Arrival Time 9.087
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.273 0.638 tNET FF 1 R12C11[0][A] clkdiv_3/n58_s2/I2
9.087 0.814 tINS FF 1 R12C11[0][A] clkdiv_3/n58_s2/F
9.087 0.000 tNET FF 1 R12C11[0][A] clkdiv_3/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C11[0][A] clkdiv_3/count_4_s0/CLK
39.009 -0.296 tSu 1 R12C11[0][A] clkdiv_3/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.158, 46.317%; route: 3.321, 48.702%; tC2Q: 0.340, 4.981%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path13

Path Summary:

Slack 29.922
Data Arrival Time 9.087
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.273 0.638 tNET FF 1 R12C11[1][A] clkdiv_3/n46_s2/I3
9.087 0.814 tINS FF 1 R12C11[1][A] clkdiv_3/n46_s2/F
9.087 0.000 tNET FF 1 R12C11[1][A] clkdiv_3/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C11[1][A] clkdiv_3/count_16_s0/CLK
39.009 -0.296 tSu 1 R12C11[1][A] clkdiv_3/count_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.158, 46.317%; route: 3.321, 48.702%; tC2Q: 0.340, 4.981%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path14

Path Summary:

Slack 29.922
Data Arrival Time 9.087
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.273 0.638 tNET FF 1 R12C11[2][A] clkdiv_3/n45_s4/I3
9.087 0.814 tINS FF 1 R12C11[2][A] clkdiv_3/n45_s4/F
9.087 0.000 tNET FF 1 R12C11[2][A] clkdiv_3/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C11[2][A] clkdiv_3/count_17_s0/CLK
39.009 -0.296 tSu 1 R12C11[2][A] clkdiv_3/count_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.158, 46.317%; route: 3.321, 48.702%; tC2Q: 0.340, 4.981%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path15

Path Summary:

Slack 29.936
Data Arrival Time 9.074
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.259 0.625 tNET FF 1 R12C12[1][A] clkdiv_3/n55_s2/I2
9.074 0.814 tINS FF 1 R12C12[1][A] clkdiv_3/n55_s2/F
9.074 0.000 tNET FF 1 R12C12[1][A] clkdiv_3/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C12[1][A] clkdiv_3/count_7_s0/CLK
39.009 -0.296 tSu 1 R12C12[1][A] clkdiv_3/count_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.158, 46.409%; route: 3.307, 48.601%; tC2Q: 0.340, 4.991%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path16

Path Summary:

Slack 30.120
Data Arrival Time 8.890
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_22_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.281 0.646 tNET FF 1 R9C12[0][B] clkdiv_3/n40_s2/I3
8.890 0.609 tINS FF 1 R9C12[0][B] clkdiv_3/n40_s2/F
8.890 0.000 tNET FF 1 R9C12[0][B] clkdiv_3/count_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C12[0][B] clkdiv_3/count_22_s0/CLK
39.009 -0.296 tSu 1 R9C12[0][B] clkdiv_3/count_22_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.953, 44.598%; route: 3.329, 50.272%; tC2Q: 0.340, 5.129%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path17

Path Summary:

Slack 30.134
Data Arrival Time 8.875
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.266 0.631 tNET FF 1 R12C11[0][B] clkdiv_3/n61_s2/I2
8.875 0.609 tINS FF 1 R12C11[0][B] clkdiv_3/n61_s2/F
8.875 0.000 tNET FF 1 R12C11[0][B] clkdiv_3/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C11[0][B] clkdiv_3/count_1_s0/CLK
39.009 -0.296 tSu 1 R12C11[0][B] clkdiv_3/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.953, 44.696%; route: 3.314, 50.163%; tC2Q: 0.340, 5.141%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path18

Path Summary:

Slack 30.134
Data Arrival Time 8.875
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.266 0.631 tNET FF 1 R12C11[1][B] clkdiv_3/n47_s2/I2
8.875 0.609 tINS FF 1 R12C11[1][B] clkdiv_3/n47_s2/F
8.875 0.000 tNET FF 1 R12C11[1][B] clkdiv_3/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C11[1][B] clkdiv_3/count_15_s0/CLK
39.009 -0.296 tSu 1 R12C11[1][B] clkdiv_3/count_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.953, 44.696%; route: 3.314, 50.163%; tC2Q: 0.340, 5.141%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path19

Path Summary:

Slack 30.141
Data Arrival Time 8.869
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.259 0.625 tNET FF 1 R12C13[0][A] clkdiv_3/n60_s2/I3
8.869 0.609 tINS FF 1 R12C13[0][A] clkdiv_3/n60_s2/F
8.869 0.000 tNET FF 1 R12C13[0][A] clkdiv_3/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C13[0][A] clkdiv_3/count_2_s0/CLK
39.009 -0.296 tSu 1 R12C13[0][A] clkdiv_3/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.953, 44.742%; route: 3.307, 50.112%; tC2Q: 0.340, 5.146%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path20

Path Summary:

Slack 30.141
Data Arrival Time 8.869
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_8_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.259 0.625 tNET FF 1 R12C12[0][B] clkdiv_3/n54_s2/I3
8.869 0.609 tINS FF 1 R12C12[0][B] clkdiv_3/n54_s2/F
8.869 0.000 tNET FF 1 R12C12[0][B] clkdiv_3/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C12[0][B] clkdiv_3/count_8_s0/CLK
39.009 -0.296 tSu 1 R12C12[0][B] clkdiv_3/count_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.953, 44.742%; route: 3.307, 50.112%; tC2Q: 0.340, 5.146%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path21

Path Summary:

Slack 30.216
Data Arrival Time 8.793
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_20_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.028 0.394 tNET FF 1 R9C12[1][B] clkdiv_3/n42_s2/I2
8.793 0.765 tINS FF 1 R9C12[1][B] clkdiv_3/n42_s2/F
8.793 0.000 tNET FF 1 R9C12[1][B] clkdiv_3/count_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C12[1][B] clkdiv_3/count_20_s0/CLK
39.009 -0.296 tSu 1 R9C12[1][B] clkdiv_3/count_20_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.108, 47.645%; route: 3.076, 47.149%; tC2Q: 0.340, 5.206%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path22

Path Summary:

Slack 30.226
Data Arrival Time 8.783
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.635 0.814 tINS FF 25 R11C12[2][B] clkdiv_3/n62_s4/F
8.018 0.383 tNET FF 1 R11C11[3][A] clkdiv_3/n48_s2/I2
8.783 0.765 tINS FF 1 R11C11[3][A] clkdiv_3/n48_s2/F
8.783 0.000 tNET FF 1 R11C11[3][A] clkdiv_3/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C11[3][A] clkdiv_3/count_14_s0/CLK
39.009 -0.296 tSu 1 R11C11[3][A] clkdiv_3/count_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.108, 47.719%; route: 3.066, 47.067%; tC2Q: 0.340, 5.214%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path23

Path Summary:

Slack 30.268
Data Arrival Time 8.741
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.607 0.786 tINS FR 25 R11C12[2][B] clkdiv_3/n62_s4/F
7.927 0.321 tNET RR 1 R12C12[2][A] clkdiv_3/n56_s2/I3
8.741 0.814 tINS RF 1 R12C12[2][A] clkdiv_3/n56_s2/F
8.741 0.000 tNET FF 1 R12C12[2][A] clkdiv_3/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C12[2][A] clkdiv_3/count_6_s0/CLK
39.009 -0.296 tSu 1 R12C12[2][A] clkdiv_3/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.130, 48.357%; route: 3.003, 46.396%; tC2Q: 0.340, 5.247%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path24

Path Summary:

Slack 30.473
Data Arrival Time 8.536
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.607 0.786 tINS FR 25 R11C12[2][B] clkdiv_3/n62_s4/F
7.927 0.321 tNET RR 1 R12C12[3][A] clkdiv_3/n57_s2/I3
8.536 0.609 tINS RF 1 R12C12[3][A] clkdiv_3/n57_s2/F
8.536 0.000 tNET FF 1 R12C12[3][A] clkdiv_3/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C12[3][A] clkdiv_3/count_5_s0/CLK
39.009 -0.296 tSu 1 R12C12[3][A] clkdiv_3/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.925, 46.665%; route: 3.003, 47.916%; tC2Q: 0.340, 5.419%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path25

Path Summary:

Slack 30.618
Data Arrival Time 8.391
Data Required Time 39.009
From clkdiv_3/count_0_s0
To clkdiv_3/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C11[2][B] clkdiv_3/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R12C11[2][B] clkdiv_3/count_0_s0/Q
3.950 1.342 tNET FF 1 R9C13[3][B] clkdiv_3/n58_s3/I1
4.715 0.765 tINS FF 9 R9C13[3][B] clkdiv_3/n58_s3/F
5.693 0.977 tNET FF 1 R12C12[3][B] clkdiv_3/n62_s5/I1
6.457 0.765 tINS FF 1 R12C12[3][B] clkdiv_3/n62_s5/F
6.820 0.363 tNET FF 1 R11C12[2][B] clkdiv_3/n62_s4/I0
7.607 0.786 tINS FR 25 R11C12[2][B] clkdiv_3/n62_s4/F
7.927 0.321 tNET RR 1 R12C12[1][B] clkdiv_3/n52_s2/I2
8.391 0.464 tINS RF 1 R12C12[1][B] clkdiv_3/n52_s2/F
8.391 0.000 tNET FF 1 R12C12[1][B] clkdiv_3/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 102 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C12[1][B] clkdiv_3/count_10_s0/CLK
39.009 -0.296 tSu 1 R12C12[1][B] clkdiv_3/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.779, 45.400%; route: 3.003, 49.052%; tC2Q: 0.340, 5.547%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.423
Data Arrival Time 1.191
Data Required Time 0.768
From debounce_1/key_n_2_s0
To debounce_1/key_n_3_s0
Launch Clk clk400hz:[R]
Latch Clk clk400hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk400hz
0.000 0.000 tCL RR 5 R13C12[0][A] clkdiv_1/clk_out_s0/Q
0.768 0.768 tNET RR 1 R6C11[2][B] debounce_1/key_n_2_s0/CLK
1.015 0.247 tC2Q RR 2 R6C11[2][B] debounce_1/key_n_2_s0/Q
1.191 0.176 tNET RR 1 R6C11[2][A] debounce_1/key_n_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk400hz
0.000 0.000 tCL RR 5 R13C12[0][A] clkdiv_1/clk_out_s0/Q
0.768 0.768 tNET RR 1 R6C11[2][A] debounce_1/key_n_3_s0/CLK
0.768 0.000 tHld 1 R6C11[2][A] debounce_1/key_n_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.768, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.176, 41.613%; tC2Q: 0.247, 58.387%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.768, 100.000%

Path2

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From clkdiv_5/count_15_s0
To clkdiv_5/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R6C10[1][A] clkdiv_5/count_15_s0/CLK
1.776 0.247 tC2Q RR 5 R6C10[1][A] clkdiv_5/count_15_s0/Q
1.778 0.002 tNET RR 1 R6C10[1][A] clkdiv_5/n47_s2/I2
2.053 0.276 tINS RF 1 R6C10[1][A] clkdiv_5/n47_s2/F
2.053 0.000 tNET FF 1 R6C10[1][A] clkdiv_5/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R6C10[1][A] clkdiv_5/count_15_s0/CLK
1.529 0.000 tHld 1 R6C10[1][A] clkdiv_5/count_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path3

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From clkdiv_3/count_2_s0
To clkdiv_3/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C13[0][A] clkdiv_3/count_2_s0/CLK
1.776 0.247 tC2Q RR 3 R12C13[0][A] clkdiv_3/count_2_s0/Q
1.778 0.002 tNET RR 1 R12C13[0][A] clkdiv_3/n60_s2/I2
2.053 0.276 tINS RF 1 R12C13[0][A] clkdiv_3/n60_s2/F
2.053 0.000 tNET FF 1 R12C13[0][A] clkdiv_3/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C13[0][A] clkdiv_3/count_2_s0/CLK
1.529 0.000 tHld 1 R12C13[0][A] clkdiv_3/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path4

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From clkdiv_3/count_16_s0
To clkdiv_3/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C11[1][A] clkdiv_3/count_16_s0/CLK
1.776 0.247 tC2Q RR 3 R12C11[1][A] clkdiv_3/count_16_s0/Q
1.778 0.002 tNET RR 1 R12C11[1][A] clkdiv_3/n46_s2/I2
2.053 0.276 tINS RF 1 R12C11[1][A] clkdiv_3/n46_s2/F
2.053 0.000 tNET FF 1 R12C11[1][A] clkdiv_3/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C11[1][A] clkdiv_3/count_16_s0/CLK
1.529 0.000 tHld 1 R12C11[1][A] clkdiv_3/count_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path5

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From clkdiv_2/count_17_s0
To clkdiv_2/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C11[0][A] clkdiv_2/count_17_s0/CLK
1.776 0.247 tC2Q RR 5 R7C11[0][A] clkdiv_2/count_17_s0/Q
1.778 0.002 tNET RR 1 R7C11[0][A] clkdiv_2/n45_s2/I2
2.053 0.276 tINS RF 1 R7C11[0][A] clkdiv_2/n45_s2/F
2.053 0.000 tNET FF 1 R7C11[0][A] clkdiv_2/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C11[0][A] clkdiv_2/count_17_s0/CLK
1.529 0.000 tHld 1 R7C11[0][A] clkdiv_2/count_17_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path6

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_5/count_7_s0
To clkdiv_5/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C10[1][A] clkdiv_5/count_7_s0/CLK
1.776 0.247 tC2Q RR 5 R7C10[1][A] clkdiv_5/count_7_s0/Q
1.778 0.003 tNET RR 1 R7C10[1][A] clkdiv_5/n55_s2/I2
2.054 0.276 tINS RF 1 R7C10[1][A] clkdiv_5/n55_s2/F
2.054 0.000 tNET FF 1 R7C10[1][A] clkdiv_5/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C10[1][A] clkdiv_5/count_7_s0/CLK
1.529 0.000 tHld 1 R7C10[1][A] clkdiv_5/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path7

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_5/count_16_s0
To clkdiv_5/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R6C8[0][A] clkdiv_5/count_16_s0/CLK
1.776 0.247 tC2Q RR 6 R6C8[0][A] clkdiv_5/count_16_s0/Q
1.778 0.003 tNET RR 1 R6C8[0][A] clkdiv_5/n46_s2/I3
2.054 0.276 tINS RF 1 R6C8[0][A] clkdiv_5/n46_s2/F
2.054 0.000 tNET FF 1 R6C8[0][A] clkdiv_5/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R6C8[0][A] clkdiv_5/count_16_s0/CLK
1.529 0.000 tHld 1 R6C8[0][A] clkdiv_5/count_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path8

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_4/count_7_s0
To clkdiv_4/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C7[0][A] clkdiv_4/count_7_s0/CLK
1.776 0.247 tC2Q RR 6 R9C7[0][A] clkdiv_4/count_7_s0/Q
1.778 0.003 tNET RR 1 R9C7[0][A] clkdiv_4/n55_s2/I1
2.054 0.276 tINS RF 1 R9C7[0][A] clkdiv_4/n55_s2/F
2.054 0.000 tNET FF 1 R9C7[0][A] clkdiv_4/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C7[0][A] clkdiv_4/count_7_s0/CLK
1.529 0.000 tHld 1 R9C7[0][A] clkdiv_4/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path9

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_4/count_11_s0
To clkdiv_4/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C10[1][A] clkdiv_4/count_11_s0/CLK
1.776 0.247 tC2Q RR 5 R8C10[1][A] clkdiv_4/count_11_s0/Q
1.778 0.003 tNET RR 1 R8C10[1][A] clkdiv_4/n51_s2/I2
2.054 0.276 tINS RF 1 R8C10[1][A] clkdiv_4/n51_s2/F
2.054 0.000 tNET FF 1 R8C10[1][A] clkdiv_4/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C10[1][A] clkdiv_4/count_11_s0/CLK
1.529 0.000 tHld 1 R8C10[1][A] clkdiv_4/count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path10

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_4/count_13_s0
To clkdiv_4/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C10[0][A] clkdiv_4/count_13_s0/CLK
1.776 0.247 tC2Q RR 5 R8C10[0][A] clkdiv_4/count_13_s0/Q
1.778 0.003 tNET RR 1 R8C10[0][A] clkdiv_4/n49_s2/I2
2.054 0.276 tINS RF 1 R8C10[0][A] clkdiv_4/n49_s2/F
2.054 0.000 tNET FF 1 R8C10[0][A] clkdiv_4/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C10[0][A] clkdiv_4/count_13_s0/CLK
1.529 0.000 tHld 1 R8C10[0][A] clkdiv_4/count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path11

Path Summary:

Slack 0.525
Data Arrival Time 1.297
Data Required Time 0.771
From leg4_1/inst1/adr_0_s0
To leg4_1/inst1/adr_0_s0
Launch Clk leg4_clk:[R]
Latch Clk leg4_clk:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 leg4_clk
0.000 0.000 tCL RR 17 R6C11[3][A] leg4_clk_s5/O
0.771 0.771 tNET RR 1 R8C6[0][A] leg4_1/inst1/adr_0_s0/CLK
1.018 0.247 tC2Q RR 31 R8C6[0][A] leg4_1/inst1/adr_0_s0/Q
1.021 0.003 tNET RR 1 R8C6[0][A] leg4_1/inst1/n15_s1/I1
1.297 0.276 tINS RF 1 R8C6[0][A] leg4_1/inst1/n15_s1/F
1.297 0.000 tNET FF 1 R8C6[0][A] leg4_1/inst1/adr_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 leg4_clk
0.000 0.000 tCL RR 17 R6C11[3][A] leg4_clk_s5/O
0.771 0.771 tNET RR 1 R8C6[0][A] leg4_1/inst1/adr_0_s0/CLK
0.771 0.000 tHld 1 R8C6[0][A] leg4_1/inst1/adr_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.771, 100.000%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.771, 100.000%

Path12

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_3/count_9_s0
To clkdiv_3/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C14[0][A] clkdiv_3/count_9_s0/CLK
1.776 0.247 tC2Q RR 6 R9C14[0][A] clkdiv_3/count_9_s0/Q
1.778 0.003 tNET RR 1 R9C14[0][A] clkdiv_3/n53_s2/I1
2.054 0.276 tINS RF 1 R9C14[0][A] clkdiv_3/n53_s2/F
2.054 0.000 tNET FF 1 R9C14[0][A] clkdiv_3/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C14[0][A] clkdiv_3/count_9_s0/CLK
1.529 0.000 tHld 1 R9C14[0][A] clkdiv_3/count_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path13

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_2/count_16_s0
To clkdiv_2/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[1][A] clkdiv_2/count_16_s0/CLK
1.776 0.247 tC2Q RR 6 R7C12[1][A] clkdiv_2/count_16_s0/Q
1.778 0.003 tNET RR 1 R7C12[1][A] clkdiv_2/n46_s2/I3
2.054 0.276 tINS RF 1 R7C12[1][A] clkdiv_2/n46_s2/F
2.054 0.000 tNET FF 1 R7C12[1][A] clkdiv_2/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[1][A] clkdiv_2/count_16_s0/CLK
1.529 0.000 tHld 1 R7C12[1][A] clkdiv_2/count_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path14

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_2/count_19_s0
To clkdiv_2/count_19_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C14[0][A] clkdiv_2/count_19_s0/CLK
1.776 0.247 tC2Q RR 5 R8C14[0][A] clkdiv_2/count_19_s0/Q
1.778 0.003 tNET RR 1 R8C14[0][A] clkdiv_2/n43_s2/I3
2.054 0.276 tINS RF 1 R8C14[0][A] clkdiv_2/n43_s2/F
2.054 0.000 tNET FF 1 R8C14[0][A] clkdiv_2/count_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C14[0][A] clkdiv_2/count_19_s0/CLK
1.529 0.000 tHld 1 R8C14[0][A] clkdiv_2/count_19_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path15

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_2/count_21_s0
To clkdiv_2/count_21_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C14[1][A] clkdiv_2/count_21_s0/CLK
1.776 0.247 tC2Q RR 4 R7C14[1][A] clkdiv_2/count_21_s0/Q
1.778 0.003 tNET RR 1 R7C14[1][A] clkdiv_2/n41_s2/I1
2.054 0.276 tINS RF 1 R7C14[1][A] clkdiv_2/n41_s2/F
2.054 0.000 tNET FF 1 R7C14[1][A] clkdiv_2/count_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C14[1][A] clkdiv_2/count_21_s0/CLK
1.529 0.000 tHld 1 R7C14[1][A] clkdiv_2/count_21_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path16

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_1/count_10_s0
To clkdiv_1/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R13C12[1][A] clkdiv_1/count_10_s0/CLK
1.776 0.247 tC2Q RR 3 R13C12[1][A] clkdiv_1/count_10_s0/Q
1.778 0.003 tNET RR 1 R13C12[1][A] clkdiv_1/n52_s2/I2
2.054 0.276 tINS RF 1 R13C12[1][A] clkdiv_1/n52_s2/F
2.054 0.000 tNET FF 1 R13C12[1][A] clkdiv_1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R13C12[1][A] clkdiv_1/count_10_s0/CLK
1.529 0.000 tHld 1 R13C12[1][A] clkdiv_1/count_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path17

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_5/count_0_s0
To clkdiv_5/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R6C10[0][A] clkdiv_5/count_0_s0/CLK
1.776 0.247 tC2Q RR 6 R6C10[0][A] clkdiv_5/count_0_s0/Q
1.779 0.003 tNET RR 1 R6C10[0][A] clkdiv_5/n62_s2/I1
2.055 0.276 tINS RF 1 R6C10[0][A] clkdiv_5/n62_s2/F
2.055 0.000 tNET FF 1 R6C10[0][A] clkdiv_5/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R6C10[0][A] clkdiv_5/count_0_s0/CLK
1.529 0.000 tHld 1 R6C10[0][A] clkdiv_5/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path18

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_4/count_5_s0
To clkdiv_4/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C10[1][A] clkdiv_4/count_5_s0/CLK
1.776 0.247 tC2Q RR 5 R9C10[1][A] clkdiv_4/count_5_s0/Q
1.779 0.003 tNET RR 1 R9C10[1][A] clkdiv_4/n57_s2/I2
2.055 0.276 tINS RF 1 R9C10[1][A] clkdiv_4/n57_s2/F
2.055 0.000 tNET FF 1 R9C10[1][A] clkdiv_4/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C10[1][A] clkdiv_4/count_5_s0/CLK
1.529 0.000 tHld 1 R9C10[1][A] clkdiv_4/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path19

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_3/count_4_s0
To clkdiv_3/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C11[0][A] clkdiv_3/count_4_s0/CLK
1.776 0.247 tC2Q RR 6 R12C11[0][A] clkdiv_3/count_4_s0/Q
1.779 0.003 tNET RR 1 R12C11[0][A] clkdiv_3/n58_s2/I1
2.055 0.276 tINS RF 1 R12C11[0][A] clkdiv_3/n58_s2/F
2.055 0.000 tNET FF 1 R12C11[0][A] clkdiv_3/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C11[0][A] clkdiv_3/count_4_s0/CLK
1.529 0.000 tHld 1 R12C11[0][A] clkdiv_3/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path20

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_3/count_19_s0
To clkdiv_3/count_19_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[0][A] clkdiv_3/count_19_s0/CLK
1.776 0.247 tC2Q RR 6 R9C11[0][A] clkdiv_3/count_19_s0/Q
1.779 0.003 tNET RR 1 R9C11[0][A] clkdiv_3/n43_s2/I1
2.055 0.276 tINS RF 1 R9C11[0][A] clkdiv_3/n43_s2/F
2.055 0.000 tNET FF 1 R9C11[0][A] clkdiv_3/count_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[0][A] clkdiv_3/count_19_s0/CLK
1.529 0.000 tHld 1 R9C11[0][A] clkdiv_3/count_19_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path21

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_3/count_21_s0
To clkdiv_3/count_21_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C12[1][A] clkdiv_3/count_21_s0/CLK
1.776 0.247 tC2Q RR 6 R9C12[1][A] clkdiv_3/count_21_s0/Q
1.779 0.003 tNET RR 1 R9C12[1][A] clkdiv_3/n41_s2/I1
2.055 0.276 tINS RF 1 R9C12[1][A] clkdiv_3/n41_s2/F
2.055 0.000 tNET FF 1 R9C12[1][A] clkdiv_3/count_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C12[1][A] clkdiv_3/count_21_s0/CLK
1.529 0.000 tHld 1 R9C12[1][A] clkdiv_3/count_21_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path22

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_2/count_20_s0
To clkdiv_2/count_20_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C14[0][A] clkdiv_2/count_20_s0/CLK
1.776 0.247 tC2Q RR 6 R7C14[0][A] clkdiv_2/count_20_s0/Q
1.779 0.003 tNET RR 1 R7C14[0][A] clkdiv_2/n42_s5/I2
2.055 0.276 tINS RF 1 R7C14[0][A] clkdiv_2/n42_s5/F
2.055 0.000 tNET FF 1 R7C14[0][A] clkdiv_2/count_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C14[0][A] clkdiv_2/count_20_s0/CLK
1.529 0.000 tHld 1 R7C14[0][A] clkdiv_2/count_20_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path23

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_1/count_4_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R14C11[1][A] clkdiv_1/count_4_s0/CLK
1.776 0.247 tC2Q RR 8 R14C11[1][A] clkdiv_1/count_4_s0/Q
1.779 0.003 tNET RR 1 R14C11[1][A] clkdiv_1/n58_s2/I1
2.055 0.276 tINS RF 1 R14C11[1][A] clkdiv_1/n58_s2/F
2.055 0.000 tNET FF 1 R14C11[1][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R14C11[1][A] clkdiv_1/count_4_s0/CLK
1.529 0.000 tHld 1 R14C11[1][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path24

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_1/count_11_s0
To clkdiv_1/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R14C13[0][A] clkdiv_1/count_11_s0/CLK
1.776 0.247 tC2Q RR 6 R14C13[0][A] clkdiv_1/count_11_s0/Q
1.779 0.003 tNET RR 1 R14C13[0][A] clkdiv_1/n51_s2/I1
2.055 0.276 tINS RF 1 R14C13[0][A] clkdiv_1/n51_s2/F
2.055 0.000 tNET FF 1 R14C13[0][A] clkdiv_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R14C13[0][A] clkdiv_1/count_11_s0/CLK
1.529 0.000 tHld 1 R14C13[0][A] clkdiv_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path25

Path Summary:

Slack 0.527
Data Arrival Time 2.056
Data Required Time 1.529
From clkdiv_5/count_5_s0
To clkdiv_5/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C8[0][A] clkdiv_5/count_5_s0/CLK
1.776 0.247 tC2Q RR 6 R7C8[0][A] clkdiv_5/count_5_s0/Q
1.780 0.004 tNET RR 1 R7C8[0][A] clkdiv_5/n57_s2/I3
2.056 0.276 tINS RF 1 R7C8[0][A] clkdiv_5/n57_s2/F
2.056 0.000 tNET FF 1 R7C8[0][A] clkdiv_5/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 102 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C8[0][A] clkdiv_5/count_5_s0/CLK
1.529 0.000 tHld 1 R7C8[0][A] clkdiv_5/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_16_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_16_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_16_s0/CLK

MPW2

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_14_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_14_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_14_s0/CLK

MPW3

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_10_s0/CLK

MPW4

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_2_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_2_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_2_s0/CLK

MPW5

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_2/count_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_2/count_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_2/count_9_s0/CLK

MPW6

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_3/count_3_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_3/count_3_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_3/count_3_s0/CLK

MPW7

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_3/count_4_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_3/count_4_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_3/count_4_s0/CLK

MPW8

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_2/count_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_2/count_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_2/count_10_s0/CLK

MPW9

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_3/count_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_3/count_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_3/count_5_s0/CLK

MPW10

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_3/count_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_3/count_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_3/count_6_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
102 clk_d 29.818 0.195
31 address[0] 999989.312 1.098
29 address[2] 999989.500 1.602
27 address[1] 999989.438 1.484
26 address[3] 999990.688 1.353
25 n62_8 29.818 1.001
21 n62_20 33.382 0.988
19 n62_9 30.941 1.002
18 col[1] 6249988.000 1.002
18 n62_7 31.733 0.641

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R12C11 79.17%
R14C11 73.61%
R8C12 72.22%
R6C10 72.22%
R8C10 70.83%
R12C12 66.67%
R9C14 65.28%
R9C10 65.28%
R7C11 65.28%
R13C7 63.89%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk1khz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 27000 [get_nets {clk1khz}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk400hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 67500 [get_nets {clk400hz}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk1hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 2700000 [get_nets {clk1hz}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk160hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 168750 [get_nets {clk160hz}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk10hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 2700000 [get_nets {clk10hz}]
TC_GENERATED_CLOCK Actived create_generated_clock -name leg4_clk -source [get_nets {clk1khz}] -master_clock clk1khz -divide_by 1 [get_nets {leg4_clk}]
TC_CLOCK_GROUP Actived set_clock_groups -exclusive -group [get_clocks {clk1khz}] -group [get_clocks {clk10hz}] -group [get_clocks {clk1hz}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {clk160hz}] -group [get_clocks {leg4_clk}]