Timing Messages

Report Title Timing Analysis Report
Design File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\impl\gwsynthesis\organ.vg
Physical Constraints File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\organ.cst
Timing Constraint File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\organ.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Thu Dec 19 16:31:33 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.71V 85C C7/I6
Hold Delay Model Fast 3.6V 0C C7/I6
Numbers of Paths Analyzed 399
Numbers of Endpoints Analyzed 210
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk27mhz Base 37.037 27.000 0.000 18.518 clk
2 clk50hz Generated 19999980.000 0.000 0.000 9999990.000 clk clk27mhz clk50hz

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk27mhz 27.000(MHz) 160.111(MHz) 6 TOP
2 clk50hz 0.000(MHz) 250.000(MHz) 2 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk27mhz Setup 0.000 0
clk27mhz Hold 0.000 0
clk50hz Setup 0.000 0
clk50hz Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 30.791 inst5/count_1_s0/Q inst5/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.949
2 30.791 inst5/count_1_s0/Q inst5/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.949
3 30.795 inst5/count_1_s0/Q inst5/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.946
4 30.922 inst5/count_1_s0/Q inst5/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.819
5 30.942 inst5/count_1_s0/Q inst5/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.799
6 30.950 inst5/count_1_s0/Q inst5/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.790
7 30.950 inst5/count_1_s0/Q inst5/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.790
8 31.028 inst5/count_1_s0/Q inst5/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.713
9 31.048 inst5/count_1_s0/Q inst5/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.693
10 31.048 inst5/count_1_s0/Q inst5/count_8_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.693
11 31.067 inst5/count_1_s0/Q inst5/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.674
12 31.067 inst5/count_1_s0/Q inst5/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.674
13 31.067 inst5/count_1_s0/Q inst5/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.674
14 31.070 inst5/count_1_s0/Q inst5/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.670
15 31.079 inst5/count_1_s0/Q inst5/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.662
16 31.100 inst5/count_1_s0/Q inst5/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.640
17 31.103 inst5/count_1_s0/Q inst5/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.637
18 31.133 inst5/count_0_s0/Q inst5/clk_out_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.608
19 31.301 clkdiv_1/count_0_s0/Q clkdiv_1/count_19_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.439
20 31.395 inst5/count_1_s0/Q inst5/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 5.345
21 31.869 clkdiv_1/count_0_s0/Q clkdiv_1/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.871
22 31.906 clkdiv_1/count_0_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.835
23 31.906 clkdiv_1/count_0_s0/Q clkdiv_1/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.835
24 31.909 clkdiv_1/count_0_s0/Q clkdiv_1/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.831
25 31.945 clkdiv_1/count_5_s0/Q clkdiv_1/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 4.796

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.524 inst5/count_15_s0/Q inst5/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.524
2 0.525 clkdiv_1/count_0_s0/Q clkdiv_1/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
3 0.525 clkdiv_1/count_14_s0/Q clkdiv_1/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
4 0.525 clkdiv_1/count_15_s0/Q clkdiv_1/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
5 0.525 clkdiv_1/count_17_s0/Q clkdiv_1/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.525
6 0.526 inst5/count_9_s0/Q inst5/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
7 0.526 inst5/count_12_s0/Q inst5/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
8 0.526 inst5/count_14_s0/Q inst5/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
9 0.526 clkdiv_1/count_13_s0/Q clkdiv_1/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.526
10 0.527 clkdiv_1/count_4_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.527
11 0.527 clkdiv_1/count_5_s0/Q clkdiv_1/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.527
12 0.527 inst2/index_0_s0/Q inst2/index_0_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.527
13 0.527 inst2/index_2_s0/Q inst2/index_2_s0/D clk50hz:[R] clk50hz:[R] 0.000 0.000 0.527
14 0.662 inst5/count_11_s0/Q inst5/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.662
15 0.662 clkdiv_1/count_7_s0/Q clkdiv_1/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.662
16 0.662 inst5/count_5_s0/Q inst5/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.662
17 0.662 inst5/count_7_s0/Q inst5/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.662
18 0.663 inst5/count_2_s0/Q inst5/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.663
19 0.711 clkdiv_1/count_19_s0/Q clkdiv_1/clk_out_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.711
20 0.714 inst5/count_7_s0/Q inst5/count_8_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.714
21 0.722 inst5/count_1_s0/Q inst5/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.722
22 0.786 inst5/count_6_s0/Q inst5/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.786
23 0.786 clkdiv_1/count_2_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.786
24 0.787 inst5/count_3_s0/Q inst5/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.787
25 0.787 inst5/count_13_s0/Q inst5/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.787

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_19_s0
2 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_17_s0
3 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_13_s0
4 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_5_s0
5 16.613 17.539 0.926 Low Pulse Width clk27mhz inst5/count_8_s0
6 16.613 17.539 0.926 Low Pulse Width clk27mhz inst5/count_9_s0
7 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_6_s0
8 16.613 17.539 0.926 Low Pulse Width clk27mhz inst5/count_10_s0
9 16.613 17.539 0.926 Low Pulse Width clk27mhz inst5/count_11_s0
10 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_14_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 30.791
Data Arrival Time 8.218
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.453 0.628 tNET FF 1 R11C12[1][A] inst5/n50_s2/I3
8.218 0.765 tINS FF 1 R11C12[1][A] inst5/n50_s2/F
8.218 0.000 tNET FF 1 R11C12[1][A] inst5/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C12[1][A] inst5/count_12_s0/CLK
39.009 -0.296 tSu 1 R11C12[1][A] inst5/count_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.828, 47.542%; route: 2.781, 46.749%; tC2Q: 0.340, 5.709%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path2

Path Summary:

Slack 30.791
Data Arrival Time 8.218
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.453 0.628 tNET FF 1 R11C12[1][B] inst5/n45_s2/I1
8.218 0.765 tINS FF 1 R11C12[1][B] inst5/n45_s2/F
8.218 0.000 tNET FF 1 R11C12[1][B] inst5/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C12[1][B] inst5/count_17_s0/CLK
39.009 -0.296 tSu 1 R11C12[1][B] inst5/count_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.828, 47.542%; route: 2.781, 46.749%; tC2Q: 0.340, 5.709%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path3

Path Summary:

Slack 30.795
Data Arrival Time 8.215
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.450 0.624 tNET FF 1 R13C12[3][A] inst5/n46_s2/I3
8.215 0.765 tINS FF 1 R13C12[3][A] inst5/n46_s2/F
8.215 0.000 tNET FF 1 R13C12[3][A] inst5/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R13C12[3][A] inst5/count_16_s0/CLK
39.009 -0.296 tSu 1 R13C12[3][A] inst5/count_16_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.828, 47.569%; route: 2.778, 46.719%; tC2Q: 0.340, 5.712%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path4

Path Summary:

Slack 30.922
Data Arrival Time 8.088
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.478 0.653 tNET FF 1 R11C14[1][B] inst5/n59_s2/I3
8.088 0.609 tINS FF 1 R11C14[1][B] inst5/n59_s2/F
8.088 0.000 tNET FF 1 R11C14[1][B] inst5/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C14[1][B] inst5/count_3_s0/CLK
39.009 -0.296 tSu 1 R11C14[1][B] inst5/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.673, 45.934%; route: 2.806, 48.230%; tC2Q: 0.340, 5.837%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path5

Path Summary:

Slack 30.942
Data Arrival Time 8.067
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.458 0.633 tNET FF 1 R13C11[0][A] inst5/n47_s2/I3
8.067 0.609 tINS FF 1 R13C11[0][A] inst5/n47_s2/F
8.067 0.000 tNET FF 1 R13C11[0][A] inst5/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R13C11[0][A] inst5/count_15_s0/CLK
39.009 -0.296 tSu 1 R13C11[0][A] inst5/count_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.673, 46.093%; route: 2.786, 48.050%; tC2Q: 0.340, 5.857%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path6

Path Summary:

Slack 30.950
Data Arrival Time 8.059
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.450 0.624 tNET FF 1 R11C12[2][B] inst5/n52_s2/I2
8.059 0.609 tINS FF 1 R11C12[2][B] inst5/n52_s2/F
8.059 0.000 tNET FF 1 R11C12[2][B] inst5/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C12[2][B] inst5/count_10_s0/CLK
39.009 -0.296 tSu 1 R11C12[2][B] inst5/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.673, 46.160%; route: 2.778, 47.975%; tC2Q: 0.340, 5.865%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path7

Path Summary:

Slack 30.950
Data Arrival Time 8.059
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.450 0.624 tNET FF 1 R11C12[0][B] inst5/n49_s2/I3
8.059 0.609 tINS FF 1 R11C12[0][B] inst5/n49_s2/F
8.059 0.000 tNET FF 1 R11C12[0][B] inst5/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C12[0][B] inst5/count_13_s0/CLK
39.009 -0.296 tSu 1 R11C12[0][B] inst5/count_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.673, 46.160%; route: 2.778, 47.975%; tC2Q: 0.340, 5.865%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path8

Path Summary:

Slack 31.028
Data Arrival Time 7.982
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.217 0.392 tNET FF 1 R12C11[0][A] inst5/n48_s2/I2
7.982 0.765 tINS FF 1 R12C11[0][A] inst5/n48_s2/F
7.982 0.000 tNET FF 1 R12C11[0][A] inst5/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C11[0][A] inst5/count_14_s0/CLK
39.009 -0.296 tSu 1 R12C11[0][A] inst5/count_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.828, 49.508%; route: 2.545, 44.547%; tC2Q: 0.340, 5.945%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path9

Path Summary:

Slack 31.048
Data Arrival Time 7.962
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.821 0.760 tINS RR 18 R12C13[3][B] inst5/n62_s5/F
7.147 0.326 tNET RR 1 R11C13[2][A] inst5/n55_s2/I2
7.962 0.814 tINS RF 1 R11C13[2][A] inst5/n55_s2/F
7.962 0.000 tNET FF 1 R11C13[2][A] inst5/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C13[2][A] inst5/count_7_s0/CLK
39.009 -0.296 tSu 1 R11C13[2][A] inst5/count_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.874, 50.477%; route: 2.480, 43.558%; tC2Q: 0.340, 5.966%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path10

Path Summary:

Slack 31.048
Data Arrival Time 7.962
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_8_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.821 0.760 tINS RR 18 R12C13[3][B] inst5/n62_s5/F
7.147 0.326 tNET RR 1 R11C13[2][B] inst5/n54_s2/I3
7.962 0.814 tINS RF 1 R11C13[2][B] inst5/n54_s2/F
7.962 0.000 tNET FF 1 R11C13[2][B] inst5/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C13[2][B] inst5/count_8_s0/CLK
39.009 -0.296 tSu 1 R11C13[2][B] inst5/count_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.874, 50.477%; route: 2.480, 43.558%; tC2Q: 0.340, 5.966%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path11

Path Summary:

Slack 31.067
Data Arrival Time 7.942
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.478 0.653 tNET FF 1 R11C14[2][A] inst5/n60_s4/I3
7.942 0.464 tINS FF 1 R11C14[2][A] inst5/n60_s4/F
7.942 0.000 tNET FF 1 R11C14[2][A] inst5/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C14[2][A] inst5/count_2_s0/CLK
39.009 -0.296 tSu 1 R11C14[2][A] inst5/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.528, 44.550%; route: 2.806, 49.464%; tC2Q: 0.340, 5.986%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path12

Path Summary:

Slack 31.067
Data Arrival Time 7.942
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.478 0.653 tNET FF 1 R13C14[3][A] inst5/n58_s2/I2
7.942 0.464 tINS FF 1 R13C14[3][A] inst5/n58_s2/F
7.942 0.000 tNET FF 1 R13C14[3][A] inst5/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R13C14[3][A] inst5/count_4_s0/CLK
39.009 -0.296 tSu 1 R13C14[3][A] inst5/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.528, 44.550%; route: 2.806, 49.464%; tC2Q: 0.340, 5.986%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path13

Path Summary:

Slack 31.067
Data Arrival Time 7.942
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.478 0.653 tNET FF 1 R13C14[2][A] inst5/n57_s2/I3
7.942 0.464 tINS FF 1 R13C14[2][A] inst5/n57_s2/F
7.942 0.000 tNET FF 1 R13C14[2][A] inst5/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R13C14[2][A] inst5/count_5_s0/CLK
39.009 -0.296 tSu 1 R13C14[2][A] inst5/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.528, 44.550%; route: 2.806, 49.464%; tC2Q: 0.340, 5.986%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path14

Path Summary:

Slack 31.070
Data Arrival Time 7.939
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.475 0.650 tNET FF 1 R11C14[0][B] inst5/n56_s2/I3
7.939 0.464 tINS FF 1 R11C14[0][B] inst5/n56_s2/F
7.939 0.000 tNET FF 1 R11C14[0][B] inst5/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C14[0][B] inst5/count_6_s0/CLK
39.009 -0.296 tSu 1 R11C14[0][B] inst5/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.528, 44.576%; route: 2.803, 49.434%; tC2Q: 0.340, 5.990%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path15

Path Summary:

Slack 31.079
Data Arrival Time 7.931
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.825 0.765 tINS RF 18 R12C13[3][B] inst5/n62_s5/F
7.467 0.641 tNET FF 1 R11C12[2][A] inst5/n51_s2/I3
7.931 0.464 tINS FF 1 R11C12[2][A] inst5/n51_s2/F
7.931 0.000 tNET FF 1 R11C12[2][A] inst5/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C12[2][A] inst5/count_11_s0/CLK
39.009 -0.296 tSu 1 R11C12[2][A] inst5/count_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.528, 44.642%; route: 2.795, 49.359%; tC2Q: 0.340, 5.999%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path16

Path Summary:

Slack 31.100
Data Arrival Time 7.909
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.821 0.760 tINS RR 18 R12C13[3][B] inst5/n62_s5/F
7.144 0.323 tNET RR 1 R13C13[3][A] inst5/n61_s2/I2
7.909 0.765 tINS RF 1 R13C13[3][A] inst5/n61_s2/F
7.909 0.000 tNET FF 1 R13C13[3][A] inst5/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
39.009 -0.296 tSu 1 R13C13[3][A] inst5/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.824, 50.067%; route: 2.477, 43.912%; tC2Q: 0.340, 6.021%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path17

Path Summary:

Slack 31.103
Data Arrival Time 7.906
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.821 0.760 tINS RR 18 R12C13[3][B] inst5/n62_s5/F
7.141 0.320 tNET RR 1 R11C13[0][A] inst5/n53_s2/I3
7.906 0.765 tINS RF 1 R11C13[0][A] inst5/n53_s2/F
7.906 0.000 tNET FF 1 R11C13[0][A] inst5/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C13[0][A] inst5/count_9_s0/CLK
39.009 -0.296 tSu 1 R11C13[0][A] inst5/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.824, 50.093%; route: 2.474, 43.882%; tC2Q: 0.340, 6.024%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path18

Path Summary:

Slack 31.133
Data Arrival Time 7.877
Data Required Time 39.009
From inst5/count_0_s0
To inst5/clk_out_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C14[3][A] inst5/count_0_s0/CLK
2.608 0.340 tC2Q RF 7 R12C14[3][A] inst5/count_0_s0/Q
4.185 1.576 tNET FF 2 R13C12[0][A] inst5/n64_s52/I1
4.592 0.408 tINS FR 1 R13C12[0][A] inst5/n64_s52/COUT
4.592 0.000 tNET RR 2 R13C12[0][B] inst5/n64_s53/CIN
4.635 0.042 tINS RF 1 R13C12[0][B] inst5/n64_s53/COUT
4.635 0.000 tNET FF 2 R13C12[1][A] inst5/n64_s54/CIN
4.677 0.042 tINS FF 1 R13C12[1][A] inst5/n64_s54/COUT
4.677 0.000 tNET FF 2 R13C12[1][B] inst5/n64_s55/CIN
4.719 0.042 tINS FF 1 R13C12[1][B] inst5/n64_s55/COUT
4.719 0.000 tNET FF 2 R13C12[2][A] inst5/n64_s56/CIN
4.761 0.042 tINS FF 1 R13C12[2][A] inst5/n64_s56/COUT
4.761 0.000 tNET FF 2 R13C12[2][B] inst5/n64_s57/CIN
4.803 0.042 tINS FF 1 R13C12[2][B] inst5/n64_s57/COUT
4.803 0.000 tNET FF 2 R13C13[0][A] inst5/n64_s58/CIN
4.846 0.042 tINS FF 1 R13C13[0][A] inst5/n64_s58/COUT
4.846 0.000 tNET FF 2 R13C13[0][B] inst5/n64_s59/CIN
4.888 0.042 tINS FF 1 R13C13[0][B] inst5/n64_s59/COUT
4.888 0.000 tNET FF 2 R13C13[1][A] inst5/n64_s60/CIN
4.930 0.042 tINS FF 1 R13C13[1][A] inst5/n64_s60/COUT
4.930 0.000 tNET FF 2 R13C13[1][B] inst5/n64_s61/CIN
4.972 0.042 tINS FF 1 R13C13[1][B] inst5/n64_s61/COUT
4.972 0.000 tNET FF 2 R13C13[2][A] inst5/n64_s62/CIN
5.015 0.042 tINS FF 1 R13C13[2][A] inst5/n64_s62/COUT
5.015 0.000 tNET FF 2 R13C13[2][B] inst5/n64_s63/CIN
5.057 0.042 tINS FF 1 R13C13[2][B] inst5/n64_s63/COUT
5.057 0.000 tNET FF 2 R13C14[0][A] inst5/n64_s64/CIN
5.099 0.042 tINS FF 1 R13C14[0][A] inst5/n64_s64/COUT
5.099 0.000 tNET FF 2 R13C14[0][B] inst5/n64_s65/CIN
5.141 0.042 tINS FF 1 R13C14[0][B] inst5/n64_s65/COUT
5.141 0.000 tNET FF 2 R13C14[1][A] inst5/n64_s66/CIN
5.184 0.042 tINS FF 1 R13C14[1][A] inst5/n64_s66/COUT
6.197 1.013 tNET FF 1 R12C13[3][A] inst5/n64_s83/I3
6.957 0.760 tINS FR 1 R12C13[3][A] inst5/n64_s83/F
7.267 0.310 tNET RR 1 R11C13[1][A] inst5/n64_s82/I0
7.877 0.609 tINS RF 1 R11C13[1][A] inst5/n64_s82/F
7.877 0.000 tNET FF 1 R11C13[1][A] inst5/clk_out_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C13[1][A] inst5/clk_out_s0/CLK
39.009 -0.296 tSu 1 R11C13[1][A] inst5/clk_out_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.368, 42.231%; route: 2.900, 51.713%; tC2Q: 0.340, 6.056%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path19

Path Summary:

Slack 31.301
Data Arrival Time 7.708
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/count_19_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R9C11[0][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R9C11[0][A] clkdiv_1/count_0_s0/Q
3.218 0.609 tNET FF 1 R8C10[1][A] clkdiv_1/n58_s3/I1
4.004 0.786 tINS FR 8 R8C10[1][A] clkdiv_1/n58_s3/F
4.325 0.321 tNET RR 1 R9C10[3][A] clkdiv_1/n49_s3/I0
5.089 0.765 tINS RF 7 R9C10[3][A] clkdiv_1/n49_s3/F
5.834 0.744 tNET FF 1 R7C12[3][B] clkdiv_1/n43_s10/I1
6.298 0.464 tINS FF 1 R7C12[3][B] clkdiv_1/n43_s10/F
6.894 0.596 tNET FF 1 R9C11[0][B] clkdiv_1/n43_s2/I1
7.708 0.814 tINS FF 1 R9C11[0][B] clkdiv_1/n43_s2/F
7.708 0.000 tNET FF 1 R9C11[0][B] clkdiv_1/count_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C11[0][B] clkdiv_1/count_19_s0/CLK
39.009 -0.296 tSu 1 R9C11[0][B] clkdiv_1/count_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.829, 52.013%; route: 2.270, 41.743%; tC2Q: 0.340, 6.244%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path20

Path Summary:

Slack 31.395
Data Arrival Time 7.614
Data Required Time 39.009
From inst5/count_1_s0
To inst5/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
2.608 0.340 tC2Q RF 6 R13C13[3][A] inst5/count_1_s0/Q
4.060 1.452 tNET FF 2 R12C12[1][A] inst5/tc_s62/I0
4.770 0.710 tINS FF 1 R12C12[1][A] inst5/tc_s62/COUT
4.770 0.000 tNET FF 2 R12C12[1][B] inst5/tc_s63/CIN
4.812 0.042 tINS FF 1 R12C12[1][B] inst5/tc_s63/COUT
4.812 0.000 tNET FF 2 R12C12[2][A] inst5/tc_s64/CIN
4.854 0.042 tINS FF 1 R12C12[2][A] inst5/tc_s64/COUT
4.854 0.000 tNET FF 2 R12C12[2][B] inst5/tc_s65/CIN
4.897 0.042 tINS FF 1 R12C12[2][B] inst5/tc_s65/COUT
4.897 0.000 tNET FF 2 R12C13[0][A] inst5/tc_s66/CIN
4.939 0.042 tINS FF 1 R12C13[0][A] inst5/tc_s66/COUT
4.939 0.000 tNET FF 2 R12C13[0][B] inst5/tc_s67/CIN
4.981 0.042 tINS FF 1 R12C13[0][B] inst5/tc_s67/COUT
4.981 0.000 tNET FF 2 R12C13[1][A] inst5/tc_s68/CIN
5.023 0.042 tINS FF 1 R12C13[1][A] inst5/tc_s68/COUT
5.023 0.000 tNET FF 2 R12C13[1][B] inst5/tc_s69/CIN
5.066 0.042 tINS FF 1 R12C13[1][B] inst5/tc_s69/COUT
5.066 0.000 tNET FF 2 R12C13[2][A] inst5/tc_s70/CIN
5.108 0.042 tINS FF 1 R12C13[2][A] inst5/tc_s70/COUT
5.108 0.000 tNET FF 2 R12C13[2][B] inst5/tc_s71/CIN
5.150 0.042 tINS FF 1 R12C13[2][B] inst5/tc_s71/COUT
5.150 0.000 tNET FF 2 R12C14[0][A] inst5/tc_s72/CIN
5.192 0.042 tINS FF 1 R12C14[0][A] inst5/tc_s72/COUT
5.192 0.000 tNET FF 2 R12C14[0][B] inst5/tc_s73/CIN
5.235 0.042 tINS FF 1 R12C14[0][B] inst5/tc_s73/COUT
5.235 0.000 tNET FF 2 R12C14[1][A] inst5/tc_s74/CIN
5.277 0.042 tINS FF 1 R12C14[1][A] inst5/tc_s74/COUT
5.277 0.000 tNET FF 2 R12C14[1][B] inst5/tc_s75/CIN
5.319 0.042 tINS FF 1 R12C14[1][B] inst5/tc_s75/COUT
5.319 0.000 tNET FF 2 R12C14[2][A] inst5/tc_s76/CIN
5.359 0.040 tINS FR 1 R12C14[2][A] inst5/tc_s76/COUT
6.061 0.702 tNET RR 1 R12C13[3][B] inst5/n62_s5/I2
6.821 0.760 tINS RR 18 R12C13[3][B] inst5/n62_s5/F
7.150 0.329 tNET RR 1 R12C14[3][A] inst5/n62_s2/I1
7.614 0.464 tINS RF 1 R12C14[3][A] inst5/n62_s2/F
7.614 0.000 tNET FF 1 R12C14[3][A] inst5/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C14[3][A] inst5/count_0_s0/CLK
39.009 -0.296 tSu 1 R12C14[3][A] inst5/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 6
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.523, 47.202%; route: 2.483, 46.445%; tC2Q: 0.340, 6.354%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path21

Path Summary:

Slack 31.869
Data Arrival Time 7.140
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R9C11[0][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R9C11[0][A] clkdiv_1/count_0_s0/Q
3.218 0.609 tNET FF 1 R8C10[1][A] clkdiv_1/n58_s3/I1
4.032 0.814 tINS FF 8 R8C10[1][A] clkdiv_1/n58_s3/F
4.416 0.383 tNET FF 1 R7C10[1][B] clkdiv_1/n62_s7/I1
4.879 0.464 tINS FF 1 R7C10[1][B] clkdiv_1/n62_s7/F
4.884 0.004 tNET FF 1 R7C10[3][A] clkdiv_1/n62_s4/I1
5.698 0.814 tINS FF 15 R7C10[3][A] clkdiv_1/n62_s4/F
6.326 0.628 tNET FF 1 R9C10[1][A] clkdiv_1/n49_s2/I0
7.140 0.814 tINS FF 1 R9C10[1][A] clkdiv_1/n49_s2/F
7.140 0.000 tNET FF 1 R9C10[1][A] clkdiv_1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C10[1][A] clkdiv_1/count_13_s0/CLK
39.009 -0.296 tSu 1 R9C10[1][A] clkdiv_1/count_13_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.907, 59.674%; route: 1.625, 33.355%; tC2Q: 0.340, 6.972%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path22

Path Summary:

Slack 31.906
Data Arrival Time 7.103
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R9C11[0][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R9C11[0][A] clkdiv_1/count_0_s0/Q
3.218 0.609 tNET FF 1 R8C10[1][A] clkdiv_1/n58_s3/I1
4.032 0.814 tINS FF 8 R8C10[1][A] clkdiv_1/n58_s3/F
4.416 0.383 tNET FF 1 R7C10[1][B] clkdiv_1/n62_s7/I1
4.879 0.464 tINS FF 1 R7C10[1][B] clkdiv_1/n62_s7/F
4.884 0.004 tNET FF 1 R7C10[3][A] clkdiv_1/n62_s4/I1
5.698 0.814 tINS FF 15 R7C10[3][A] clkdiv_1/n62_s4/F
6.339 0.641 tNET FF 1 R8C12[0][B] clkdiv_1/n60_s2/I0
7.103 0.765 tINS FF 1 R8C12[0][B] clkdiv_1/n60_s2/F
7.103 0.000 tNET FF 1 R8C12[0][B] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C12[0][B] clkdiv_1/count_2_s0/CLK
39.009 -0.296 tSu 1 R8C12[0][B] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.857, 59.100%; route: 1.638, 33.875%; tC2Q: 0.340, 7.025%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path23

Path Summary:

Slack 31.906
Data Arrival Time 7.103
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R9C11[0][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R9C11[0][A] clkdiv_1/count_0_s0/Q
3.218 0.609 tNET FF 1 R8C10[1][A] clkdiv_1/n58_s3/I1
4.032 0.814 tINS FF 8 R8C10[1][A] clkdiv_1/n58_s3/F
4.416 0.383 tNET FF 1 R7C10[1][B] clkdiv_1/n62_s7/I1
4.879 0.464 tINS FF 1 R7C10[1][B] clkdiv_1/n62_s7/F
4.884 0.004 tNET FF 1 R7C10[3][A] clkdiv_1/n62_s4/I1
5.698 0.814 tINS FF 15 R7C10[3][A] clkdiv_1/n62_s4/F
6.339 0.641 tNET FF 1 R8C12[1][A] clkdiv_1/n57_s2/I0
7.103 0.765 tINS FF 1 R8C12[1][A] clkdiv_1/n57_s2/F
7.103 0.000 tNET FF 1 R8C12[1][A] clkdiv_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C12[1][A] clkdiv_1/count_5_s0/CLK
39.009 -0.296 tSu 1 R8C12[1][A] clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.857, 59.100%; route: 1.638, 33.875%; tC2Q: 0.340, 7.025%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path24

Path Summary:

Slack 31.909
Data Arrival Time 7.100
Data Required Time 39.009
From clkdiv_1/count_0_s0
To clkdiv_1/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R9C11[0][A] clkdiv_1/count_0_s0/CLK
2.608 0.340 tC2Q RF 5 R9C11[0][A] clkdiv_1/count_0_s0/Q
3.218 0.609 tNET FF 1 R8C10[1][A] clkdiv_1/n58_s3/I1
4.032 0.814 tINS FF 8 R8C10[1][A] clkdiv_1/n58_s3/F
4.416 0.383 tNET FF 1 R7C10[1][B] clkdiv_1/n62_s7/I1
4.879 0.464 tINS FF 1 R7C10[1][B] clkdiv_1/n62_s7/F
4.884 0.004 tNET FF 1 R7C10[3][A] clkdiv_1/n62_s4/I1
5.698 0.814 tINS FF 15 R7C10[3][A] clkdiv_1/n62_s4/F
6.335 0.637 tNET FF 1 R8C11[3][A] clkdiv_1/n53_s2/I0
7.100 0.765 tINS FF 1 R8C11[3][A] clkdiv_1/n53_s2/F
7.100 0.000 tNET FF 1 R8C11[3][A] clkdiv_1/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C11[3][A] clkdiv_1/count_9_s0/CLK
39.009 -0.296 tSu 1 R8C11[3][A] clkdiv_1/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.857, 59.141%; route: 1.634, 33.829%; tC2Q: 0.340, 7.030%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path25

Path Summary:

Slack 31.945
Data Arrival Time 7.064
Data Required Time 39.009
From clkdiv_1/count_5_s0
To clkdiv_1/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R8C12[1][A] clkdiv_1/count_5_s0/CLK
2.608 0.340 tC2Q RF 6 R8C12[1][A] clkdiv_1/count_5_s0/Q
3.219 0.611 tNET FF 1 R8C10[3][B] clkdiv_1/n55_s4/I1
4.005 0.786 tINS FR 2 R8C10[3][B] clkdiv_1/n55_s4/F
4.318 0.313 tNET RR 1 R9C10[0][B] clkdiv_1/n53_s5/I3
5.083 0.765 tINS RF 4 R9C10[0][B] clkdiv_1/n53_s5/F
5.687 0.603 tNET FF 1 R7C11[3][B] clkdiv_1/n51_s3/I2
6.296 0.609 tINS FF 1 R7C11[3][B] clkdiv_1/n51_s3/F
6.300 0.004 tNET FF 1 R7C11[0][B] clkdiv_1/n51_s2/I1
7.064 0.765 tINS FF 1 R7C11[0][B] clkdiv_1/n51_s2/F
7.064 0.000 tNET FF 1 R7C11[0][B] clkdiv_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 40 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R7C11[0][B] clkdiv_1/count_11_s0/CLK
39.009 -0.296 tSu 1 R7C11[0][B] clkdiv_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 5
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 2.925, 60.986%; route: 1.531, 31.932%; tC2Q: 0.340, 7.082%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.524
Data Arrival Time 2.053
Data Required Time 1.529
From inst5/count_15_s0
To inst5/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R13C11[0][A] inst5/count_15_s0/CLK
1.776 0.247 tC2Q RR 4 R13C11[0][A] inst5/count_15_s0/Q
1.778 0.002 tNET RR 1 R13C11[0][A] inst5/n47_s2/I2
2.053 0.276 tINS RF 1 R13C11[0][A] inst5/n47_s2/F
2.053 0.000 tNET FF 1 R13C11[0][A] inst5/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R13C11[0][A] inst5/count_15_s0/CLK
1.529 0.000 tHld 1 R13C11[0][A] inst5/count_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path2

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_1/count_0_s0
To clkdiv_1/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[0][A] clkdiv_1/count_0_s0/CLK
1.776 0.247 tC2Q RR 5 R9C11[0][A] clkdiv_1/count_0_s0/Q
1.778 0.003 tNET RR 1 R9C11[0][A] clkdiv_1/n62_s3/I0
2.054 0.276 tINS RF 1 R9C11[0][A] clkdiv_1/n62_s3/F
2.054 0.000 tNET FF 1 R9C11[0][A] clkdiv_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[0][A] clkdiv_1/count_0_s0/CLK
1.529 0.000 tHld 1 R9C11[0][A] clkdiv_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path3

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_1/count_14_s0
To clkdiv_1/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[1][A] clkdiv_1/count_14_s0/CLK
1.776 0.247 tC2Q RR 5 R7C12[1][A] clkdiv_1/count_14_s0/Q
1.778 0.003 tNET RR 1 R7C12[1][A] clkdiv_1/n48_s3/I2
2.054 0.276 tINS RF 1 R7C12[1][A] clkdiv_1/n48_s3/F
2.054 0.000 tNET FF 1 R7C12[1][A] clkdiv_1/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[1][A] clkdiv_1/count_14_s0/CLK
1.529 0.000 tHld 1 R7C12[1][A] clkdiv_1/count_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path4

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_1/count_15_s0
To clkdiv_1/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[0][A] clkdiv_1/count_15_s0/CLK
1.776 0.247 tC2Q RR 5 R7C12[0][A] clkdiv_1/count_15_s0/Q
1.778 0.003 tNET RR 1 R7C12[0][A] clkdiv_1/n47_s4/I2
2.054 0.276 tINS RF 1 R7C12[0][A] clkdiv_1/n47_s4/F
2.054 0.000 tNET FF 1 R7C12[0][A] clkdiv_1/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C12[0][A] clkdiv_1/count_15_s0/CLK
1.529 0.000 tHld 1 R7C12[0][A] clkdiv_1/count_15_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path5

Path Summary:

Slack 0.525
Data Arrival Time 2.054
Data Required Time 1.529
From clkdiv_1/count_17_s0
To clkdiv_1/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C11[0][A] clkdiv_1/count_17_s0/CLK
1.776 0.247 tC2Q RR 4 R8C11[0][A] clkdiv_1/count_17_s0/Q
1.778 0.003 tNET RR 1 R8C11[0][A] clkdiv_1/n45_s7/I2
2.054 0.276 tINS RF 1 R8C11[0][A] clkdiv_1/n45_s7/F
2.054 0.000 tNET FF 1 R8C11[0][A] clkdiv_1/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C11[0][A] clkdiv_1/count_17_s0/CLK
1.529 0.000 tHld 1 R8C11[0][A] clkdiv_1/count_17_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path6

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From inst5/count_9_s0
To inst5/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C13[0][A] inst5/count_9_s0/CLK
1.776 0.247 tC2Q RR 5 R11C13[0][A] inst5/count_9_s0/Q
1.779 0.003 tNET RR 1 R11C13[0][A] inst5/n53_s2/I2
2.055 0.276 tINS RF 1 R11C13[0][A] inst5/n53_s2/F
2.055 0.000 tNET FF 1 R11C13[0][A] inst5/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C13[0][A] inst5/count_9_s0/CLK
1.529 0.000 tHld 1 R11C13[0][A] inst5/count_9_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path7

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From inst5/count_12_s0
To inst5/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[1][A] inst5/count_12_s0/CLK
1.776 0.247 tC2Q RR 4 R11C12[1][A] inst5/count_12_s0/Q
1.779 0.003 tNET RR 1 R11C12[1][A] inst5/n50_s2/I2
2.055 0.276 tINS RF 1 R11C12[1][A] inst5/n50_s2/F
2.055 0.000 tNET FF 1 R11C12[1][A] inst5/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[1][A] inst5/count_12_s0/CLK
1.529 0.000 tHld 1 R11C12[1][A] inst5/count_12_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path8

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From inst5/count_14_s0
To inst5/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C11[0][A] inst5/count_14_s0/CLK
1.776 0.247 tC2Q RR 5 R12C11[0][A] inst5/count_14_s0/Q
1.779 0.003 tNET RR 1 R12C11[0][A] inst5/n48_s2/I0
2.055 0.276 tINS RF 1 R12C11[0][A] inst5/n48_s2/F
2.055 0.000 tNET FF 1 R12C11[0][A] inst5/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C11[0][A] inst5/count_14_s0/CLK
1.529 0.000 tHld 1 R12C11[0][A] inst5/count_14_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path9

Path Summary:

Slack 0.526
Data Arrival Time 2.055
Data Required Time 1.529
From clkdiv_1/count_13_s0
To clkdiv_1/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C10[1][A] clkdiv_1/count_13_s0/CLK
1.776 0.247 tC2Q RR 7 R9C10[1][A] clkdiv_1/count_13_s0/Q
1.779 0.003 tNET RR 1 R9C10[1][A] clkdiv_1/n49_s2/I1
2.055 0.276 tINS RF 1 R9C10[1][A] clkdiv_1/n49_s2/F
2.055 0.000 tNET FF 1 R9C10[1][A] clkdiv_1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C10[1][A] clkdiv_1/count_13_s0/CLK
1.529 0.000 tHld 1 R9C10[1][A] clkdiv_1/count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path10

Path Summary:

Slack 0.527
Data Arrival Time 2.056
Data Required Time 1.529
From clkdiv_1/count_4_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C10[1][A] clkdiv_1/count_4_s0/CLK
1.776 0.247 tC2Q RR 7 R7C10[1][A] clkdiv_1/count_4_s0/Q
1.780 0.004 tNET RR 1 R7C10[1][A] clkdiv_1/n58_s2/I1
2.056 0.276 tINS RF 1 R7C10[1][A] clkdiv_1/n58_s2/F
2.056 0.000 tNET FF 1 R7C10[1][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C10[1][A] clkdiv_1/count_4_s0/CLK
1.529 0.000 tHld 1 R7C10[1][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path11

Path Summary:

Slack 0.527
Data Arrival Time 2.056
Data Required Time 1.529
From clkdiv_1/count_5_s0
To clkdiv_1/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C12[1][A] clkdiv_1/count_5_s0/CLK
1.776 0.247 tC2Q RR 6 R8C12[1][A] clkdiv_1/count_5_s0/Q
1.780 0.004 tNET RR 1 R8C12[1][A] clkdiv_1/n57_s2/I1
2.056 0.276 tINS RF 1 R8C12[1][A] clkdiv_1/n57_s2/F
2.056 0.000 tNET FF 1 R8C12[1][A] clkdiv_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C12[1][A] clkdiv_1/count_5_s0/CLK
1.529 0.000 tHld 1 R8C12[1][A] clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path12

Path Summary:

Slack 0.527
Data Arrival Time 1.033
Data Required Time 0.506
From inst2/index_0_s0
To inst2/index_0_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C10[0][A] clkdiv_1/clk_out_s0/Q
0.506 0.506 tNET RR 1 R11C7[1][A] inst2/index_0_s0/CLK
0.753 0.247 tC2Q RR 12 R11C7[1][A] inst2/index_0_s0/Q
0.758 0.004 tNET RR 1 R11C7[1][A] inst2/n137_s2/I0
1.033 0.276 tINS RF 1 R11C7[1][A] inst2/n137_s2/F
1.033 0.000 tNET FF 1 R11C7[1][A] inst2/index_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C10[0][A] clkdiv_1/clk_out_s0/Q
0.506 0.506 tNET RR 1 R11C7[1][A] inst2/index_0_s0/CLK
0.506 0.000 tHld 1 R11C7[1][A] inst2/index_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.506, 100.000%
Arrival Data Path Delay cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.506, 100.000%

Path13

Path Summary:

Slack 0.527
Data Arrival Time 1.033
Data Required Time 0.506
From inst2/index_2_s0
To inst2/index_2_s0
Launch Clk clk50hz:[R]
Latch Clk clk50hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C10[0][A] clkdiv_1/clk_out_s0/Q
0.506 0.506 tNET RR 1 R12C7[1][A] inst2/index_2_s0/CLK
0.753 0.247 tC2Q RR 10 R12C7[1][A] inst2/index_2_s0/Q
0.758 0.004 tNET RR 1 R12C7[1][A] inst2/n135_s0/I2
1.033 0.276 tINS RF 1 R12C7[1][A] inst2/n135_s0/F
1.033 0.000 tNET FF 1 R12C7[1][A] inst2/index_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk50hz
0.000 0.000 tCL RR 40 R9C10[0][A] clkdiv_1/clk_out_s0/Q
0.506 0.506 tNET RR 1 R12C7[1][A] inst2/index_2_s0/CLK
0.506 0.000 tHld 1 R12C7[1][A] inst2/index_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.506, 100.000%
Arrival Data Path Delay cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.506, 100.000%

Path14

Path Summary:

Slack 0.662
Data Arrival Time 2.190
Data Required Time 1.529
From inst5/count_11_s0
To inst5/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[2][A] inst5/count_11_s0/CLK
1.776 0.247 tC2Q RR 5 R11C12[2][A] inst5/count_11_s0/Q
1.778 0.003 tNET RR 1 R11C12[2][A] inst5/n51_s2/I2
2.190 0.412 tINS RR 1 R11C12[2][A] inst5/n51_s2/F
2.190 0.000 tNET RR 1 R11C12[2][A] inst5/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[2][A] inst5/count_11_s0/CLK
1.529 0.000 tHld 1 R11C12[2][A] inst5/count_11_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path15

Path Summary:

Slack 0.662
Data Arrival Time 2.190
Data Required Time 1.529
From clkdiv_1/count_7_s0
To clkdiv_1/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C11[2][A] clkdiv_1/count_7_s0/CLK
1.776 0.247 tC2Q RR 6 R7C11[2][A] clkdiv_1/count_7_s0/Q
1.778 0.003 tNET RR 1 R7C11[2][A] clkdiv_1/n55_s2/I1
2.190 0.412 tINS RR 1 R7C11[2][A] clkdiv_1/n55_s2/F
2.190 0.000 tNET RR 1 R7C11[2][A] clkdiv_1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R7C11[2][A] clkdiv_1/count_7_s0/CLK
1.529 0.000 tHld 1 R7C11[2][A] clkdiv_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path16

Path Summary:

Slack 0.662
Data Arrival Time 2.191
Data Required Time 1.529
From inst5/count_5_s0
To inst5/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R13C14[2][A] inst5/count_5_s0/CLK
1.776 0.247 tC2Q RR 5 R13C14[2][A] inst5/count_5_s0/Q
1.779 0.003 tNET RR 1 R13C14[2][A] inst5/n57_s2/I2
2.191 0.412 tINS RR 1 R13C14[2][A] inst5/n57_s2/F
2.191 0.000 tNET RR 1 R13C14[2][A] inst5/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R13C14[2][A] inst5/count_5_s0/CLK
1.529 0.000 tHld 1 R13C14[2][A] inst5/count_5_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.412, 62.189%; route: 0.003, 0.528%; tC2Q: 0.247, 37.283%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path17

Path Summary:

Slack 0.662
Data Arrival Time 2.191
Data Required Time 1.529
From inst5/count_7_s0
To inst5/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C13[2][A] inst5/count_7_s0/CLK
1.776 0.247 tC2Q RR 7 R11C13[2][A] inst5/count_7_s0/Q
1.779 0.003 tNET RR 1 R11C13[2][A] inst5/n55_s2/I0
2.191 0.412 tINS RR 1 R11C13[2][A] inst5/n55_s2/F
2.191 0.000 tNET RR 1 R11C13[2][A] inst5/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C13[2][A] inst5/count_7_s0/CLK
1.529 0.000 tHld 1 R11C13[2][A] inst5/count_7_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.412, 62.189%; route: 0.003, 0.528%; tC2Q: 0.247, 37.283%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path18

Path Summary:

Slack 0.663
Data Arrival Time 2.192
Data Required Time 1.529
From inst5/count_2_s0
To inst5/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C14[2][A] inst5/count_2_s0/CLK
1.776 0.247 tC2Q RR 5 R11C14[2][A] inst5/count_2_s0/Q
1.780 0.004 tNET RR 1 R11C14[2][A] inst5/n60_s4/I0
2.192 0.412 tINS RR 1 R11C14[2][A] inst5/n60_s4/F
2.192 0.000 tNET RR 1 R11C14[2][A] inst5/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C14[2][A] inst5/count_2_s0/CLK
1.529 0.000 tHld 1 R11C14[2][A] inst5/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.412, 62.107%; route: 0.004, 0.659%; tC2Q: 0.247, 37.234%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path19

Path Summary:

Slack 0.711
Data Arrival Time 2.240
Data Required Time 1.529
From clkdiv_1/count_19_s0
To clkdiv_1/clk_out_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C11[0][B] clkdiv_1/count_19_s0/CLK
1.776 0.247 tC2Q RF 10 R9C11[0][B] clkdiv_1/count_19_s0/Q
1.964 0.189 tNET FF 1 R9C10[0][A] clkdiv_1/n64_s88/I3
2.240 0.276 tINS FF 1 R9C10[0][A] clkdiv_1/n64_s88/F
2.240 0.000 tNET FF 1 R9C10[0][A] clkdiv_1/clk_out_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C10[0][A] clkdiv_1/clk_out_s0/CLK
1.529 0.000 tHld 1 R9C10[0][A] clkdiv_1/clk_out_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 38.760%; route: 0.189, 26.509%; tC2Q: 0.247, 34.731%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path20

Path Summary:

Slack 0.714
Data Arrival Time 2.243
Data Required Time 1.529
From inst5/count_7_s0
To inst5/count_8_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C13[2][A] inst5/count_7_s0/CLK
1.776 0.247 tC2Q RR 7 R11C13[2][A] inst5/count_7_s0/Q
1.967 0.192 tNET RR 1 R11C13[2][B] inst5/n54_s2/I0
2.243 0.276 tINS RF 1 R11C13[2][B] inst5/n54_s2/F
2.243 0.000 tNET FF 1 R11C13[2][B] inst5/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C13[2][B] inst5/count_8_s0/CLK
1.529 0.000 tHld 1 R11C13[2][B] inst5/count_8_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 38.593%; route: 0.192, 26.825%; tC2Q: 0.247, 34.582%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path21

Path Summary:

Slack 0.722
Data Arrival Time 2.250
Data Required Time 1.529
From inst5/count_1_s0
To inst5/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
1.776 0.247 tC2Q RR 6 R13C13[3][A] inst5/count_1_s0/Q
1.975 0.199 tNET RR 1 R13C13[3][A] inst5/n61_s2/I0
2.250 0.276 tINS RF 1 R13C13[3][A] inst5/n61_s2/F
2.250 0.000 tNET FF 1 R13C13[3][A] inst5/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R13C13[3][A] inst5/count_1_s0/CLK
1.529 0.000 tHld 1 R13C13[3][A] inst5/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 38.201%; route: 0.199, 27.569%; tC2Q: 0.247, 34.230%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path22

Path Summary:

Slack 0.786
Data Arrival Time 2.315
Data Required Time 1.529
From inst5/count_6_s0
To inst5/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C14[0][B] inst5/count_6_s0/CLK
1.776 0.247 tC2Q RR 4 R11C14[0][B] inst5/count_6_s0/Q
1.778 0.003 tNET RR 1 R11C14[0][B] inst5/n56_s2/I2
2.315 0.536 tINS RR 1 R11C14[0][B] inst5/n56_s2/F
2.315 0.000 tNET RR 1 R11C14[0][B] inst5/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C14[0][B] inst5/count_6_s0/CLK
1.529 0.000 tHld 1 R11C14[0][B] inst5/count_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path23

Path Summary:

Slack 0.786
Data Arrival Time 2.315
Data Required Time 1.529
From clkdiv_1/count_2_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C12[0][B] clkdiv_1/count_2_s0/CLK
1.776 0.247 tC2Q RR 3 R8C12[0][B] clkdiv_1/count_2_s0/Q
1.778 0.003 tNET RR 1 R8C12[0][B] clkdiv_1/n60_s2/I1
2.315 0.536 tINS RR 1 R8C12[0][B] clkdiv_1/n60_s2/F
2.315 0.000 tNET RR 1 R8C12[0][B] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C12[0][B] clkdiv_1/count_2_s0/CLK
1.529 0.000 tHld 1 R8C12[0][B] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path24

Path Summary:

Slack 0.787
Data Arrival Time 2.316
Data Required Time 1.529
From inst5/count_3_s0
To inst5/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C14[1][B] inst5/count_3_s0/CLK
1.776 0.247 tC2Q RR 4 R11C14[1][B] inst5/count_3_s0/Q
1.779 0.003 tNET RR 1 R11C14[1][B] inst5/n59_s2/I2
2.316 0.536 tINS RR 1 R11C14[1][B] inst5/n59_s2/F
2.316 0.000 tNET RR 1 R11C14[1][B] inst5/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C14[1][B] inst5/count_3_s0/CLK
1.529 0.000 tHld 1 R11C14[1][B] inst5/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.170%; route: 0.003, 0.445%; tC2Q: 0.247, 31.386%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path25

Path Summary:

Slack 0.787
Data Arrival Time 2.316
Data Required Time 1.529
From inst5/count_13_s0
To inst5/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[0][B] inst5/count_13_s0/CLK
1.776 0.247 tC2Q RR 4 R11C12[0][B] inst5/count_13_s0/Q
1.779 0.003 tNET RR 1 R11C12[0][B] inst5/n49_s2/I2
2.316 0.536 tINS RR 1 R11C12[0][B] inst5/n49_s2/F
2.316 0.000 tNET RR 1 R11C12[0][B] inst5/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 40 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C12[0][B] inst5/count_13_s0/CLK
1.529 0.000 tHld 1 R11C12[0][B] inst5/count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.170%; route: 0.003, 0.445%; tC2Q: 0.247, 31.386%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_19_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_19_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_19_s0/CLK

MPW2

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_17_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_17_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_17_s0/CLK

MPW3

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_13_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_13_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_13_s0/CLK

MPW4

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_5_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_5_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_5_s0/CLK

MPW5

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: inst5/count_8_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF inst5/count_8_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR inst5/count_8_s0/CLK

MPW6

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: inst5/count_9_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF inst5/count_9_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR inst5/count_9_s0/CLK

MPW7

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_6_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_6_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_6_s0/CLK

MPW8

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: inst5/count_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF inst5/count_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR inst5/count_10_s0/CLK

MPW9

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: inst5/count_11_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF inst5/count_11_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR inst5/count_11_s0/CLK

MPW10

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_14_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_14_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_14_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
40 clk_d 30.791 0.195
40 clk50hz 19999978.000 0.798
18 n62_12 30.791 0.653
17 key_15_5 19999976.000 1.807
15 n62_8 31.869 0.641
14 n62_19 32.758 0.637
12 index[0] 19999976.000 0.860
11 index[1] 19999976.000 0.385
10 index[2] 19999976.000 0.321
10 count[19] 33.596 0.630

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R7C6 79.17%
R7C7 72.22%
R11C13 70.83%
R11C12 69.44%
R7C11 65.28%
R8C6 62.50%
R8C11 61.11%
R9C7 59.72%
R7C5 58.33%
R8C10 58.33%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk50hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 540000 [get_nets {clk50hz}]
TC_CLOCK_GROUP Actived set_clock_groups -asynchronous -group [get_clocks {clk27mhz}] -group [get_clocks {clk50hz}]