Synthesis Messages
| Report Title | GowinSynthesis Report |
| Design File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\clkdiv.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\debounce.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\dec16to4.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\decdiv.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\drv7seg.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\matrix_key.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\mux7seg.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\organ.sv C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\organ\src\toggle.sv |
| GowinSynthesis Constraints File | --- |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW1N-UV1P5QN48XFC7/I6 |
| Device | GW1N-1P5 |
| Device Version | C |
| Created Time | Mon Dec 16 16:52:54 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved. |
Synthesis Details
| Top Level Module | organ |
| Synthesis Process | Running parser: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.057s, Peak memory usage = 231.199MB Running netlist conversion: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB Running device independent optimization: Optimizing Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 231.199MB Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 231.199MB Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 231.199MB Running inference: Inferring Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 231.199MB Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 231.199MB Running technical mapping: Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 231.199MB Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 231.199MB Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 231.199MB Tech-Mapping Phase 3: CPU time = 0h 0m 0.468s, Elapsed time = 0h 0m 0.536s, Peak memory usage = 231.199MB Tech-Mapping Phase 4: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 231.199MB Generate output files: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.015s, Peak memory usage = 231.199MB |
| Total Time and Memory Usage | CPU time = 0h 0m 0.575s, Elapsed time = 0h 0m 0.678s, Peak memory usage = 231.199MB |
Resource
Resource Usage Summary
| Resource | Usage |
| I/O Port | 24 |
| I/O Buf | 24 |
|     IBUF | 6 |
|     OBUF | 18 |
| Register | 80 |
|     DFFE | 7 |
|     DFFPE | 16 |
|     DFFC | 41 |
|     DFFCE | 16 |
| LUT | 156 |
|     LUT2 | 28 |
|     LUT3 | 31 |
|     LUT4 | 97 |
| ALU | 31 |
|     ALU | 31 |
| INV | 18 |
|     INV | 18 |
Resource Utilization Summary
| Resource | Usage | Utilization |
| Logic | 205(174 LUT, 31 ALU) / 1584 | 13% |
| Register | 80 / 1704 | 5% |
|   --Register as Latch | 0 / 1704 | 0% |
|   --Register as FF | 80 / 1704 | 5% |
| BSRAM | 0 / 4 | 0% |
Timing
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Object |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk | Base | 20.000 | 50.0 | 0.000 | 10.000 | clk_ibuf/I | ||
| 2 | clkdiv_1/clk50hz | Base | 20.000 | 50.0 | 0.000 | 10.000 | clkdiv_1/clk_out_s0/Q |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk | 50.000(MHz) | 134.223(MHz) | 5 | TOP |
| 2 | clkdiv_1/clk50hz | 50.000(MHz) | 348.056(MHz) | 2 | TOP |
Detail Timing Paths Information
Path 1
Path Summary:| Slack | 5.314 |
| Data Arrival Time | 14.898 |
| Data Required Time | 20.212 |
| From | inst2/key_9_s0 |
| To | inst5/count_0_s0 |
| Launch Clk | clkdiv_1/clk50hz[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clkdiv_1/clk50hz | |||
| 0.000 | 0.000 | tCL | RR | 40 | clkdiv_1/clk_out_s0/Q |
| 0.538 | 0.538 | tNET | RR | 1 | inst2/key_9_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 4 | inst2/key_9_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | inst3/sw_3_s7/I1 |
| 2.403 | 0.814 | tINS | FF | 5 | inst3/sw_3_s7/F |
| 3.115 | 0.711 | tNET | FF | 1 | bz_d_s2/I2 |
| 3.724 | 0.609 | tINS | FF | 1 | bz_d_s2/F |
| 4.435 | 0.711 | tNET | FF | 1 | bz_d_s0/I1 |
| 5.249 | 0.814 | tINS | FF | 2 | bz_d_s0/F |
| 5.961 | 0.711 | tNET | FF | 1 | inst3/seg_d_0_s0/I3 |
| 6.425 | 0.464 | tINS | FF | 2 | inst3/seg_d_0_s0/F |
| 7.136 | 0.711 | tNET | FF | 1 | inst3/sw_0_s/I2 |
| 7.745 | 0.609 | tINS | FF | 23 | inst3/sw_0_s/F |
| 8.457 | 0.711 | tNET | FF | 1 | inst4/count_0_s16/I0 |
| 9.221 | 0.765 | tINS | FF | 1 | inst4/count_0_s16/F |
| 9.933 | 0.711 | tNET | FF | 2 | inst5/tc_s61/I1 |
| 10.707 | 0.774 | tINS | FF | 1 | inst5/tc_s61/COUT |
| 10.707 | 0.000 | tNET | FF | 2 | inst5/tc_s62/CIN |
| 10.749 | 0.042 | tINS | FF | 1 | inst5/tc_s62/COUT |
| 10.749 | 0.000 | tNET | FF | 2 | inst5/tc_s63/CIN |
| 10.791 | 0.042 | tINS | FF | 1 | inst5/tc_s63/COUT |
| 10.791 | 0.000 | tNET | FF | 2 | inst5/tc_s64/CIN |
| 10.834 | 0.042 | tINS | FF | 1 | inst5/tc_s64/COUT |
| 10.834 | 0.000 | tNET | FF | 2 | inst5/tc_s65/CIN |
| 10.876 | 0.042 | tINS | FF | 1 | inst5/tc_s65/COUT |
| 10.876 | 0.000 | tNET | FF | 2 | inst5/tc_s66/CIN |
| 10.918 | 0.042 | tINS | FF | 1 | inst5/tc_s66/COUT |
| 10.918 | 0.000 | tNET | FF | 2 | inst5/tc_s67/CIN |
| 10.960 | 0.042 | tINS | FF | 1 | inst5/tc_s67/COUT |
| 10.960 | 0.000 | tNET | FF | 2 | inst5/tc_s68/CIN |
| 11.003 | 0.042 | tINS | FF | 1 | inst5/tc_s68/COUT |
| 11.003 | 0.000 | tNET | FF | 2 | inst5/tc_s69/CIN |
| 11.045 | 0.042 | tINS | FF | 1 | inst5/tc_s69/COUT |
| 11.045 | 0.000 | tNET | FF | 2 | inst5/tc_s70/CIN |
| 11.087 | 0.042 | tINS | FF | 1 | inst5/tc_s70/COUT |
| 11.087 | 0.000 | tNET | FF | 2 | inst5/tc_s71/CIN |
| 11.129 | 0.042 | tINS | FF | 1 | inst5/tc_s71/COUT |
| 11.129 | 0.000 | tNET | FF | 2 | inst5/tc_s72/CIN |
| 11.172 | 0.042 | tINS | FF | 1 | inst5/tc_s72/COUT |
| 11.172 | 0.000 | tNET | FF | 2 | inst5/tc_s73/CIN |
| 11.214 | 0.042 | tINS | FF | 1 | inst5/tc_s73/COUT |
| 11.214 | 0.000 | tNET | FF | 2 | inst5/tc_s74/CIN |
| 11.256 | 0.042 | tINS | FF | 1 | inst5/tc_s74/COUT |
| 11.256 | 0.000 | tNET | FF | 2 | inst5/tc_s75/CIN |
| 11.298 | 0.042 | tINS | FF | 1 | inst5/tc_s75/COUT |
| 11.298 | 0.000 | tNET | FF | 2 | inst5/tc_s76/CIN |
| 11.341 | 0.042 | tINS | FF | 1 | inst5/tc_s76/COUT |
| 12.052 | 0.711 | tNET | FF | 1 | inst5/n62_s5/I2 |
| 12.661 | 0.609 | tINS | FF | 18 | inst5/n62_s5/F |
| 13.372 | 0.711 | tNET | FF | 1 | inst5/n62_s2/I1 |
| 14.187 | 0.814 | tINS | FF | 1 | inst5/n62_s2/F |
| 14.898 | 0.711 | tNET | FF | 1 | inst5/count_0_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | inst5/count_0_s0/CLK |
| 20.508 | -0.030 | tUnc | inst5/count_0_s0 | ||
| 20.212 | -0.296 | tSu | 1 | inst5/count_0_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 6.907, 48.098%; route: 7.114, 49.537%; tC2Q: 0.340, 2.365% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 2
Path Summary:| Slack | 5.314 |
| Data Arrival Time | 14.898 |
| Data Required Time | 20.212 |
| From | inst2/key_9_s0 |
| To | inst5/count_17_s0 |
| Launch Clk | clkdiv_1/clk50hz[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clkdiv_1/clk50hz | |||
| 0.000 | 0.000 | tCL | RR | 40 | clkdiv_1/clk_out_s0/Q |
| 0.538 | 0.538 | tNET | RR | 1 | inst2/key_9_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 4 | inst2/key_9_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | inst3/sw_3_s7/I1 |
| 2.403 | 0.814 | tINS | FF | 5 | inst3/sw_3_s7/F |
| 3.115 | 0.711 | tNET | FF | 1 | bz_d_s2/I2 |
| 3.724 | 0.609 | tINS | FF | 1 | bz_d_s2/F |
| 4.435 | 0.711 | tNET | FF | 1 | bz_d_s0/I1 |
| 5.249 | 0.814 | tINS | FF | 2 | bz_d_s0/F |
| 5.961 | 0.711 | tNET | FF | 1 | inst3/seg_d_0_s0/I3 |
| 6.425 | 0.464 | tINS | FF | 2 | inst3/seg_d_0_s0/F |
| 7.136 | 0.711 | tNET | FF | 1 | inst3/sw_0_s/I2 |
| 7.745 | 0.609 | tINS | FF | 23 | inst3/sw_0_s/F |
| 8.457 | 0.711 | tNET | FF | 1 | inst4/count_0_s16/I0 |
| 9.221 | 0.765 | tINS | FF | 1 | inst4/count_0_s16/F |
| 9.933 | 0.711 | tNET | FF | 2 | inst5/tc_s61/I1 |
| 10.707 | 0.774 | tINS | FF | 1 | inst5/tc_s61/COUT |
| 10.707 | 0.000 | tNET | FF | 2 | inst5/tc_s62/CIN |
| 10.749 | 0.042 | tINS | FF | 1 | inst5/tc_s62/COUT |
| 10.749 | 0.000 | tNET | FF | 2 | inst5/tc_s63/CIN |
| 10.791 | 0.042 | tINS | FF | 1 | inst5/tc_s63/COUT |
| 10.791 | 0.000 | tNET | FF | 2 | inst5/tc_s64/CIN |
| 10.834 | 0.042 | tINS | FF | 1 | inst5/tc_s64/COUT |
| 10.834 | 0.000 | tNET | FF | 2 | inst5/tc_s65/CIN |
| 10.876 | 0.042 | tINS | FF | 1 | inst5/tc_s65/COUT |
| 10.876 | 0.000 | tNET | FF | 2 | inst5/tc_s66/CIN |
| 10.918 | 0.042 | tINS | FF | 1 | inst5/tc_s66/COUT |
| 10.918 | 0.000 | tNET | FF | 2 | inst5/tc_s67/CIN |
| 10.960 | 0.042 | tINS | FF | 1 | inst5/tc_s67/COUT |
| 10.960 | 0.000 | tNET | FF | 2 | inst5/tc_s68/CIN |
| 11.003 | 0.042 | tINS | FF | 1 | inst5/tc_s68/COUT |
| 11.003 | 0.000 | tNET | FF | 2 | inst5/tc_s69/CIN |
| 11.045 | 0.042 | tINS | FF | 1 | inst5/tc_s69/COUT |
| 11.045 | 0.000 | tNET | FF | 2 | inst5/tc_s70/CIN |
| 11.087 | 0.042 | tINS | FF | 1 | inst5/tc_s70/COUT |
| 11.087 | 0.000 | tNET | FF | 2 | inst5/tc_s71/CIN |
| 11.129 | 0.042 | tINS | FF | 1 | inst5/tc_s71/COUT |
| 11.129 | 0.000 | tNET | FF | 2 | inst5/tc_s72/CIN |
| 11.172 | 0.042 | tINS | FF | 1 | inst5/tc_s72/COUT |
| 11.172 | 0.000 | tNET | FF | 2 | inst5/tc_s73/CIN |
| 11.214 | 0.042 | tINS | FF | 1 | inst5/tc_s73/COUT |
| 11.214 | 0.000 | tNET | FF | 2 | inst5/tc_s74/CIN |
| 11.256 | 0.042 | tINS | FF | 1 | inst5/tc_s74/COUT |
| 11.256 | 0.000 | tNET | FF | 2 | inst5/tc_s75/CIN |
| 11.298 | 0.042 | tINS | FF | 1 | inst5/tc_s75/COUT |
| 11.298 | 0.000 | tNET | FF | 2 | inst5/tc_s76/CIN |
| 11.341 | 0.042 | tINS | FF | 1 | inst5/tc_s76/COUT |
| 12.052 | 0.711 | tNET | FF | 1 | inst5/n62_s5/I2 |
| 12.661 | 0.609 | tINS | FF | 18 | inst5/n62_s5/F |
| 13.372 | 0.711 | tNET | FF | 1 | inst5/n45_s2/I1 |
| 14.187 | 0.814 | tINS | FF | 1 | inst5/n45_s2/F |
| 14.898 | 0.711 | tNET | FF | 1 | inst5/count_17_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | inst5/count_17_s0/CLK |
| 20.508 | -0.030 | tUnc | inst5/count_17_s0 | ||
| 20.212 | -0.296 | tSu | 1 | inst5/count_17_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 6.907, 48.098%; route: 7.114, 49.537%; tC2Q: 0.340, 2.365% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 3
Path Summary:| Slack | 5.519 |
| Data Arrival Time | 14.693 |
| Data Required Time | 20.212 |
| From | inst2/key_9_s0 |
| To | inst5/count_1_s0 |
| Launch Clk | clkdiv_1/clk50hz[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clkdiv_1/clk50hz | |||
| 0.000 | 0.000 | tCL | RR | 40 | clkdiv_1/clk_out_s0/Q |
| 0.538 | 0.538 | tNET | RR | 1 | inst2/key_9_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 4 | inst2/key_9_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | inst3/sw_3_s7/I1 |
| 2.403 | 0.814 | tINS | FF | 5 | inst3/sw_3_s7/F |
| 3.115 | 0.711 | tNET | FF | 1 | bz_d_s2/I2 |
| 3.724 | 0.609 | tINS | FF | 1 | bz_d_s2/F |
| 4.435 | 0.711 | tNET | FF | 1 | bz_d_s0/I1 |
| 5.249 | 0.814 | tINS | FF | 2 | bz_d_s0/F |
| 5.961 | 0.711 | tNET | FF | 1 | inst3/seg_d_0_s0/I3 |
| 6.425 | 0.464 | tINS | FF | 2 | inst3/seg_d_0_s0/F |
| 7.136 | 0.711 | tNET | FF | 1 | inst3/sw_0_s/I2 |
| 7.745 | 0.609 | tINS | FF | 23 | inst3/sw_0_s/F |
| 8.457 | 0.711 | tNET | FF | 1 | inst4/count_0_s16/I0 |
| 9.221 | 0.765 | tINS | FF | 1 | inst4/count_0_s16/F |
| 9.933 | 0.711 | tNET | FF | 2 | inst5/tc_s61/I1 |
| 10.707 | 0.774 | tINS | FF | 1 | inst5/tc_s61/COUT |
| 10.707 | 0.000 | tNET | FF | 2 | inst5/tc_s62/CIN |
| 10.749 | 0.042 | tINS | FF | 1 | inst5/tc_s62/COUT |
| 10.749 | 0.000 | tNET | FF | 2 | inst5/tc_s63/CIN |
| 10.791 | 0.042 | tINS | FF | 1 | inst5/tc_s63/COUT |
| 10.791 | 0.000 | tNET | FF | 2 | inst5/tc_s64/CIN |
| 10.834 | 0.042 | tINS | FF | 1 | inst5/tc_s64/COUT |
| 10.834 | 0.000 | tNET | FF | 2 | inst5/tc_s65/CIN |
| 10.876 | 0.042 | tINS | FF | 1 | inst5/tc_s65/COUT |
| 10.876 | 0.000 | tNET | FF | 2 | inst5/tc_s66/CIN |
| 10.918 | 0.042 | tINS | FF | 1 | inst5/tc_s66/COUT |
| 10.918 | 0.000 | tNET | FF | 2 | inst5/tc_s67/CIN |
| 10.960 | 0.042 | tINS | FF | 1 | inst5/tc_s67/COUT |
| 10.960 | 0.000 | tNET | FF | 2 | inst5/tc_s68/CIN |
| 11.003 | 0.042 | tINS | FF | 1 | inst5/tc_s68/COUT |
| 11.003 | 0.000 | tNET | FF | 2 | inst5/tc_s69/CIN |
| 11.045 | 0.042 | tINS | FF | 1 | inst5/tc_s69/COUT |
| 11.045 | 0.000 | tNET | FF | 2 | inst5/tc_s70/CIN |
| 11.087 | 0.042 | tINS | FF | 1 | inst5/tc_s70/COUT |
| 11.087 | 0.000 | tNET | FF | 2 | inst5/tc_s71/CIN |
| 11.129 | 0.042 | tINS | FF | 1 | inst5/tc_s71/COUT |
| 11.129 | 0.000 | tNET | FF | 2 | inst5/tc_s72/CIN |
| 11.172 | 0.042 | tINS | FF | 1 | inst5/tc_s72/COUT |
| 11.172 | 0.000 | tNET | FF | 2 | inst5/tc_s73/CIN |
| 11.214 | 0.042 | tINS | FF | 1 | inst5/tc_s73/COUT |
| 11.214 | 0.000 | tNET | FF | 2 | inst5/tc_s74/CIN |
| 11.256 | 0.042 | tINS | FF | 1 | inst5/tc_s74/COUT |
| 11.256 | 0.000 | tNET | FF | 2 | inst5/tc_s75/CIN |
| 11.298 | 0.042 | tINS | FF | 1 | inst5/tc_s75/COUT |
| 11.298 | 0.000 | tNET | FF | 2 | inst5/tc_s76/CIN |
| 11.341 | 0.042 | tINS | FF | 1 | inst5/tc_s76/COUT |
| 12.052 | 0.711 | tNET | FF | 1 | inst5/n62_s5/I2 |
| 12.661 | 0.609 | tINS | FF | 18 | inst5/n62_s5/F |
| 13.372 | 0.711 | tNET | FF | 1 | inst5/n61_s2/I2 |
| 13.981 | 0.609 | tINS | FF | 1 | inst5/n61_s2/F |
| 14.693 | 0.711 | tNET | FF | 1 | inst5/count_1_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | inst5/count_1_s0/CLK |
| 20.508 | -0.030 | tUnc | inst5/count_1_s0 | ||
| 20.212 | -0.296 | tSu | 1 | inst5/count_1_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 6.702, 47.345%; route: 7.114, 50.256%; tC2Q: 0.340, 2.399% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 4
Path Summary:| Slack | 5.519 |
| Data Arrival Time | 14.693 |
| Data Required Time | 20.212 |
| From | inst2/key_9_s0 |
| To | inst5/count_4_s0 |
| Launch Clk | clkdiv_1/clk50hz[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clkdiv_1/clk50hz | |||
| 0.000 | 0.000 | tCL | RR | 40 | clkdiv_1/clk_out_s0/Q |
| 0.538 | 0.538 | tNET | RR | 1 | inst2/key_9_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 4 | inst2/key_9_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | inst3/sw_3_s7/I1 |
| 2.403 | 0.814 | tINS | FF | 5 | inst3/sw_3_s7/F |
| 3.115 | 0.711 | tNET | FF | 1 | bz_d_s2/I2 |
| 3.724 | 0.609 | tINS | FF | 1 | bz_d_s2/F |
| 4.435 | 0.711 | tNET | FF | 1 | bz_d_s0/I1 |
| 5.249 | 0.814 | tINS | FF | 2 | bz_d_s0/F |
| 5.961 | 0.711 | tNET | FF | 1 | inst3/seg_d_0_s0/I3 |
| 6.425 | 0.464 | tINS | FF | 2 | inst3/seg_d_0_s0/F |
| 7.136 | 0.711 | tNET | FF | 1 | inst3/sw_0_s/I2 |
| 7.745 | 0.609 | tINS | FF | 23 | inst3/sw_0_s/F |
| 8.457 | 0.711 | tNET | FF | 1 | inst4/count_0_s16/I0 |
| 9.221 | 0.765 | tINS | FF | 1 | inst4/count_0_s16/F |
| 9.933 | 0.711 | tNET | FF | 2 | inst5/tc_s61/I1 |
| 10.707 | 0.774 | tINS | FF | 1 | inst5/tc_s61/COUT |
| 10.707 | 0.000 | tNET | FF | 2 | inst5/tc_s62/CIN |
| 10.749 | 0.042 | tINS | FF | 1 | inst5/tc_s62/COUT |
| 10.749 | 0.000 | tNET | FF | 2 | inst5/tc_s63/CIN |
| 10.791 | 0.042 | tINS | FF | 1 | inst5/tc_s63/COUT |
| 10.791 | 0.000 | tNET | FF | 2 | inst5/tc_s64/CIN |
| 10.834 | 0.042 | tINS | FF | 1 | inst5/tc_s64/COUT |
| 10.834 | 0.000 | tNET | FF | 2 | inst5/tc_s65/CIN |
| 10.876 | 0.042 | tINS | FF | 1 | inst5/tc_s65/COUT |
| 10.876 | 0.000 | tNET | FF | 2 | inst5/tc_s66/CIN |
| 10.918 | 0.042 | tINS | FF | 1 | inst5/tc_s66/COUT |
| 10.918 | 0.000 | tNET | FF | 2 | inst5/tc_s67/CIN |
| 10.960 | 0.042 | tINS | FF | 1 | inst5/tc_s67/COUT |
| 10.960 | 0.000 | tNET | FF | 2 | inst5/tc_s68/CIN |
| 11.003 | 0.042 | tINS | FF | 1 | inst5/tc_s68/COUT |
| 11.003 | 0.000 | tNET | FF | 2 | inst5/tc_s69/CIN |
| 11.045 | 0.042 | tINS | FF | 1 | inst5/tc_s69/COUT |
| 11.045 | 0.000 | tNET | FF | 2 | inst5/tc_s70/CIN |
| 11.087 | 0.042 | tINS | FF | 1 | inst5/tc_s70/COUT |
| 11.087 | 0.000 | tNET | FF | 2 | inst5/tc_s71/CIN |
| 11.129 | 0.042 | tINS | FF | 1 | inst5/tc_s71/COUT |
| 11.129 | 0.000 | tNET | FF | 2 | inst5/tc_s72/CIN |
| 11.172 | 0.042 | tINS | FF | 1 | inst5/tc_s72/COUT |
| 11.172 | 0.000 | tNET | FF | 2 | inst5/tc_s73/CIN |
| 11.214 | 0.042 | tINS | FF | 1 | inst5/tc_s73/COUT |
| 11.214 | 0.000 | tNET | FF | 2 | inst5/tc_s74/CIN |
| 11.256 | 0.042 | tINS | FF | 1 | inst5/tc_s74/COUT |
| 11.256 | 0.000 | tNET | FF | 2 | inst5/tc_s75/CIN |
| 11.298 | 0.042 | tINS | FF | 1 | inst5/tc_s75/COUT |
| 11.298 | 0.000 | tNET | FF | 2 | inst5/tc_s76/CIN |
| 11.341 | 0.042 | tINS | FF | 1 | inst5/tc_s76/COUT |
| 12.052 | 0.711 | tNET | FF | 1 | inst5/n62_s5/I2 |
| 12.661 | 0.609 | tINS | FF | 18 | inst5/n62_s5/F |
| 13.372 | 0.711 | tNET | FF | 1 | inst5/n58_s2/I2 |
| 13.981 | 0.609 | tINS | FF | 1 | inst5/n58_s2/F |
| 14.693 | 0.711 | tNET | FF | 1 | inst5/count_4_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | inst5/count_4_s0/CLK |
| 20.508 | -0.030 | tUnc | inst5/count_4_s0 | ||
| 20.212 | -0.296 | tSu | 1 | inst5/count_4_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 6.702, 47.345%; route: 7.114, 50.256%; tC2Q: 0.340, 2.399% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
Path 5
Path Summary:| Slack | 5.519 |
| Data Arrival Time | 14.693 |
| Data Required Time | 20.212 |
| From | inst2/key_9_s0 |
| To | inst5/count_7_s0 |
| Launch Clk | clkdiv_1/clk50hz[R] |
| Latch Clk | clk[R] |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 0.000 | 0.000 | clkdiv_1/clk50hz | |||
| 0.000 | 0.000 | tCL | RR | 40 | clkdiv_1/clk_out_s0/Q |
| 0.538 | 0.538 | tNET | RR | 1 | inst2/key_9_s0/CLK |
| 0.878 | 0.340 | tC2Q | RF | 4 | inst2/key_9_s0/Q |
| 1.589 | 0.711 | tNET | FF | 1 | inst3/sw_3_s7/I1 |
| 2.403 | 0.814 | tINS | FF | 5 | inst3/sw_3_s7/F |
| 3.115 | 0.711 | tNET | FF | 1 | bz_d_s2/I2 |
| 3.724 | 0.609 | tINS | FF | 1 | bz_d_s2/F |
| 4.435 | 0.711 | tNET | FF | 1 | bz_d_s0/I1 |
| 5.249 | 0.814 | tINS | FF | 2 | bz_d_s0/F |
| 5.961 | 0.711 | tNET | FF | 1 | inst3/seg_d_0_s0/I3 |
| 6.425 | 0.464 | tINS | FF | 2 | inst3/seg_d_0_s0/F |
| 7.136 | 0.711 | tNET | FF | 1 | inst3/sw_0_s/I2 |
| 7.745 | 0.609 | tINS | FF | 23 | inst3/sw_0_s/F |
| 8.457 | 0.711 | tNET | FF | 1 | inst4/count_0_s16/I0 |
| 9.221 | 0.765 | tINS | FF | 1 | inst4/count_0_s16/F |
| 9.933 | 0.711 | tNET | FF | 2 | inst5/tc_s61/I1 |
| 10.707 | 0.774 | tINS | FF | 1 | inst5/tc_s61/COUT |
| 10.707 | 0.000 | tNET | FF | 2 | inst5/tc_s62/CIN |
| 10.749 | 0.042 | tINS | FF | 1 | inst5/tc_s62/COUT |
| 10.749 | 0.000 | tNET | FF | 2 | inst5/tc_s63/CIN |
| 10.791 | 0.042 | tINS | FF | 1 | inst5/tc_s63/COUT |
| 10.791 | 0.000 | tNET | FF | 2 | inst5/tc_s64/CIN |
| 10.834 | 0.042 | tINS | FF | 1 | inst5/tc_s64/COUT |
| 10.834 | 0.000 | tNET | FF | 2 | inst5/tc_s65/CIN |
| 10.876 | 0.042 | tINS | FF | 1 | inst5/tc_s65/COUT |
| 10.876 | 0.000 | tNET | FF | 2 | inst5/tc_s66/CIN |
| 10.918 | 0.042 | tINS | FF | 1 | inst5/tc_s66/COUT |
| 10.918 | 0.000 | tNET | FF | 2 | inst5/tc_s67/CIN |
| 10.960 | 0.042 | tINS | FF | 1 | inst5/tc_s67/COUT |
| 10.960 | 0.000 | tNET | FF | 2 | inst5/tc_s68/CIN |
| 11.003 | 0.042 | tINS | FF | 1 | inst5/tc_s68/COUT |
| 11.003 | 0.000 | tNET | FF | 2 | inst5/tc_s69/CIN |
| 11.045 | 0.042 | tINS | FF | 1 | inst5/tc_s69/COUT |
| 11.045 | 0.000 | tNET | FF | 2 | inst5/tc_s70/CIN |
| 11.087 | 0.042 | tINS | FF | 1 | inst5/tc_s70/COUT |
| 11.087 | 0.000 | tNET | FF | 2 | inst5/tc_s71/CIN |
| 11.129 | 0.042 | tINS | FF | 1 | inst5/tc_s71/COUT |
| 11.129 | 0.000 | tNET | FF | 2 | inst5/tc_s72/CIN |
| 11.172 | 0.042 | tINS | FF | 1 | inst5/tc_s72/COUT |
| 11.172 | 0.000 | tNET | FF | 2 | inst5/tc_s73/CIN |
| 11.214 | 0.042 | tINS | FF | 1 | inst5/tc_s73/COUT |
| 11.214 | 0.000 | tNET | FF | 2 | inst5/tc_s74/CIN |
| 11.256 | 0.042 | tINS | FF | 1 | inst5/tc_s74/COUT |
| 11.256 | 0.000 | tNET | FF | 2 | inst5/tc_s75/CIN |
| 11.298 | 0.042 | tINS | FF | 1 | inst5/tc_s75/COUT |
| 11.298 | 0.000 | tNET | FF | 2 | inst5/tc_s76/CIN |
| 11.341 | 0.042 | tINS | FF | 1 | inst5/tc_s76/COUT |
| 12.052 | 0.711 | tNET | FF | 1 | inst5/n62_s5/I2 |
| 12.661 | 0.609 | tINS | FF | 18 | inst5/n62_s5/F |
| 13.372 | 0.711 | tNET | FF | 1 | inst5/n55_s2/I2 |
| 13.981 | 0.609 | tINS | FF | 1 | inst5/n55_s2/F |
| 14.693 | 0.711 | tNET | FF | 1 | inst5/count_7_s0/D |
| AT | DELAY | TYPE | RF | FANOUT | NODE |
|---|---|---|---|---|---|
| 20.000 | 0.000 | clk | |||
| 20.000 | 0.000 | tCL | RR | 1 | clk_ibuf/I |
| 20.000 | 0.000 | tINS | RR | 40 | clk_ibuf/O |
| 20.538 | 0.538 | tNET | RR | 1 | inst5/count_7_s0/CLK |
| 20.508 | -0.030 | tUnc | inst5/count_7_s0 | ||
| 20.212 | -0.296 | tSu | 1 | inst5/count_7_s0 |
| Clock Skew: | 0.000 |
| Setup Relationship: | 20.000 |
| Logic Level: | 12 |
| Arrival Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |
| Arrival Data Path Delay: | cell: 6.702, 47.345%; route: 7.114, 50.256%; tC2Q: 0.340, 2.399% |
| Required Clock Path Delay: | cell: 0.000, 0.000%; route: 0.538, 100.000% |