Timing Messages
| Report Title | Timing Analysis Report |
| Design File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\impl\gwsynthesis\stopwatchB.vg |
| Physical Constraints File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\stopwatch.cst |
| Timing Constraint File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatchB\src\stopwatchB.sdc |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW1N-UV1P5QN48XFC7/I6 |
| Device | GW1N-1P5 |
| Device Version | C |
| Created Time | Thu Nov 28 14:53:02 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 1.71V 85C C7/I6 |
| Hold Delay Model | Fast 3.6V 0C C7/I6 |
| Numbers of Paths Analyzed | 316 |
| Numbers of Endpoints Analyzed | 251 |
| Numbers of Falling Endpoints | 0 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk27mhz | Base | 37.037 | 27.000 | 0.000 | 18.518 | clk | ||
| 2 | clk160hz | Generated | 9999990.000 | 0.000 | 0.000 | 4999995.000 | clk | clk27mhz | clk160hz |
| 3 | clk400hz | Generated | 2499997.500 | 0.000 | 0.000 | 1249998.750 | clk | clk27mhz | clk400hz |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk27mhz | 27.000(MHz) | 122.920(MHz) | 5 | TOP |
| 2 | clk160hz | 0.000(MHz) | 250.000(MHz) | 2 | TOP |
| 3 | clk400hz | 0.000(MHz) | 444.444(MHz) | 2 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| clk27mhz | Setup | 0.000 | 0 |
| clk27mhz | Hold | 0.000 | 0 |
| clk160hz | Setup | 0.000 | 0 |
| clk160hz | Hold | 0.000 | 0 |
| clk400hz | Setup | 0.000 | 0 |
| clk400hz | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 28.902 | clkdiv_1/count_5_s0/Q | run_led_1/led_1_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 8.103 |
| 2 | 29.183 | clkdiv_1/count_5_s0/Q | run_led_1/led_7_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.822 |
| 3 | 29.183 | clkdiv_1/count_5_s0/Q | run_led_1/led_6_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.822 |
| 4 | 29.208 | clkdiv_1/count_5_s0/Q | run_led_1/led_0_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.797 |
| 5 | 29.254 | clkdiv_1/count_5_s0/Q | run_led_1/count_0_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.751 |
| 6 | 29.460 | clkdiv_1/count_5_s0/Q | run_led_1/count_1_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.545 |
| 7 | 29.460 | clkdiv_1/count_5_s0/Q | run_led_1/count_2_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.545 |
| 8 | 29.513 | clkdiv_1/count_5_s0/Q | run_led_1/led_4_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.492 |
| 9 | 29.513 | clkdiv_1/count_5_s0/Q | run_led_1/led_5_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.492 |
| 10 | 29.516 | clkdiv_1/count_5_s0/Q | run_led_1/led_2_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.489 |
| 11 | 29.516 | clkdiv_1/count_5_s0/Q | run_led_1/led_3_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.489 |
| 12 | 29.527 | clkdiv_1/count_5_s0/Q | cntr4max_1/cnt_0_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.478 |
| 13 | 29.527 | clkdiv_1/count_5_s0/Q | cntr4max_1/cnt_1_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.478 |
| 14 | 29.677 | clkdiv_1/count_5_s0/Q | cntr4max_3/cnt_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.064 |
| 15 | 29.740 | clkdiv_1/count_5_s0/Q | cntr4max_3/cnt_3_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.265 |
| 16 | 29.740 | clkdiv_1/count_5_s0/Q | cntr4max_3/cnt_0_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.265 |
| 17 | 29.740 | clkdiv_1/count_5_s0/Q | cntr4max_3/cnt_1_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.265 |
| 18 | 29.740 | clkdiv_1/count_5_s0/Q | cntr4max_3/cnt_2_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.265 |
| 19 | 29.804 | clkdiv_1/count_5_s0/Q | cntr4max_1/cnt_3_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.201 |
| 20 | 29.804 | clkdiv_1/count_5_s0/Q | cntr4max_1/cnt_2_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 7.201 |
| 21 | 29.809 | clkdiv_1/count_5_s0/Q | clkdiv_1/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.931 |
| 22 | 29.859 | clkdiv_1/count_5_s0/Q | cntr4max_1/cnt_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.882 |
| 23 | 29.859 | clkdiv_1/count_5_s0/Q | cntr4max_1/cnt_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.882 |
| 24 | 29.862 | clkdiv_1/count_5_s0/Q | cntr4max_1/cnt_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.878 |
| 25 | 29.862 | clkdiv_1/count_5_s0/Q | cntr4max_1/cnt_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.878 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.524 | clkdiv_3/count_12_s0/Q | clkdiv_3/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 2 | 0.524 | clkdiv_2/count_5_s0/Q | clkdiv_2/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 3 | 0.524 | clkdiv_2/count_10_s0/Q | clkdiv_2/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 4 | 0.524 | clkdiv_1/count_3_s0/Q | clkdiv_1/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 5 | 0.524 | clkdiv_1/count_12_s0/Q | clkdiv_1/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 6 | 0.524 | clkdiv_1/count_14_s0/Q | clkdiv_1/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 7 | 0.525 | toggle_2/out_s0/Q | toggle_2/out_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 8 | 0.525 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 9 | 0.525 | clkdiv_3/count_11_s0/Q | clkdiv_3/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 10 | 0.525 | clkdiv_3/count_14_s0/Q | clkdiv_3/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 11 | 0.525 | clkdiv_2/count_7_s0/Q | clkdiv_2/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 12 | 0.525 | clkdiv_1/count_7_s0/Q | clkdiv_1/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 13 | 0.525 | clkdiv_1/count_13_s0/Q | clkdiv_1/count_13_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 14 | 0.526 | cntr4max_3/cnt_2_s0/Q | cntr4max_3/cnt_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 15 | 0.526 | cntr4max_1/cnt_1_s0/Q | cntr4max_1/cnt_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 16 | 0.526 | clkdiv_3/count_3_s0/Q | clkdiv_3/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 17 | 0.526 | clkdiv_3/count_16_s0/Q | clkdiv_3/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 18 | 0.526 | clkdiv_2/count_4_s0/Q | clkdiv_2/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 19 | 0.527 | cntr4max_2/cnt_0_s1/Q | cntr4max_2/cnt_0_s1/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.527 |
| 20 | 0.528 | inst20/col_1_s0/Q | inst20/col_1_s0/D | clk160hz:[R] | clk160hz:[R] | 0.000 | 0.000 | 0.528 |
| 21 | 0.528 | run_led_1/count_2_s0/Q | run_led_1/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.528 |
| 22 | 0.528 | cntr4max_2/cnt_1_s0/Q | cntr4max_2/cnt_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.528 |
| 23 | 0.528 | cntr4max_1/cnt_2_s0/Q | cntr4max_1/cnt_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.528 |
| 24 | 0.528 | cntr4maxe_1/cnt_0_s1/Q | cntr4maxe_1/cnt_0_s1/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.528 |
| 25 | 0.662 | clkdiv_3/count_13_s0/Q | clkdiv_3/count_13_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.662 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/count_18_s0 |
| 2 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/count_16_s0 |
| 3 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/count_12_s0 |
| 4 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/count_4_s0 |
| 5 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_2/count_5_s0 |
| 6 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | cntr4max_1/cnt_1_s0 |
| 7 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | cntr4max_1/cnt_2_s0 |
| 8 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_2/count_6_s0 |
| 9 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_0_s1 |
| 10 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_3_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 28.902 |
| Data Arrival Time | 10.372 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/led_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 10.372 | 1.761 | tNET | RR | 1 | IOR17[A] | run_led_1/led_1_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | IOR17[A] | run_led_1/led_1_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | IOR17[A] | run_led_1/led_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 31.933%; route: 5.176, 63.876%; tC2Q: 0.340, 4.191% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path2
Path Summary:
| Slack | 29.183 |
| Data Arrival Time | 10.091 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/led_7_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 10.091 | 1.480 | tNET | RR | 1 | IOB18[A] | run_led_1/led_7_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | IOB18[A] | run_led_1/led_7_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | IOB18[A] | run_led_1/led_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 33.079%; route: 4.895, 62.579%; tC2Q: 0.340, 4.342% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path3
Path Summary:
| Slack | 29.183 |
| Data Arrival Time | 10.091 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/led_6_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 10.091 | 1.480 | tNET | RR | 1 | IOB18[B] | run_led_1/led_6_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | IOB18[B] | run_led_1/led_6_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | IOB18[B] | run_led_1/led_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 33.079%; route: 4.895, 62.579%; tC2Q: 0.340, 4.342% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path4
Path Summary:
| Slack | 29.208 |
| Data Arrival Time | 10.066 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/led_0_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 10.066 | 1.454 | tNET | RR | 1 | IOR15[B] | run_led_1/led_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | IOR15[B] | run_led_1/led_0_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | IOR15[B] | run_led_1/led_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 33.188%; route: 4.870, 62.456%; tC2Q: 0.340, 4.356% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path5
Path Summary:
| Slack | 29.254 |
| Data Arrival Time | 10.019 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/count_0_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 10.019 | 1.408 | tNET | RR | 1 | R13C12[0][B] | run_led_1/count_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R13C12[0][B] | run_led_1/count_0_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R13C12[0][B] | run_led_1/count_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 33.386%; route: 4.823, 62.232%; tC2Q: 0.340, 4.382% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path6
Path Summary:
| Slack | 29.460 |
| Data Arrival Time | 9.814 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/count_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 9.814 | 1.203 | tNET | RR | 1 | R12C12[0][B] | run_led_1/count_1_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C12[0][B] | run_led_1/count_1_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R12C12[0][B] | run_led_1/count_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 34.295%; route: 4.618, 61.204%; tC2Q: 0.340, 4.501% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path7
Path Summary:
| Slack | 29.460 |
| Data Arrival Time | 9.814 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/count_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 9.814 | 1.203 | tNET | RR | 1 | R12C12[0][A] | run_led_1/count_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C12[0][A] | run_led_1/count_2_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R12C12[0][A] | run_led_1/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 34.295%; route: 4.618, 61.204%; tC2Q: 0.340, 4.501% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path8
Path Summary:
| Slack | 29.513 |
| Data Arrival Time | 9.761 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/led_4_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 9.761 | 1.149 | tNET | RR | 1 | IOB5[A] | run_led_1/led_4_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | IOB5[A] | run_led_1/led_4_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | IOB5[A] | run_led_1/led_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 34.538%; route: 4.565, 60.928%; tC2Q: 0.340, 4.533% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path9
Path Summary:
| Slack | 29.513 |
| Data Arrival Time | 9.761 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/led_5_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 9.761 | 1.149 | tNET | RR | 1 | IOB5[B] | run_led_1/led_5_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | IOB5[B] | run_led_1/led_5_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | IOB5[B] | run_led_1/led_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 34.538%; route: 4.565, 60.928%; tC2Q: 0.340, 4.533% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path10
Path Summary:
| Slack | 29.516 |
| Data Arrival Time | 9.758 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/led_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 9.758 | 1.147 | tNET | RR | 1 | IOT14[B] | run_led_1/led_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | IOT14[B] | run_led_1/led_2_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | IOT14[B] | run_led_1/led_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 34.550%; route: 4.562, 60.915%; tC2Q: 0.340, 4.535% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path11
Path Summary:
| Slack | 29.516 |
| Data Arrival Time | 9.758 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | run_led_1/led_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 9.758 | 1.147 | tNET | RR | 1 | IOT14[A] | run_led_1/led_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | IOT14[A] | run_led_1/led_3_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | IOT14[A] | run_led_1/led_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 34.550%; route: 4.562, 60.915%; tC2Q: 0.340, 4.535% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path12
Path Summary:
| Slack | 29.527 |
| Data Arrival Time | 9.747 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_1/cnt_0_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 9.747 | 1.136 | tNET | RR | 1 | R12C10[0][B] | cntr4max_1/cnt_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C10[0][B] | cntr4max_1/cnt_0_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R12C10[0][B] | cntr4max_1/cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 34.602%; route: 4.551, 60.857%; tC2Q: 0.340, 4.542% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path13
Path Summary:
| Slack | 29.527 |
| Data Arrival Time | 9.747 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_1/cnt_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 9.747 | 1.136 | tNET | RR | 1 | R12C10[0][A] | cntr4max_1/cnt_1_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C10[0][A] | cntr4max_1/cnt_1_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R12C10[0][A] | cntr4max_1/cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 34.602%; route: 4.551, 60.857%; tC2Q: 0.340, 4.542% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path14
Path Summary:
| Slack | 29.677 |
| Data Arrival Time | 9.333 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_3/cnt_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.518 | 1.375 | tNET | FF | 1 | R11C9[1][A] | cntr4max_3/n17_s2/I0 |
| 9.333 | 0.814 | tINS | FF | 1 | R11C9[1][A] | cntr4max_3/n17_s2/F |
| 9.333 | 0.000 | tNET | FF | 1 | R11C9[1][A] | cntr4max_3/cnt_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C9[1][A] | cntr4max_3/cnt_2_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C9[1][A] | cntr4max_3/cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.808, 39.746%; route: 3.917, 55.446%; tC2Q: 0.340, 4.808% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path15
Path Summary:
| Slack | 29.740 |
| Data Arrival Time | 9.533 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_3/cnt_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.518 | 1.375 | tNET | FF | 1 | R11C9[2][A] | cntr4max_2/clk10s_s2/I0 |
| 9.279 | 0.760 | tINS | FR | 4 | R11C9[2][A] | cntr4max_2/clk10s_s2/F |
| 9.533 | 0.255 | tNET | RR | 1 | R11C9[0][A] | cntr4max_3/cnt_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C9[0][A] | cntr4max_3/cnt_3_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R11C9[0][A] | cntr4max_3/cnt_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.754, 37.904%; route: 4.171, 57.421%; tC2Q: 0.340, 4.675% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path16
Path Summary:
| Slack | 29.740 |
| Data Arrival Time | 9.533 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_3/cnt_0_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.518 | 1.375 | tNET | FF | 1 | R11C9[2][A] | cntr4max_2/clk10s_s2/I0 |
| 9.279 | 0.760 | tINS | FR | 4 | R11C9[2][A] | cntr4max_2/clk10s_s2/F |
| 9.533 | 0.255 | tNET | RR | 1 | R11C9[0][B] | cntr4max_3/cnt_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C9[0][B] | cntr4max_3/cnt_0_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R11C9[0][B] | cntr4max_3/cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.754, 37.904%; route: 4.171, 57.421%; tC2Q: 0.340, 4.675% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path17
Path Summary:
| Slack | 29.740 |
| Data Arrival Time | 9.533 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_3/cnt_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.518 | 1.375 | tNET | FF | 1 | R11C9[2][A] | cntr4max_2/clk10s_s2/I0 |
| 9.279 | 0.760 | tINS | FR | 4 | R11C9[2][A] | cntr4max_2/clk10s_s2/F |
| 9.533 | 0.255 | tNET | RR | 1 | R11C9[1][B] | cntr4max_3/cnt_1_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C9[1][B] | cntr4max_3/cnt_1_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R11C9[1][B] | cntr4max_3/cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.754, 37.904%; route: 4.171, 57.421%; tC2Q: 0.340, 4.675% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path18
Path Summary:
| Slack | 29.740 |
| Data Arrival Time | 9.533 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_3/cnt_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.518 | 1.375 | tNET | FF | 1 | R11C9[2][A] | cntr4max_2/clk10s_s2/I0 |
| 9.279 | 0.760 | tINS | FR | 4 | R11C9[2][A] | cntr4max_2/clk10s_s2/F |
| 9.533 | 0.255 | tNET | RR | 1 | R11C9[1][A] | cntr4max_3/cnt_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C9[1][A] | cntr4max_3/cnt_2_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R11C9[1][A] | cntr4max_3/cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.754, 37.904%; route: 4.171, 57.421%; tC2Q: 0.340, 4.675% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path19
Path Summary:
| Slack | 29.804 |
| Data Arrival Time | 9.469 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_1/cnt_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 9.469 | 0.858 | tNET | RR | 1 | R11C10[0][B] | cntr4max_1/cnt_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C10[0][B] | cntr4max_1/cnt_3_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R11C10[0][B] | cntr4max_1/cnt_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 35.935%; route: 4.274, 59.349%; tC2Q: 0.340, 4.717% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path20
Path Summary:
| Slack | 29.804 |
| Data Arrival Time | 9.469 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_1/cnt_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.017 | 0.874 | tNET | FF | 1 | R7C6[3][A] | run_led_1/n7_s0/I0 |
| 8.611 | 0.594 | tINS | FR | 15 | R7C6[3][A] | run_led_1/n7_s0/F |
| 9.469 | 0.858 | tNET | RR | 1 | R11C10[0][A] | cntr4max_1/cnt_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C10[0][A] | cntr4max_1/cnt_2_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R11C10[0][A] | cntr4max_1/cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.588, 35.935%; route: 4.274, 59.349%; tC2Q: 0.340, 4.717% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path21
Path Summary:
| Slack | 29.809 |
| Data Arrival Time | 9.200 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_5_s0 |
| To | clkdiv_1/count_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.386 | 1.242 | tNET | FF | 1 | R11C10[2][B] | clkdiv_1/n61_s2/I2 |
| 9.200 | 0.814 | tINS | FF | 1 | R11C10[2][B] | clkdiv_1/n61_s2/F |
| 9.200 | 0.000 | tNET | FF | 1 | R11C10[2][B] | clkdiv_1/count_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C10[2][B] | clkdiv_1/count_1_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C10[2][B] | clkdiv_1/count_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.808, 40.507%; route: 3.784, 54.593%; tC2Q: 0.340, 4.900% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path22
Path Summary:
| Slack | 29.859 |
| Data Arrival Time | 9.150 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_1/cnt_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.386 | 1.242 | tNET | FF | 1 | R11C10[0][B] | cntr4max_1/n16_s2/I1 |
| 9.150 | 0.765 | tINS | FF | 1 | R11C10[0][B] | cntr4max_1/n16_s2/F |
| 9.150 | 0.000 | tNET | FF | 1 | R11C10[0][B] | cntr4max_1/cnt_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C10[0][B] | cntr4max_1/cnt_3_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C10[0][B] | cntr4max_1/cnt_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.758, 40.078%; route: 3.784, 54.987%; tC2Q: 0.340, 4.935% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path23
Path Summary:
| Slack | 29.859 |
| Data Arrival Time | 9.150 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_1/cnt_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.386 | 1.242 | tNET | FF | 1 | R11C10[0][A] | cntr4max_1/n17_s2/I0 |
| 9.150 | 0.765 | tINS | FF | 1 | R11C10[0][A] | cntr4max_1/n17_s2/F |
| 9.150 | 0.000 | tNET | FF | 1 | R11C10[0][A] | cntr4max_1/cnt_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C10[0][A] | cntr4max_1/cnt_2_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C10[0][A] | cntr4max_1/cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.758, 40.078%; route: 3.784, 54.987%; tC2Q: 0.340, 4.935% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path24
Path Summary:
| Slack | 29.862 |
| Data Arrival Time | 9.147 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_1/cnt_0_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.382 | 1.239 | tNET | FF | 1 | R12C10[0][B] | cntr4max_1/n19_s3/I1 |
| 9.147 | 0.765 | tINS | FF | 1 | R12C10[0][B] | cntr4max_1/n19_s3/F |
| 9.147 | 0.000 | tNET | FF | 1 | R12C10[0][B] | cntr4max_1/cnt_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C10[0][B] | cntr4max_1/cnt_0_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C10[0][B] | cntr4max_1/cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.758, 40.098%; route: 3.781, 54.965%; tC2Q: 0.340, 4.938% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path25
Path Summary:
| Slack | 29.862 |
| Data Arrival Time | 9.147 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_5_s0 |
| To | cntr4max_1/cnt_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R9C7[0][B] | clkdiv_1/count_5_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 4 | R9C7[0][B] | clkdiv_1/count_5_s0/Q |
| 4.180 | 1.572 | tNET | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/I1 |
| 4.945 | 0.765 | tINS | FF | 1 | R9C7[3][B] | cntr4maxe_1/active_s6/F |
| 5.541 | 0.596 | tNET | FF | 1 | R8C8[1][A] | cntr4maxe_1/active_s2/I0 |
| 6.305 | 0.765 | tINS | FF | 4 | R8C8[1][A] | cntr4maxe_1/active_s2/F |
| 6.679 | 0.374 | tNET | FF | 1 | R8C6[2][A] | cntr4maxe_1/active_s10/I0 |
| 7.143 | 0.464 | tINS | FF | 36 | R8C6[2][A] | cntr4maxe_1/active_s10/F |
| 8.382 | 1.239 | tNET | FF | 1 | R12C10[0][A] | cntr4max_1/n18_s2/I0 |
| 9.147 | 0.765 | tINS | FF | 1 | R12C10[0][A] | cntr4max_1/n18_s2/F |
| 9.147 | 0.000 | tNET | FF | 1 | R12C10[0][A] | cntr4max_1/cnt_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C10[0][A] | cntr4max_1/cnt_1_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C10[0][A] | cntr4max_1/cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.758, 40.098%; route: 3.781, 54.965%; tC2Q: 0.340, 4.938% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_12_s0 |
| To | clkdiv_3/count_12_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C11[0][A] | clkdiv_3/count_12_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 4 | R8C11[0][A] | clkdiv_3/count_12_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R8C11[0][A] | clkdiv_3/n50_s2/I2 |
| 2.053 | 0.276 | tINS | RF | 1 | R8C11[0][A] | clkdiv_3/n50_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R8C11[0][A] | clkdiv_3/count_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C11[0][A] | clkdiv_3/count_12_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C11[0][A] | clkdiv_3/count_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path2
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_5_s0 |
| To | clkdiv_2/count_5_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R13C14[0][A] | clkdiv_2/count_5_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R13C14[0][A] | clkdiv_2/count_5_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R13C14[0][A] | clkdiv_2/n57_s2/I3 |
| 2.053 | 0.276 | tINS | RF | 1 | R13C14[0][A] | clkdiv_2/n57_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R13C14[0][A] | clkdiv_2/count_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R13C14[0][A] | clkdiv_2/count_5_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R13C14[0][A] | clkdiv_2/count_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path3
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_10_s0 |
| To | clkdiv_2/count_10_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C14[0][A] | clkdiv_2/count_10_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R11C14[0][A] | clkdiv_2/count_10_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R11C14[0][A] | clkdiv_2/n52_s2/I1 |
| 2.053 | 0.276 | tINS | RF | 1 | R11C14[0][A] | clkdiv_2/n52_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R11C14[0][A] | clkdiv_2/count_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C14[0][A] | clkdiv_2/count_10_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C14[0][A] | clkdiv_2/count_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path4
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_3_s0 |
| To | clkdiv_1/count_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C7[1][A] | clkdiv_1/count_3_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 2 | R9C7[1][A] | clkdiv_1/count_3_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R9C7[1][A] | clkdiv_1/n59_s2/I2 |
| 2.053 | 0.276 | tINS | RF | 1 | R9C7[1][A] | clkdiv_1/n59_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R9C7[1][A] | clkdiv_1/count_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C7[1][A] | clkdiv_1/count_3_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C7[1][A] | clkdiv_1/count_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path5
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_12_s0 |
| To | clkdiv_1/count_12_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C7[0][A] | clkdiv_1/count_12_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 2 | R8C7[0][A] | clkdiv_1/count_12_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R8C7[0][A] | clkdiv_1/n50_s2/I2 |
| 2.053 | 0.276 | tINS | RF | 1 | R8C7[0][A] | clkdiv_1/n50_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R8C7[0][A] | clkdiv_1/count_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C7[0][A] | clkdiv_1/count_12_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C7[0][A] | clkdiv_1/count_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path6
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_14_s0 |
| To | clkdiv_1/count_14_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C8[1][A] | clkdiv_1/count_14_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R7C8[1][A] | clkdiv_1/count_14_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R7C8[1][A] | clkdiv_1/n48_s2/I0 |
| 2.053 | 0.276 | tINS | RF | 1 | R7C8[1][A] | clkdiv_1/n48_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R7C8[1][A] | clkdiv_1/count_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C8[1][A] | clkdiv_1/count_14_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C8[1][A] | clkdiv_1/count_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path7
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | toggle_2/out_s0 |
| To | toggle_2/out_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C11[0][A] | toggle_2/out_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 7 | R9C11[0][A] | toggle_2/out_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R9C11[0][A] | toggle_2/n10_s1/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R9C11[0][A] | toggle_2/n10_s1/F |
| 2.054 | 0.000 | tNET | FF | 1 | R9C11[0][A] | toggle_2/out_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C11[0][A] | toggle_2/out_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C11[0][A] | toggle_2/out_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path8
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_1_s0 |
| To | clkdiv_3/count_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C14[1][A] | clkdiv_3/count_1_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R8C14[1][A] | clkdiv_3/count_1_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R8C14[1][A] | clkdiv_3/n61_s2/I1 |
| 2.054 | 0.276 | tINS | RF | 1 | R8C14[1][A] | clkdiv_3/n61_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R8C14[1][A] | clkdiv_3/count_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C14[1][A] | clkdiv_3/count_1_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C14[1][A] | clkdiv_3/count_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path9
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_11_s0 |
| To | clkdiv_3/count_11_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C11[0][A] | clkdiv_3/count_11_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R7C11[0][A] | clkdiv_3/count_11_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R7C11[0][A] | clkdiv_3/n51_s2/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R7C11[0][A] | clkdiv_3/n51_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R7C11[0][A] | clkdiv_3/count_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C11[0][A] | clkdiv_3/count_11_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C11[0][A] | clkdiv_3/count_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path10
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_14_s0 |
| To | clkdiv_3/count_14_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C13[0][A] | clkdiv_3/count_14_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R8C13[0][A] | clkdiv_3/count_14_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R8C13[0][A] | clkdiv_3/n48_s2/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R8C13[0][A] | clkdiv_3/n48_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R8C13[0][A] | clkdiv_3/count_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C13[0][A] | clkdiv_3/count_14_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C13[0][A] | clkdiv_3/count_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path11
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_7_s0 |
| To | clkdiv_2/count_7_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C14[1][A] | clkdiv_2/count_7_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R11C14[1][A] | clkdiv_2/count_7_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R11C14[1][A] | clkdiv_2/n55_s2/I1 |
| 2.054 | 0.276 | tINS | RF | 1 | R11C14[1][A] | clkdiv_2/n55_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R11C14[1][A] | clkdiv_2/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C14[1][A] | clkdiv_2/count_7_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C14[1][A] | clkdiv_2/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path12
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_7_s0 |
| To | clkdiv_1/count_7_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C8[1][A] | clkdiv_1/count_7_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R9C8[1][A] | clkdiv_1/count_7_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R9C8[1][A] | clkdiv_1/n55_s2/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R9C8[1][A] | clkdiv_1/n55_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R9C8[1][A] | clkdiv_1/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C8[1][A] | clkdiv_1/count_7_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C8[1][A] | clkdiv_1/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path13
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_13_s0 |
| To | clkdiv_1/count_13_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C7[0][A] | clkdiv_1/count_13_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 4 | R7C7[0][A] | clkdiv_1/count_13_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R7C7[0][A] | clkdiv_1/n49_s2/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R7C7[0][A] | clkdiv_1/n49_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R7C7[0][A] | clkdiv_1/count_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C7[0][A] | clkdiv_1/count_13_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C7[0][A] | clkdiv_1/count_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path14
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | cntr4max_3/cnt_2_s0 |
| To | cntr4max_3/cnt_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C9[1][A] | cntr4max_3/cnt_2_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 16 | R11C9[1][A] | cntr4max_3/cnt_2_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R11C9[1][A] | cntr4max_3/n17_s2/I3 |
| 2.055 | 0.276 | tINS | RF | 1 | R11C9[1][A] | cntr4max_3/n17_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R11C9[1][A] | cntr4max_3/cnt_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C9[1][A] | cntr4max_3/cnt_2_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C9[1][A] | cntr4max_3/cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path15
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | cntr4max_1/cnt_1_s0 |
| To | cntr4max_1/cnt_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R12C10[0][A] | cntr4max_1/cnt_1_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 18 | R12C10[0][A] | cntr4max_1/cnt_1_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R12C10[0][A] | cntr4max_1/n18_s2/I3 |
| 2.055 | 0.276 | tINS | RF | 1 | R12C10[0][A] | cntr4max_1/n18_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R12C10[0][A] | cntr4max_1/cnt_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R12C10[0][A] | cntr4max_1/cnt_1_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R12C10[0][A] | cntr4max_1/cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path16
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_3_s0 |
| To | clkdiv_3/count_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C13[1][A] | clkdiv_3/count_3_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 4 | R8C13[1][A] | clkdiv_3/count_3_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R8C13[1][A] | clkdiv_3/n59_s2/I2 |
| 2.055 | 0.276 | tINS | RF | 1 | R8C13[1][A] | clkdiv_3/n59_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R8C13[1][A] | clkdiv_3/count_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C13[1][A] | clkdiv_3/count_3_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C13[1][A] | clkdiv_3/count_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path17
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_16_s0 |
| To | clkdiv_3/count_16_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[1][A] | clkdiv_3/count_16_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R8C10[1][A] | clkdiv_3/count_16_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R8C10[1][A] | clkdiv_3/n46_s3/I2 |
| 2.055 | 0.276 | tINS | RF | 1 | R8C10[1][A] | clkdiv_3/n46_s3/F |
| 2.055 | 0.000 | tNET | FF | 1 | R8C10[1][A] | clkdiv_3/count_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[1][A] | clkdiv_3/count_16_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C10[1][A] | clkdiv_3/count_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path18
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_4_s0 |
| To | clkdiv_2/count_4_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R13C14[1][A] | clkdiv_2/count_4_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 7 | R13C14[1][A] | clkdiv_2/count_4_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R13C14[1][A] | clkdiv_2/n58_s2/I1 |
| 2.055 | 0.276 | tINS | RF | 1 | R13C14[1][A] | clkdiv_2/n58_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R13C14[1][A] | clkdiv_2/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R13C14[1][A] | clkdiv_2/count_4_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R13C14[1][A] | clkdiv_2/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path19
Path Summary:
| Slack | 0.527 |
| Data Arrival Time | 2.056 |
| Data Required Time | 1.529 |
| From | cntr4max_2/cnt_0_s1 |
| To | cntr4max_2/cnt_0_s1 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C9[0][A] | cntr4max_2/cnt_0_s1/CLK |
| 1.776 | 0.247 | tC2Q | RR | 18 | R8C9[0][A] | cntr4max_2/cnt_0_s1/Q |
| 1.780 | 0.004 | tNET | RR | 1 | R8C9[0][A] | cntr4max_2/n19_s6/I1 |
| 2.056 | 0.276 | tINS | RF | 1 | R8C9[0][A] | cntr4max_2/n19_s6/F |
| 2.056 | 0.000 | tNET | FF | 1 | R8C9[0][A] | cntr4max_2/cnt_0_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C9[0][A] | cntr4max_2/cnt_0_s1/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C9[0][A] | cntr4max_2/cnt_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path20
Path Summary:
| Slack | 0.528 |
| Data Arrival Time | 1.055 |
| Data Required Time | 0.527 |
| From | inst20/col_1_s0 |
| To | inst20/col_1_s0 |
| Launch Clk | clk160hz:[R] |
| Latch Clk | clk160hz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk160hz | ||||
| 0.000 | 0.000 | tCL | RR | 14 | R8C12[2][A] | clkdiv_3/clk_out_s0/Q |
| 0.527 | 0.527 | tNET | RR | 1 | R13C6[0][A] | inst20/col_1_s0/CLK |
| 0.774 | 0.247 | tC2Q | RR | 13 | R13C6[0][A] | inst20/col_1_s0/Q |
| 0.780 | 0.005 | tNET | RR | 1 | R13C6[0][A] | inst20/n11_s2/I0 |
| 1.055 | 0.276 | tINS | RF | 1 | R13C6[0][A] | inst20/n11_s2/F |
| 1.055 | 0.000 | tNET | FF | 1 | R13C6[0][A] | inst20/col_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk160hz | ||||
| 0.000 | 0.000 | tCL | RR | 14 | R8C12[2][A] | clkdiv_3/clk_out_s0/Q |
| 0.527 | 0.527 | tNET | RR | 1 | R13C6[0][A] | inst20/col_1_s0/CLK |
| 0.527 | 0.000 | tHld | 1 | R13C6[0][A] | inst20/col_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.527, 100.000% |
| Arrival Data Path Delay | cell: 0.276, 52.217%; route: 0.005, 0.994%; tC2Q: 0.247, 46.789% |
| Required Clock Path Delay | cell: 0.000, 0.000%; route: 0.527, 100.000% |
Path21
Path Summary:
| Slack | 0.528 |
| Data Arrival Time | 2.057 |
| Data Required Time | 1.529 |
| From | run_led_1/count_2_s0 |
| To | run_led_1/count_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R12C12[0][A] | run_led_1/count_2_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 16 | R12C12[0][A] | run_led_1/count_2_s0/Q |
| 1.781 | 0.005 | tNET | RR | 1 | R12C12[0][A] | run_led_1/n9_s1/I0 |
| 2.057 | 0.276 | tINS | RF | 1 | R12C12[0][A] | run_led_1/n9_s1/F |
| 2.057 | 0.000 | tNET | FF | 1 | R12C12[0][A] | run_led_1/count_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R12C12[0][A] | run_led_1/count_2_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R12C12[0][A] | run_led_1/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.217%; route: 0.005, 0.994%; tC2Q: 0.247, 46.789% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path22
Path Summary:
| Slack | 0.528 |
| Data Arrival Time | 2.057 |
| Data Required Time | 1.529 |
| From | cntr4max_2/cnt_1_s0 |
| To | cntr4max_2/cnt_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C9[1][A] | cntr4max_2/cnt_1_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 17 | R9C9[1][A] | cntr4max_2/cnt_1_s0/Q |
| 1.781 | 0.005 | tNET | RR | 1 | R9C9[1][A] | cntr4max_2/n18_s2/I3 |
| 2.057 | 0.276 | tINS | RF | 1 | R9C9[1][A] | cntr4max_2/n18_s2/F |
| 2.057 | 0.000 | tNET | FF | 1 | R9C9[1][A] | cntr4max_2/cnt_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C9[1][A] | cntr4max_2/cnt_1_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C9[1][A] | cntr4max_2/cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.217%; route: 0.005, 0.994%; tC2Q: 0.247, 46.789% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path23
Path Summary:
| Slack | 0.528 |
| Data Arrival Time | 2.057 |
| Data Required Time | 1.529 |
| From | cntr4max_1/cnt_2_s0 |
| To | cntr4max_1/cnt_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C10[0][A] | cntr4max_1/cnt_2_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 17 | R11C10[0][A] | cntr4max_1/cnt_2_s0/Q |
| 1.781 | 0.005 | tNET | RR | 1 | R11C10[0][A] | cntr4max_1/n17_s2/I2 |
| 2.057 | 0.276 | tINS | RF | 1 | R11C10[0][A] | cntr4max_1/n17_s2/F |
| 2.057 | 0.000 | tNET | FF | 1 | R11C10[0][A] | cntr4max_1/cnt_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C10[0][A] | cntr4max_1/cnt_2_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C10[0][A] | cntr4max_1/cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.217%; route: 0.005, 0.994%; tC2Q: 0.247, 46.789% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path24
Path Summary:
| Slack | 0.528 |
| Data Arrival Time | 2.057 |
| Data Required Time | 1.529 |
| From | cntr4maxe_1/cnt_0_s1 |
| To | cntr4maxe_1/cnt_0_s1 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C6[1][A] | cntr4maxe_1/cnt_0_s1/CLK |
| 1.776 | 0.247 | tC2Q | RR | 18 | R7C6[1][A] | cntr4maxe_1/cnt_0_s1/Q |
| 1.781 | 0.005 | tNET | RR | 1 | R7C6[1][A] | cntr4maxe_1/n17_s5/I0 |
| 2.057 | 0.276 | tINS | RF | 1 | R7C6[1][A] | cntr4maxe_1/n17_s5/F |
| 2.057 | 0.000 | tNET | FF | 1 | R7C6[1][A] | cntr4maxe_1/cnt_0_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C6[1][A] | cntr4maxe_1/cnt_0_s1/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C6[1][A] | cntr4maxe_1/cnt_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.217%; route: 0.005, 0.994%; tC2Q: 0.247, 46.789% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path25
Path Summary:
| Slack | 0.662 |
| Data Arrival Time | 2.190 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_13_s0 |
| To | clkdiv_3/count_13_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C13[2][A] | clkdiv_3/count_13_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R8C13[2][A] | clkdiv_3/count_13_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R8C13[2][A] | clkdiv_3/n49_s2/I0 |
| 2.190 | 0.412 | tINS | RR | 1 | R8C13[2][A] | clkdiv_3/n49_s2/F |
| 2.190 | 0.000 | tNET | RR | 1 | R8C13[2][A] | clkdiv_3/count_13_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 84 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C13[2][A] | clkdiv_3/count_13_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C13[2][A] | clkdiv_3/count_13_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.412, 62.271%; route: 0.003, 0.397%; tC2Q: 0.247, 37.333% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_1/count_18_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_18_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_18_s0/CLK |
MPW2
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_1/count_16_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_16_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_16_s0/CLK |
MPW3
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_1/count_12_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_12_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_12_s0/CLK |
MPW4
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_1/count_4_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_4_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_4_s0/CLK |
MPW5
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_2/count_5_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_2/count_5_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_2/count_5_s0/CLK |
MPW6
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | cntr4max_1/cnt_1_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | cntr4max_1/cnt_1_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | cntr4max_1/cnt_1_s0/CLK |
MPW7
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | cntr4max_1/cnt_2_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | cntr4max_1/cnt_2_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | cntr4max_1/cnt_2_s0/CLK |
MPW8
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_2/count_6_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_2/count_6_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_2/count_6_s0/CLK |
MPW9
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | cntr4maxe_1/cnt_0_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | cntr4maxe_1/cnt_0_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | cntr4maxe_1/cnt_0_s1/CLK |
MPW10
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | cntr4maxe_1/cnt_3_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | cntr4maxe_1/cnt_3_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | cntr4maxe_1/cnt_3_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 84 | clk_d | 28.902 | 0.195 |
| 36 | active_15 | 28.902 | 1.375 |
| 22 | clk400hz | 2499995.250 | 1.420 |
| 21 | col[0] | 9999986.000 | 0.976 |
| 19 | cnt10hz[0] | 31.982 | 1.105 |
| 18 | cnt100hz[0] | 32.068 | 1.348 |
| 18 | cnt10hz[1] | 32.087 | 0.982 |
| 18 | cnt10s[0] | 33.925 | 0.996 |
| 18 | cnt1s[0] | 33.656 | 1.462 |
| 17 | cnt100hz[1] | 31.909 | 1.227 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R13C14 | 79.17% |
| R8C10 | 72.22% |
| R11C9 | 68.06% |
| R7C6 | 63.89% |
| R8C13 | 63.89% |
| R11C10 | 62.50% |
| R11C14 | 61.11% |
| R8C6 | 58.33% |
| R9C9 | 58.33% |
| R8C7 | 56.94% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk160hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 270000 [get_nets {clk160hz}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk400hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 67500 [get_nets {clk400hz}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk27mhz}] -group [get_clocks {clk400hz}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk27mhz}] -group [get_clocks {clk160hz}] |