PnR Messages

Report Title PnR Report
Design File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\impl\gwsynthesis\matrix_key.vg
Physical Constraints File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\src\matrix_key.cst
Timing Constraints File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\matrix_key\src\matrix_key.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Thu Dec 19 16:26:53 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

PnR Details

Place & Route Process Running placement: Placement Phase 0: CPU time = 0h 0m 0.007s, Elapsed time = 0h 0m 0.007s Placement Phase 1: CPU time = 0h 0m 0.028s, Elapsed time = 0h 0m 0.028s Placement Phase 2: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0.001s Placement Phase 3: CPU time = 0h 0m 0.316s, Elapsed time = 0h 0m 0.316s Total Placement: CPU time = 0h 0m 0.352s, Elapsed time = 0h 0m 0.352s Running routing: Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Routing Phase 1: CPU time = 0h 0m 0.03s, Elapsed time = 0h 0m 0.03s Routing Phase 2: CPU time = 0h 0m 0.04s, Elapsed time = 0h 0m 0.039s Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s Total Routing: CPU time = 0h 0m 0.07s, Elapsed time = 0h 0m 0.069s Generate output files: CPU time = 0h 0m 0.17s, Elapsed time = 0h 0m 0.17s
Total Time and Memory Usage CPU time = 0h 0m 0.592s, Elapsed time = 0h 0m 0.591s, Peak memory usage = 187MB

Resource

Resource Usage Summary:

Resource Usage Utilization
Logic 122/1584 8%
    --LUT,ALU,ROM16 122(122 LUT, 0 ALU, 0 ROM16) -
    --SSRAM(RAM16) 0 -
Register 61/1704 4%
    --Logic Register as Latch 0/1584 0%
    --Logic Register as FF 56/1584 4%
    --I/O Register as Latch 0/120 0%
    --I/O Register as FF 5/120 5%
I/O Port 23/40 58%
I/O Buf 23 -
    --Input Buf 6 -
    --Output Buf 17 -
    --Inout Buf 0 -

I/O Bank Usage Summary:

I/O Bank UsageUtilization
bank 0 2/1020%
bank 1 5/1050%
bank 2 6/1060%
bank 3 2/2100%
bank 4 4/4100%
bank 5 4/4100%

Clock Resource Usage Summary:

Clock Resource Usage Utilization
PRIMARY 2/8 25%
LW 0/8 0%
GCLK_PIN 4/6 67%

Global Clock Signals:

Signal Global Clock Location
clk_d PRIMARY RIGHT
clk50hz PRIMARY LEFT RIGHT

Pinout by Port Name:

Port Name Diff Pair Loc./Bank Constraint Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor BankVccio
clk - 4/5 Y in IOL6[A] LVCMOS33 NA NONE ON NONE NA NA NA NA 3.3
nrst - 35/1 Y in IOR1[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
row[0] - 7/4 Y in IOL11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
row[1] - 5/5 Y in IOL6[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
row[2] - 3/5 Y in IOL4[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
row[3] - 2/5 Y in IOL4[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
col[0] - 8/4 Y out IOL11[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
col[1] - 9/4 Y out IOL12[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
col[2] - 10/4 Y out IOL12[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
col[3] - 11/3 Y out IOL17[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[0] - 26/1 Y out IOR17[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[1] - 21/2 Y out IOB9[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[2] - 20/2 Y out IOB9[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[3] - 19/2 Y out IOB7[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[4] - 18/2 Y out IOB7[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[5] - 15/2 Y out IOB2[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[6] - 14/2 Y out IOB2[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
seg[7] - 12/3 Y out IOL17[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
dig[0] - 31/1 Y out IOR13[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
dig[1] - 29/1 Y out IOR15[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
dig[2] - 40/0 Y out IOT15[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
dig[3] - 41/0 Y out IOT15[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
ready - 28/1 Y out IOR15[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3

All Package Pins:

Loc./Bank Signal Dir. Site IO Type Drive Pull Mode PCI Clamp Hysteresis Open Drain Vref Single Resistor Diff Resistor Bank Vccio
48/0 - out IOT7[A] LVCMOS33 8 NONE NA NA OFF NA NA NA 3.3
47/0 - in IOT7[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
45/0 - in IOT9[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
44/0 - in IOT9[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
43/0 - in IOT14[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
42/0 - in IOT14[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
41/0 dig[3] out IOT15[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
40/0 dig[2] out IOT15[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
38/0 - in IOT18[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
37/0 - in IOT18[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
14/2 seg[6] out IOB2[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
15/2 seg[5] out IOB2[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
16/2 - in IOB5[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
17/2 - in IOB5[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
18/2 seg[4] out IOB7[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
19/2 seg[3] out IOB7[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
20/2 seg[2] out IOB9[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
21/2 seg[1] out IOB9[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
23/2 - in IOB18[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
24/2 - in IOB18[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
2/5 row[3] in IOL4[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
3/5 row[2] in IOL4[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
4/5 clk in IOL6[A] LVCMOS33 NA NONE ON NONE NA NA NA NA 3.3
5/5 row[1] in IOL6[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
7/4 row[0] in IOL11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
8/4 col[0] out IOL11[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
9/4 col[1] out IOL12[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
10/4 col[2] out IOL12[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
11/3 col[3] out IOL17[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
12/3 seg[7] out IOL17[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
36/1 - in IOR1[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
35/1 nrst in IOR1[B] LVCMOS33 NA UP ON NONE NA NA OFF NA 3.3
34/1 - in IOR11[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
33/1 - in IOR11[B] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
32/1 - in IOR13[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
31/1 dig[0] out IOR13[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
29/1 dig[1] out IOR15[A] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
28/1 ready out IOR15[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3
27/1 - in IOR17[A] LVCMOS33 NA UP ON NONE NA NA NA NA 3.3
26/1 seg[0] out IOR17[B] LVCMOS33 8 UP NA NA OFF NA NA NA 3.3