Timing Messages
| Report Title | Timing Analysis Report |
| Design File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\impl\gwsynthesis\stopwatch.vg |
| Physical Constraints File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\stopwatch.cst |
| Timing Constraint File | C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\stopwatch\src\stopwatch.sdc |
| Tool Version | V1.9.10.03 (64-bit) |
| Part Number | GW1N-UV1P5QN48XFC7/I6 |
| Device | GW1N-1P5 |
| Device Version | C |
| Created Time | Wed Dec 18 11:39:50 2024 |
| Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
| Setup Delay Model | Slow 1.71V 85C C7/I6 |
| Hold Delay Model | Fast 3.6V 0C C7/I6 |
| Numbers of Paths Analyzed | 279 |
| Numbers of Endpoints Analyzed | 230 |
| Numbers of Falling Endpoints | 0 |
| Numbers of Setup Violated Endpoints | 0 |
| Numbers of Hold Violated Endpoints | 0 |
Clock Summary:
| NO. | Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
|---|---|---|---|---|---|---|---|---|---|
| 1 | clk27mhz | Base | 37.037 | 27.000 | 0.000 | 18.518 | clk | ||
| 2 | clk160hz | Generated | 6249993.500 | 0.000 | 0.000 | 3124996.750 | clk | clk27mhz | clk160hz |
| 3 | clk400hz | Generated | 2499997.500 | 0.000 | 0.000 | 1249998.750 | clk | clk27mhz | clk400hz |
Max Frequency Summary:
| NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
|---|---|---|---|---|---|
| 1 | clk27mhz | 27.000(MHz) | 142.707(MHz) | 5 | TOP |
| 2 | clk160hz | 0.000(MHz) | 250.000(MHz) | 2 | TOP |
| 3 | clk400hz | 0.000(MHz) | 444.444(MHz) | 2 | TOP |
Total Negative Slack Summary:
| Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
|---|---|---|---|
| clk27mhz | Setup | 0.000 | 0 |
| clk27mhz | Hold | 0.000 | 0 |
| clk160hz | Setup | 0.000 | 0 |
| clk160hz | Hold | 0.000 | 0 |
| clk400hz | Setup | 0.000 | 0 |
| clk400hz | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 30.030 | clkdiv_1/count_16_s0/Q | cntr4max_4/cnt_0_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.975 |
| 2 | 30.030 | clkdiv_1/count_16_s0/Q | cntr4max_4/cnt_2_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.975 |
| 3 | 30.241 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.500 |
| 4 | 30.251 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.489 |
| 5 | 30.251 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.489 |
| 6 | 30.289 | clkdiv_1/count_16_s0/Q | cntr4max_4/cnt_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.451 |
| 7 | 30.302 | clkdiv_1/count_16_s0/Q | cntr4max_4/cnt_3_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.703 |
| 8 | 30.302 | clkdiv_1/count_16_s0/Q | cntr4max_4/cnt_1_s0/CE | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.703 |
| 9 | 30.363 | clkdiv_1/count_16_s0/Q | cntr4max_4/cnt_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.377 |
| 10 | 30.363 | clkdiv_1/count_16_s0/Q | cntr4max_2/cnt_0_s1/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.377 |
| 11 | 30.367 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_12_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.374 |
| 12 | 30.367 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_18_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.374 |
| 13 | 30.367 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_10_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.373 |
| 14 | 30.367 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.373 |
| 15 | 30.420 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_17_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.321 |
| 16 | 30.493 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.247 |
| 17 | 30.497 | clkdiv_1/count_16_s0/Q | cntr4max_4/cnt_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.244 |
| 18 | 30.497 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.244 |
| 19 | 30.570 | clkdiv_1/count_16_s0/Q | cntr4max_2/cnt_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.170 |
| 20 | 30.575 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.165 |
| 21 | 30.580 | clkdiv_1/count_16_s0/Q | cntr4max_2/cnt_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.160 |
| 22 | 30.591 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.149 |
| 23 | 30.632 | clkdiv_1/count_9_s0/Q | clkdiv_1/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.108 |
| 24 | 30.707 | cntr4maxe_1/cnt_1_s0/Q | cntr4max_3/cnt_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.034 |
| 25 | 30.707 | cntr4maxe_1/cnt_1_s0/Q | cntr4max_3/cnt_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 37.037 | 0.000 | 6.034 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
| Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
|---|---|---|---|---|---|---|---|---|
| 1 | 0.524 | clkdiv_3/count_1_s0/Q | clkdiv_3/count_1_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 2 | 0.524 | clkdiv_2/count_8_s0/Q | clkdiv_2/count_8_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 3 | 0.524 | clkdiv_2/count_9_s0/Q | clkdiv_2/count_9_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 4 | 0.524 | clkdiv_1/count_3_s0/Q | clkdiv_1/count_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 5 | 0.524 | clkdiv_1/count_11_s0/Q | clkdiv_1/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.524 |
| 6 | 0.525 | clkdiv_3/count_2_s0/Q | clkdiv_3/count_2_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 7 | 0.525 | clkdiv_3/count_6_s0/Q | clkdiv_3/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 8 | 0.525 | clkdiv_3/count_15_s0/Q | clkdiv_3/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 9 | 0.525 | clkdiv_2/count_11_s0/Q | clkdiv_2/count_11_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 10 | 0.525 | clkdiv_2/count_14_s0/Q | clkdiv_2/count_14_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 11 | 0.525 | clkdiv_2/count_15_s0/Q | clkdiv_2/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 12 | 0.525 | clkdiv_1/count_15_s0/Q | clkdiv_1/count_15_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 13 | 0.525 | clkdiv_1/count_16_s0/Q | clkdiv_1/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 14 | 0.525 | clkdiv_1/count_18_s0/Q | clkdiv_1/count_18_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.525 |
| 15 | 0.526 | clkdiv_3/count_7_s0/Q | clkdiv_3/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 16 | 0.526 | clkdiv_2/count_5_s0/Q | clkdiv_2/count_5_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 17 | 0.526 | clkdiv_1/count_0_s0/Q | clkdiv_1/count_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 18 | 0.526 | clkdiv_1/count_4_s0/Q | clkdiv_1/count_4_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 19 | 0.526 | clkdiv_1/count_6_s0/Q | clkdiv_1/count_6_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 20 | 0.526 | clkdiv_1/count_7_s0/Q | clkdiv_1/count_7_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.526 |
| 21 | 0.527 | cntr4max_4/cnt_0_s0/Q | cntr4max_4/cnt_0_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.527 |
| 22 | 0.527 | cntr4maxe_1/cnt_0_s1/Q | cntr4maxe_1/cnt_0_s1/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.527 |
| 23 | 0.527 | toggle_2/out_s0/Q | toggle_2/out_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.527 |
| 24 | 0.527 | clkdiv_3/count_16_s0/Q | clkdiv_3/count_16_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.527 |
| 25 | 0.528 | cntr4max_4/cnt_3_s0/Q | cntr4max_4/cnt_3_s0/D | clk27mhz:[R] | clk27mhz:[R] | 0.000 | 0.000 | 0.528 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
| Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
|---|---|---|---|---|---|---|
| 1 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/count_18_s0 |
| 2 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/count_16_s0 |
| 3 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/count_12_s0 |
| 4 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_1/count_4_s0 |
| 5 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_2/count_5_s0 |
| 6 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | cntr4max_1/cnt_1_s0 |
| 7 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | cntr4max_1/cnt_2_s0 |
| 8 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | clkdiv_2/count_6_s0 |
| 9 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_0_s1 |
| 10 | 16.613 | 17.539 | 0.926 | Low Pulse Width | clk27mhz | cntr4maxe_1/cnt_3_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 30.030 |
| Data Arrival Time | 9.244 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_16_s0 |
| To | cntr4max_4/cnt_0_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.955 | 1.142 | tNET | FF | 1 | R12C14[2][B] | cntr4max_3/clk1m_s2/I0 |
| 8.716 | 0.760 | tINS | FR | 4 | R12C14[2][B] | cntr4max_3/clk1m_s2/F |
| 9.244 | 0.528 | tNET | RR | 1 | R11C14[0][A] | cntr4max_4/cnt_0_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C14[0][A] | cntr4max_4/cnt_0_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R11C14[0][A] | cntr4max_4/cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.899, 41.558%; route: 3.737, 53.573%; tC2Q: 0.340, 4.869% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path2
Path Summary:
| Slack | 30.030 |
| Data Arrival Time | 9.244 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_16_s0 |
| To | cntr4max_4/cnt_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.955 | 1.142 | tNET | FF | 1 | R12C14[2][B] | cntr4max_3/clk1m_s2/I0 |
| 8.716 | 0.760 | tINS | FR | 4 | R12C14[2][B] | cntr4max_3/clk1m_s2/F |
| 9.244 | 0.528 | tNET | RR | 1 | R11C14[1][A] | cntr4max_4/cnt_2_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C14[1][A] | cntr4max_4/cnt_2_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R11C14[1][A] | cntr4max_4/cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.899, 41.558%; route: 3.737, 53.573%; tC2Q: 0.340, 4.869% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path3
Path Summary:
| Slack | 30.241 |
| Data Arrival Time | 8.769 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_5_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.954 | 1.141 | tNET | FF | 1 | R9C9[2][A] | clkdiv_1/n57_s2/I3 |
| 8.769 | 0.814 | tINS | FF | 1 | R9C9[2][A] | clkdiv_1/n57_s2/F |
| 8.769 | 0.000 | tNET | FF | 1 | R9C9[2][A] | clkdiv_1/count_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R9C9[2][A] | clkdiv_1/count_5_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R9C9[2][A] | clkdiv_1/count_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.953, 45.431%; route: 3.207, 49.344%; tC2Q: 0.340, 5.225% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path4
Path Summary:
| Slack | 30.251 |
| Data Arrival Time | 8.758 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_7_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.944 | 1.130 | tNET | FF | 1 | R9C8[0][A] | clkdiv_1/n55_s2/I2 |
| 8.758 | 0.814 | tINS | FF | 1 | R9C8[0][A] | clkdiv_1/n55_s2/F |
| 8.758 | 0.000 | tNET | FF | 1 | R9C8[0][A] | clkdiv_1/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/count_7_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R9C8[0][A] | clkdiv_1/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.953, 45.505%; route: 3.197, 49.261%; tC2Q: 0.340, 5.234% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path5
Path Summary:
| Slack | 30.251 |
| Data Arrival Time | 8.758 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_15_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.944 | 1.130 | tNET | FF | 1 | R8C8[0][A] | clkdiv_1/n47_s2/I3 |
| 8.758 | 0.814 | tINS | FF | 1 | R8C8[0][A] | clkdiv_1/n47_s2/F |
| 8.758 | 0.000 | tNET | FF | 1 | R8C8[0][A] | clkdiv_1/count_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R8C8[0][A] | clkdiv_1/count_15_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R8C8[0][A] | clkdiv_1/count_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.953, 45.505%; route: 3.197, 49.261%; tC2Q: 0.340, 5.234% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path6
Path Summary:
| Slack | 30.289 |
| Data Arrival Time | 8.720 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | cntr4max_4/cnt_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.955 | 1.142 | tNET | FF | 1 | R12C14[0][A] | cntr4max_4/n16_s2/I1 |
| 8.720 | 0.765 | tINS | FF | 1 | R12C14[0][A] | cntr4max_4/n16_s2/F |
| 8.720 | 0.000 | tNET | FF | 1 | R12C14[0][A] | cntr4max_4/cnt_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C14[0][A] | cntr4max_4/cnt_3_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C14[0][A] | cntr4max_4/cnt_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.903, 45.003%; route: 3.208, 49.733%; tC2Q: 0.340, 5.265% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path7
Path Summary:
| Slack | 30.302 |
| Data Arrival Time | 8.972 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_16_s0 |
| To | cntr4max_4/cnt_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.955 | 1.142 | tNET | FF | 1 | R12C14[2][B] | cntr4max_3/clk1m_s2/I0 |
| 8.716 | 0.760 | tINS | FR | 4 | R12C14[2][B] | cntr4max_3/clk1m_s2/F |
| 8.972 | 0.256 | tNET | RR | 1 | R12C14[0][A] | cntr4max_4/cnt_3_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C14[0][A] | cntr4max_4/cnt_3_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R12C14[0][A] | cntr4max_4/cnt_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.899, 43.247%; route: 3.464, 51.686%; tC2Q: 0.340, 5.067% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path8
Path Summary:
| Slack | 30.302 |
| Data Arrival Time | 8.972 |
| Data Required Time | 39.274 |
| From | clkdiv_1/count_16_s0 |
| To | cntr4max_4/cnt_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.955 | 1.142 | tNET | FF | 1 | R12C14[2][B] | cntr4max_3/clk1m_s2/I0 |
| 8.716 | 0.760 | tINS | FR | 4 | R12C14[2][B] | cntr4max_3/clk1m_s2/F |
| 8.972 | 0.256 | tNET | RR | 1 | R12C14[3][A] | cntr4max_4/cnt_1_s0/CE |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C14[3][A] | cntr4max_4/cnt_1_s0/CLK |
| 39.274 | -0.032 | tSu | 1 | R12C14[3][A] | cntr4max_4/cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.899, 43.247%; route: 3.464, 51.686%; tC2Q: 0.340, 5.067% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path9
Path Summary:
| Slack | 30.363 |
| Data Arrival Time | 8.646 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | cntr4max_4/cnt_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 8.182 | 1.369 | tNET | FF | 1 | R12C14[3][A] | cntr4max_4/n18_s2/I0 |
| 8.646 | 0.464 | tINS | FF | 1 | R12C14[3][A] | cntr4max_4/n18_s2/F |
| 8.646 | 0.000 | tNET | FF | 1 | R12C14[3][A] | cntr4max_4/cnt_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C14[3][A] | cntr4max_4/cnt_1_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C14[3][A] | cntr4max_4/cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.602, 40.806%; route: 3.435, 53.869%; tC2Q: 0.340, 5.325% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path10
Path Summary:
| Slack | 30.363 |
| Data Arrival Time | 8.646 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | cntr4max_2/cnt_0_s1 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 8.182 | 1.369 | tNET | FF | 1 | R12C14[1][B] | cntr4max_2/n19_s6/I0 |
| 8.646 | 0.464 | tINS | FF | 1 | R12C14[1][B] | cntr4max_2/n19_s6/F |
| 8.646 | 0.000 | tNET | FF | 1 | R12C14[1][B] | cntr4max_2/cnt_0_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C14[1][B] | cntr4max_2/cnt_0_s1/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C14[1][B] | cntr4max_2/cnt_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.602, 40.806%; route: 3.435, 53.869%; tC2Q: 0.340, 5.325% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path11
Path Summary:
| Slack | 30.367 |
| Data Arrival Time | 8.643 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_12_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.828 | 1.015 | tNET | FF | 1 | R7C8[2][A] | clkdiv_1/n50_s2/I2 |
| 8.643 | 0.814 | tINS | FF | 1 | R7C8[2][A] | clkdiv_1/n50_s2/F |
| 8.643 | 0.000 | tNET | FF | 1 | R7C8[2][A] | clkdiv_1/count_12_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R7C8[2][A] | clkdiv_1/count_12_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R7C8[2][A] | clkdiv_1/count_12_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.953, 46.328%; route: 3.081, 48.344%; tC2Q: 0.340, 5.328% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path12
Path Summary:
| Slack | 30.367 |
| Data Arrival Time | 8.643 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_18_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.828 | 1.015 | tNET | FF | 1 | R7C8[1][A] | clkdiv_1/n44_s2/I3 |
| 8.643 | 0.814 | tINS | FF | 1 | R7C8[1][A] | clkdiv_1/n44_s2/F |
| 8.643 | 0.000 | tNET | FF | 1 | R7C8[1][A] | clkdiv_1/count_18_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R7C8[1][A] | clkdiv_1/count_18_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R7C8[1][A] | clkdiv_1/count_18_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.953, 46.328%; route: 3.081, 48.344%; tC2Q: 0.340, 5.328% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path13
Path Summary:
| Slack | 30.367 |
| Data Arrival Time | 8.642 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_10_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.828 | 1.015 | tNET | FF | 1 | R7C9[2][A] | clkdiv_1/n52_s4/I3 |
| 8.642 | 0.814 | tINS | FF | 1 | R7C9[2][A] | clkdiv_1/n52_s4/F |
| 8.642 | 0.000 | tNET | FF | 1 | R7C9[2][A] | clkdiv_1/count_10_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R7C9[2][A] | clkdiv_1/count_10_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R7C9[2][A] | clkdiv_1/count_10_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.953, 46.332%; route: 3.081, 48.339%; tC2Q: 0.340, 5.329% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path14
Path Summary:
| Slack | 30.367 |
| Data Arrival Time | 8.642 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_11_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.828 | 1.015 | tNET | FF | 1 | R7C9[1][A] | clkdiv_1/n51_s2/I3 |
| 8.642 | 0.814 | tINS | FF | 1 | R7C9[1][A] | clkdiv_1/n51_s2/F |
| 8.642 | 0.000 | tNET | FF | 1 | R7C9[1][A] | clkdiv_1/count_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R7C9[1][A] | clkdiv_1/count_11_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R7C9[1][A] | clkdiv_1/count_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.953, 46.332%; route: 3.081, 48.339%; tC2Q: 0.340, 5.329% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path15
Path Summary:
| Slack | 30.420 |
| Data Arrival Time | 8.590 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_17_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.825 | 1.012 | tNET | FF | 1 | R7C8[1][B] | clkdiv_1/n45_s2/I2 |
| 8.590 | 0.765 | tINS | FF | 1 | R7C8[1][B] | clkdiv_1/n45_s2/F |
| 8.590 | 0.000 | tNET | FF | 1 | R7C8[1][B] | clkdiv_1/count_17_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R7C8[1][B] | clkdiv_1/count_17_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R7C8[1][B] | clkdiv_1/count_17_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.903, 45.931%; route: 3.078, 48.696%; tC2Q: 0.340, 5.373% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path16
Path Summary:
| Slack | 30.493 |
| Data Arrival Time | 8.516 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_6_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.702 | 0.889 | tNET | FF | 1 | R9C9[1][A] | clkdiv_1/n56_s2/I3 |
| 8.516 | 0.814 | tINS | FF | 1 | R9C9[1][A] | clkdiv_1/n56_s2/F |
| 8.516 | 0.000 | tNET | FF | 1 | R9C9[1][A] | clkdiv_1/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R9C9[1][A] | clkdiv_1/count_6_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R9C9[1][A] | clkdiv_1/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.953, 47.266%; route: 2.955, 47.297%; tC2Q: 0.340, 5.436% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path17
Path Summary:
| Slack | 30.497 |
| Data Arrival Time | 8.513 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | cntr4max_4/cnt_0_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.698 | 0.885 | tNET | FF | 1 | R11C14[0][A] | cntr4max_4/n19_s3/I0 |
| 8.513 | 0.814 | tINS | FF | 1 | R11C14[0][A] | cntr4max_4/n19_s3/F |
| 8.513 | 0.000 | tNET | FF | 1 | R11C14[0][A] | cntr4max_4/cnt_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C14[0][A] | cntr4max_4/cnt_0_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C14[0][A] | cntr4max_4/cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.953, 47.292%; route: 2.951, 47.269%; tC2Q: 0.340, 5.439% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path18
Path Summary:
| Slack | 30.497 |
| Data Arrival Time | 8.513 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.698 | 0.885 | tNET | FF | 1 | R8C9[1][A] | clkdiv_1/n59_s2/I3 |
| 8.513 | 0.814 | tINS | FF | 1 | R8C9[1][A] | clkdiv_1/n59_s2/F |
| 8.513 | 0.000 | tNET | FF | 1 | R8C9[1][A] | clkdiv_1/count_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R8C9[1][A] | clkdiv_1/count_3_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R8C9[1][A] | clkdiv_1/count_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.953, 47.292%; route: 2.951, 47.269%; tC2Q: 0.340, 5.439% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path19
Path Summary:
| Slack | 30.570 |
| Data Arrival Time | 8.439 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | cntr4max_2/cnt_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.830 | 1.017 | tNET | FF | 1 | R12C13[1][B] | cntr4max_2/n17_s2/I0 |
| 8.439 | 0.609 | tINS | FF | 1 | R12C13[1][B] | cntr4max_2/n17_s2/F |
| 8.439 | 0.000 | tNET | FF | 1 | R12C13[1][B] | cntr4max_2/cnt_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C13[1][B] | cntr4max_2/cnt_2_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C13[1][B] | cntr4max_2/cnt_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.748, 44.530%; route: 3.083, 49.966%; tC2Q: 0.340, 5.504% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path20
Path Summary:
| Slack | 30.575 |
| Data Arrival Time | 8.434 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_4_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.825 | 1.012 | tNET | FF | 1 | R9C10[0][A] | clkdiv_1/n58_s2/I2 |
| 8.434 | 0.609 | tINS | FF | 1 | R9C10[0][A] | clkdiv_1/n58_s2/F |
| 8.434 | 0.000 | tNET | FF | 1 | R9C10[0][A] | clkdiv_1/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R9C10[0][A] | clkdiv_1/count_4_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R9C10[0][A] | clkdiv_1/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.748, 44.566%; route: 3.078, 49.925%; tC2Q: 0.340, 5.509% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path21
Path Summary:
| Slack | 30.580 |
| Data Arrival Time | 8.429 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | cntr4max_2/cnt_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.820 | 1.007 | tNET | FF | 1 | R12C13[3][A] | cntr4max_2/n18_s2/I0 |
| 8.429 | 0.609 | tINS | FF | 1 | R12C13[3][A] | cntr4max_2/n18_s2/F |
| 8.429 | 0.000 | tNET | FF | 1 | R12C13[3][A] | cntr4max_2/cnt_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R12C13[3][A] | cntr4max_2/cnt_1_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R12C13[3][A] | cntr4max_2/cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.748, 44.602%; route: 3.073, 49.885%; tC2Q: 0.340, 5.513% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path22
Path Summary:
| Slack | 30.591 |
| Data Arrival Time | 8.418 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_8_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 3.695 | 1.086 | tNET | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/I2 |
| 4.304 | 0.609 | tINS | FF | 1 | R7C8[3][B] | cntr4maxe_1/active_s7/F |
| 4.308 | 0.004 | tNET | FF | 1 | R7C8[0][B] | cntr4maxe_1/active_s4/I0 |
| 5.073 | 0.765 | tINS | FF | 4 | R7C8[0][B] | cntr4maxe_1/active_s4/F |
| 6.048 | 0.976 | tNET | FF | 1 | R7C13[0][B] | cntr4maxe_1/active_s10/I2 |
| 6.813 | 0.765 | tINS | FF | 41 | R7C13[0][B] | cntr4maxe_1/active_s10/F |
| 7.954 | 1.141 | tNET | FF | 1 | R9C9[0][B] | clkdiv_1/n54_s2/I3 |
| 8.418 | 0.464 | tINS | FF | 1 | R9C9[0][B] | clkdiv_1/n54_s2/F |
| 8.418 | 0.000 | tNET | FF | 1 | R9C9[0][B] | clkdiv_1/count_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R9C9[0][B] | clkdiv_1/count_8_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R9C9[0][B] | clkdiv_1/count_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.602, 42.320%; route: 3.207, 52.157%; tC2Q: 0.340, 5.523% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path23
Path Summary:
| Slack | 30.632 |
| Data Arrival Time | 8.377 |
| Data Required Time | 39.009 |
| From | clkdiv_1/count_9_s0 |
| To | clkdiv_1/count_16_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R7C8[2][B] | clkdiv_1/count_9_s0/CLK |
| 2.608 | 0.340 | tC2Q | RR | 5 | R7C8[2][B] | clkdiv_1/count_9_s0/Q |
| 2.928 | 0.320 | tNET | RR | 1 | R7C9[3][A] | clkdiv_1/n49_s4/I0 |
| 3.693 | 0.765 | tINS | RF | 2 | R7C9[3][A] | clkdiv_1/n49_s4/F |
| 4.538 | 0.845 | tNET | FF | 1 | R8C9[1][B] | clkdiv_1/n49_s3/I0 |
| 5.303 | 0.765 | tINS | FF | 5 | R8C9[1][B] | clkdiv_1/n49_s3/F |
| 5.926 | 0.623 | tNET | FF | 1 | R8C8[0][B] | clkdiv_1/n46_s4/I1 |
| 6.535 | 0.609 | tINS | FF | 1 | R8C8[0][B] | clkdiv_1/n46_s4/F |
| 7.612 | 1.077 | tNET | FF | 1 | R7C13[0][A] | clkdiv_1/n46_s2/I1 |
| 8.377 | 0.765 | tINS | FF | 1 | R7C13[0][A] | clkdiv_1/n46_s2/F |
| 8.377 | 0.000 | tNET | FF | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R7C13[0][A] | clkdiv_1/count_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.903, 47.531%; route: 2.865, 46.909%; tC2Q: 0.340, 5.560% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path24
Path Summary:
| Slack | 30.707 |
| Data Arrival Time | 8.302 |
| Data Required Time | 39.009 |
| From | cntr4maxe_1/cnt_1_s0 |
| To | cntr4max_3/cnt_0_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R8C14[3][A] | cntr4maxe_1/cnt_1_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 17 | R8C14[3][A] | cntr4maxe_1/cnt_1_s0/Q |
| 3.701 | 1.093 | tNET | FF | 1 | R8C13[0][B] | cntr4maxe_1/clk10hz_s1/I1 |
| 4.296 | 0.594 | tINS | FR | 3 | R8C13[0][B] | cntr4maxe_1/clk10hz_s1/F |
| 4.609 | 0.313 | tNET | RR | 1 | R9C13[1][A] | cntr4max_1/clk1s_s0/I0 |
| 5.073 | 0.464 | tINS | RF | 11 | R9C13[1][A] | cntr4max_1/clk1s_s0/F |
| 6.051 | 0.978 | tNET | FF | 1 | R12C14[2][A] | cntr4max_3/clk1m_s0/I2 |
| 6.865 | 0.814 | tINS | FF | 8 | R12C14[2][A] | cntr4max_3/clk1m_s0/F |
| 7.488 | 0.623 | tNET | FF | 1 | R11C13[2][B] | cntr4max_3/n19_s3/I0 |
| 8.302 | 0.814 | tINS | FF | 1 | R11C13[2][B] | cntr4max_3/n19_s3/F |
| 8.302 | 0.000 | tNET | FF | 1 | R11C13[2][B] | cntr4max_3/cnt_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C13[2][B] | cntr4max_3/cnt_0_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C13[2][B] | cntr4max_3/cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.687, 44.532%; route: 3.007, 49.839%; tC2Q: 0.340, 5.629% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Path25
Path Summary:
| Slack | 30.707 |
| Data Arrival Time | 8.302 |
| Data Required Time | 39.009 |
| From | cntr4maxe_1/cnt_1_s0 |
| To | cntr4max_3/cnt_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 2.088 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 2.269 | 0.181 | tNET | RR | 1 | R8C14[3][A] | cntr4maxe_1/cnt_1_s0/CLK |
| 2.608 | 0.340 | tC2Q | RF | 17 | R8C14[3][A] | cntr4maxe_1/cnt_1_s0/Q |
| 3.701 | 1.093 | tNET | FF | 1 | R8C13[0][B] | cntr4maxe_1/clk10hz_s1/I1 |
| 4.296 | 0.594 | tINS | FR | 3 | R8C13[0][B] | cntr4maxe_1/clk10hz_s1/F |
| 4.609 | 0.313 | tNET | RR | 1 | R9C13[1][A] | cntr4max_1/clk1s_s0/I0 |
| 5.073 | 0.464 | tINS | RF | 11 | R9C13[1][A] | cntr4max_1/clk1s_s0/F |
| 6.051 | 0.978 | tNET | FF | 1 | R12C14[2][A] | cntr4max_3/clk1m_s0/I2 |
| 6.865 | 0.814 | tINS | FF | 8 | R12C14[2][A] | cntr4max_3/clk1m_s0/F |
| 7.488 | 0.623 | tNET | FF | 1 | R11C13[2][A] | cntr4max_3/n18_s2/I1 |
| 8.302 | 0.814 | tINS | FF | 1 | R11C13[2][A] | cntr4max_3/n18_s2/F |
| 8.302 | 0.000 | tNET | FF | 1 | R11C13[2][A] | cntr4max_3/cnt_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 37.037 | 37.037 | active clock edge time | ||||
| 37.037 | 0.000 | clk27mhz | ||||
| 37.037 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 39.125 | 2.088 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 39.306 | 0.181 | tNET | RR | 1 | R11C13[2][A] | cntr4max_3/cnt_1_s0/CLK |
| 39.009 | -0.296 | tSu | 1 | R11C13[2][A] | cntr4max_3/cnt_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Setup Relationship | 37.037 |
| Logic Level | 5 |
| Arrival Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
| Arrival Data Path Delay | cell: 2.687, 44.532%; route: 3.007, 49.839%; tC2Q: 0.340, 5.629% |
| Required Clock Path Delay | cell: 2.088, 92.033%; route: 0.181, 7.967% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_1_s0 |
| To | clkdiv_3/count_1_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C7[0][A] | clkdiv_3/count_1_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R7C7[0][A] | clkdiv_3/count_1_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R7C7[0][A] | clkdiv_3/n61_s2/I1 |
| 2.053 | 0.276 | tINS | RF | 1 | R7C7[0][A] | clkdiv_3/n61_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R7C7[0][A] | clkdiv_3/count_1_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C7[0][A] | clkdiv_3/count_1_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C7[0][A] | clkdiv_3/count_1_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path2
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_8_s0 |
| To | clkdiv_2/count_8_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[0][A] | clkdiv_2/count_8_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R8C10[0][A] | clkdiv_2/count_8_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R8C10[0][A] | clkdiv_2/n54_s2/I3 |
| 2.053 | 0.276 | tINS | RF | 1 | R8C10[0][A] | clkdiv_2/n54_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R8C10[0][A] | clkdiv_2/count_8_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[0][A] | clkdiv_2/count_8_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C10[0][A] | clkdiv_2/count_8_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path3
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_9_s0 |
| To | clkdiv_2/count_9_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C11[0][A] | clkdiv_2/count_9_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R7C11[0][A] | clkdiv_2/count_9_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R7C11[0][A] | clkdiv_2/n53_s2/I1 |
| 2.053 | 0.276 | tINS | RF | 1 | R7C11[0][A] | clkdiv_2/n53_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R7C11[0][A] | clkdiv_2/count_9_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C11[0][A] | clkdiv_2/count_9_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C11[0][A] | clkdiv_2/count_9_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path4
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_3_s0 |
| To | clkdiv_1/count_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C9[1][A] | clkdiv_1/count_3_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 2 | R8C9[1][A] | clkdiv_1/count_3_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R8C9[1][A] | clkdiv_1/n59_s2/I2 |
| 2.053 | 0.276 | tINS | RF | 1 | R8C9[1][A] | clkdiv_1/n59_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R8C9[1][A] | clkdiv_1/count_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C9[1][A] | clkdiv_1/count_3_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C9[1][A] | clkdiv_1/count_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path5
Path Summary:
| Slack | 0.524 |
| Data Arrival Time | 2.053 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_11_s0 |
| To | clkdiv_1/count_11_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C9[1][A] | clkdiv_1/count_11_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R7C9[1][A] | clkdiv_1/count_11_s0/Q |
| 1.778 | 0.002 | tNET | RR | 1 | R7C9[1][A] | clkdiv_1/n51_s2/I2 |
| 2.053 | 0.276 | tINS | RF | 1 | R7C9[1][A] | clkdiv_1/n51_s2/F |
| 2.053 | 0.000 | tNET | FF | 1 | R7C9[1][A] | clkdiv_1/count_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C9[1][A] | clkdiv_1/count_11_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C9[1][A] | clkdiv_1/count_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.565%; route: 0.002, 0.334%; tC2Q: 0.247, 47.101% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path6
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_2_s0 |
| To | clkdiv_3/count_2_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C7[1][A] | clkdiv_3/count_2_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R9C7[1][A] | clkdiv_3/count_2_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R9C7[1][A] | clkdiv_3/n60_s4/I0 |
| 2.054 | 0.276 | tINS | RF | 1 | R9C7[1][A] | clkdiv_3/n60_s4/F |
| 2.054 | 0.000 | tNET | FF | 1 | R9C7[1][A] | clkdiv_3/count_2_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C7[1][A] | clkdiv_3/count_2_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C7[1][A] | clkdiv_3/count_2_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path7
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_6_s0 |
| To | clkdiv_3/count_6_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C7[0][A] | clkdiv_3/count_6_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R11C7[0][A] | clkdiv_3/count_6_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R11C7[0][A] | clkdiv_3/n56_s2/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R11C7[0][A] | clkdiv_3/n56_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R11C7[0][A] | clkdiv_3/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C7[0][A] | clkdiv_3/count_6_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C7[0][A] | clkdiv_3/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path8
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_15_s0 |
| To | clkdiv_3/count_15_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C6[0][A] | clkdiv_3/count_15_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 4 | R7C6[0][A] | clkdiv_3/count_15_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R7C6[0][A] | clkdiv_3/n47_s2/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R7C6[0][A] | clkdiv_3/n47_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R7C6[0][A] | clkdiv_3/count_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C6[0][A] | clkdiv_3/count_15_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C6[0][A] | clkdiv_3/count_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path9
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_11_s0 |
| To | clkdiv_2/count_11_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C11[0][A] | clkdiv_2/count_11_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R8C11[0][A] | clkdiv_2/count_11_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R8C11[0][A] | clkdiv_2/n51_s2/I3 |
| 2.054 | 0.276 | tINS | RF | 1 | R8C11[0][A] | clkdiv_2/n51_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R8C11[0][A] | clkdiv_2/count_11_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C11[0][A] | clkdiv_2/count_11_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C11[0][A] | clkdiv_2/count_11_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path10
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_14_s0 |
| To | clkdiv_2/count_14_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[1][A] | clkdiv_2/count_14_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R8C10[1][A] | clkdiv_2/count_14_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R8C10[1][A] | clkdiv_2/n48_s2/I3 |
| 2.054 | 0.276 | tINS | RF | 1 | R8C10[1][A] | clkdiv_2/n48_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R8C10[1][A] | clkdiv_2/count_14_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C10[1][A] | clkdiv_2/count_14_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C10[1][A] | clkdiv_2/count_14_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path11
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_15_s0 |
| To | clkdiv_2/count_15_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C11[1][A] | clkdiv_2/count_15_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R8C11[1][A] | clkdiv_2/count_15_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R8C11[1][A] | clkdiv_2/n47_s2/I1 |
| 2.054 | 0.276 | tINS | RF | 1 | R8C11[1][A] | clkdiv_2/n47_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R8C11[1][A] | clkdiv_2/count_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C11[1][A] | clkdiv_2/count_15_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C11[1][A] | clkdiv_2/count_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path12
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_15_s0 |
| To | clkdiv_1/count_15_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C8[0][A] | clkdiv_1/count_15_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 4 | R8C8[0][A] | clkdiv_1/count_15_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R8C8[0][A] | clkdiv_1/n47_s2/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R8C8[0][A] | clkdiv_1/n47_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R8C8[0][A] | clkdiv_1/count_15_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C8[0][A] | clkdiv_1/count_15_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C8[0][A] | clkdiv_1/count_15_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path13
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_16_s0 |
| To | clkdiv_1/count_16_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R7C13[0][A] | clkdiv_1/count_16_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/n46_s2/I0 |
| 2.054 | 0.276 | tINS | RF | 1 | R7C13[0][A] | clkdiv_1/n46_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C13[0][A] | clkdiv_1/count_16_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C13[0][A] | clkdiv_1/count_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path14
Path Summary:
| Slack | 0.525 |
| Data Arrival Time | 2.054 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_18_s0 |
| To | clkdiv_1/count_18_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C8[1][A] | clkdiv_1/count_18_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 3 | R7C8[1][A] | clkdiv_1/count_18_s0/Q |
| 1.778 | 0.003 | tNET | RR | 1 | R7C8[1][A] | clkdiv_1/n44_s2/I2 |
| 2.054 | 0.276 | tINS | RF | 1 | R7C8[1][A] | clkdiv_1/n44_s2/F |
| 2.054 | 0.000 | tNET | FF | 1 | R7C8[1][A] | clkdiv_1/count_18_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C8[1][A] | clkdiv_1/count_18_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C8[1][A] | clkdiv_1/count_18_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.478%; route: 0.003, 0.500%; tC2Q: 0.247, 47.023% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path15
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_7_s0 |
| To | clkdiv_3/count_7_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C7[0][A] | clkdiv_3/count_7_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R8C7[0][A] | clkdiv_3/count_7_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R8C7[0][A] | clkdiv_3/n55_s2/I0 |
| 2.055 | 0.276 | tINS | RF | 1 | R8C7[0][A] | clkdiv_3/n55_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R8C7[0][A] | clkdiv_3/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C7[0][A] | clkdiv_3/count_7_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C7[0][A] | clkdiv_3/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path16
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_2/count_5_s0 |
| To | clkdiv_2/count_5_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C11[1][A] | clkdiv_2/count_5_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R7C11[1][A] | clkdiv_2/count_5_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R7C11[1][A] | clkdiv_2/n57_s2/I3 |
| 2.055 | 0.276 | tINS | RF | 1 | R7C11[1][A] | clkdiv_2/n57_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R7C11[1][A] | clkdiv_2/count_5_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C11[1][A] | clkdiv_2/count_5_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C11[1][A] | clkdiv_2/count_5_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path17
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_0_s0 |
| To | clkdiv_1/count_0_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C9[0][A] | clkdiv_1/count_0_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R7C9[0][A] | clkdiv_1/count_0_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R7C9[0][A] | clkdiv_1/n62_s3/I0 |
| 2.055 | 0.276 | tINS | RF | 1 | R7C9[0][A] | clkdiv_1/n62_s3/F |
| 2.055 | 0.000 | tNET | FF | 1 | R7C9[0][A] | clkdiv_1/count_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R7C9[0][A] | clkdiv_1/count_0_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R7C9[0][A] | clkdiv_1/count_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path18
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_4_s0 |
| To | clkdiv_1/count_4_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C10[0][A] | clkdiv_1/count_4_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R9C10[0][A] | clkdiv_1/count_4_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R9C10[0][A] | clkdiv_1/n58_s2/I0 |
| 2.055 | 0.276 | tINS | RF | 1 | R9C10[0][A] | clkdiv_1/n58_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R9C10[0][A] | clkdiv_1/count_4_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C10[0][A] | clkdiv_1/count_4_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C10[0][A] | clkdiv_1/count_4_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path19
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_6_s0 |
| To | clkdiv_1/count_6_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C9[1][A] | clkdiv_1/count_6_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R9C9[1][A] | clkdiv_1/count_6_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R9C9[1][A] | clkdiv_1/n56_s2/I2 |
| 2.055 | 0.276 | tINS | RF | 1 | R9C9[1][A] | clkdiv_1/n56_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R9C9[1][A] | clkdiv_1/count_6_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C9[1][A] | clkdiv_1/count_6_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C9[1][A] | clkdiv_1/count_6_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path20
Path Summary:
| Slack | 0.526 |
| Data Arrival Time | 2.055 |
| Data Required Time | 1.529 |
| From | clkdiv_1/count_7_s0 |
| To | clkdiv_1/count_7_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/count_7_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 5 | R9C8[0][A] | clkdiv_1/count_7_s0/Q |
| 1.779 | 0.003 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/n55_s2/I0 |
| 2.055 | 0.276 | tINS | RF | 1 | R9C8[0][A] | clkdiv_1/n55_s2/F |
| 2.055 | 0.000 | tNET | FF | 1 | R9C8[0][A] | clkdiv_1/count_7_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C8[0][A] | clkdiv_1/count_7_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C8[0][A] | clkdiv_1/count_7_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.390%; route: 0.003, 0.665%; tC2Q: 0.247, 46.945% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path21
Path Summary:
| Slack | 0.527 |
| Data Arrival Time | 2.056 |
| Data Required Time | 1.529 |
| From | cntr4max_4/cnt_0_s0 |
| To | cntr4max_4/cnt_0_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C14[0][A] | cntr4max_4/cnt_0_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 9 | R11C14[0][A] | cntr4max_4/cnt_0_s0/Q |
| 1.780 | 0.004 | tNET | RR | 1 | R11C14[0][A] | cntr4max_4/n19_s3/I3 |
| 2.056 | 0.276 | tINS | RF | 1 | R11C14[0][A] | cntr4max_4/n19_s3/F |
| 2.056 | 0.000 | tNET | FF | 1 | R11C14[0][A] | cntr4max_4/cnt_0_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R11C14[0][A] | cntr4max_4/cnt_0_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R11C14[0][A] | cntr4max_4/cnt_0_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path22
Path Summary:
| Slack | 0.527 |
| Data Arrival Time | 2.056 |
| Data Required Time | 1.529 |
| From | cntr4maxe_1/cnt_0_s1 |
| To | cntr4maxe_1/cnt_0_s1 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C14[0][A] | cntr4maxe_1/cnt_0_s1/CLK |
| 1.776 | 0.247 | tC2Q | RR | 18 | R8C14[0][A] | cntr4maxe_1/cnt_0_s1/Q |
| 1.780 | 0.004 | tNET | RR | 1 | R8C14[0][A] | cntr4maxe_1/n17_s5/I0 |
| 2.056 | 0.276 | tINS | RF | 1 | R8C14[0][A] | cntr4maxe_1/n17_s5/F |
| 2.056 | 0.000 | tNET | FF | 1 | R8C14[0][A] | cntr4maxe_1/cnt_0_s1/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C14[0][A] | cntr4maxe_1/cnt_0_s1/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C14[0][A] | cntr4maxe_1/cnt_0_s1 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path23
Path Summary:
| Slack | 0.527 |
| Data Arrival Time | 2.056 |
| Data Required Time | 1.529 |
| From | toggle_2/out_s0 |
| To | toggle_2/out_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C13[1][A] | toggle_2/out_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 7 | R8C13[1][A] | toggle_2/out_s0/Q |
| 1.780 | 0.004 | tNET | RR | 1 | R8C13[1][A] | toggle_2/n10_s1/I2 |
| 2.056 | 0.276 | tINS | RF | 1 | R8C13[1][A] | toggle_2/n10_s1/F |
| 2.056 | 0.000 | tNET | FF | 1 | R8C13[1][A] | toggle_2/out_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R8C13[1][A] | toggle_2/out_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R8C13[1][A] | toggle_2/out_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path24
Path Summary:
| Slack | 0.527 |
| Data Arrival Time | 2.056 |
| Data Required Time | 1.529 |
| From | clkdiv_3/count_16_s0 |
| To | clkdiv_3/count_16_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C6[0][A] | clkdiv_3/count_16_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 6 | R9C6[0][A] | clkdiv_3/count_16_s0/Q |
| 1.780 | 0.004 | tNET | RR | 1 | R9C6[0][A] | clkdiv_3/n46_s4/I2 |
| 2.056 | 0.276 | tINS | RF | 1 | R9C6[0][A] | clkdiv_3/n46_s4/F |
| 2.056 | 0.000 | tNET | FF | 1 | R9C6[0][A] | clkdiv_3/count_16_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R9C6[0][A] | clkdiv_3/count_16_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R9C6[0][A] | clkdiv_3/count_16_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.303%; route: 0.004, 0.830%; tC2Q: 0.247, 46.867% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Path25
Path Summary:
| Slack | 0.528 |
| Data Arrival Time | 2.057 |
| Data Required Time | 1.529 |
| From | cntr4max_4/cnt_3_s0 |
| To | cntr4max_4/cnt_3_s0 |
| Launch Clk | clk27mhz:[R] |
| Latch Clk | clk27mhz:[R] |
Data Arrival Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R12C14[0][A] | cntr4max_4/cnt_3_s0/CLK |
| 1.776 | 0.247 | tC2Q | RR | 12 | R12C14[0][A] | cntr4max_4/cnt_3_s0/Q |
| 1.781 | 0.005 | tNET | RR | 1 | R12C14[0][A] | cntr4max_4/n16_s2/I3 |
| 2.057 | 0.276 | tINS | RF | 1 | R12C14[0][A] | cntr4max_4/n16_s2/F |
| 2.057 | 0.000 | tNET | FF | 1 | R12C14[0][A] | cntr4max_4/cnt_3_s0/D |
Data Required Path:
| AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
|---|---|---|---|---|---|---|
| 0.000 | 0.000 | active clock edge time | ||||
| 0.000 | 0.000 | clk27mhz | ||||
| 0.000 | 0.000 | tCL | RR | 1 | IOL6[A] | clk_ibuf/I |
| 1.392 | 1.392 | tINS | RR | 77 | IOL6[A] | clk_ibuf/O |
| 1.529 | 0.137 | tNET | RR | 1 | R12C14[0][A] | cntr4max_4/cnt_3_s0/CLK |
| 1.529 | 0.000 | tHld | 1 | R12C14[0][A] | cntr4max_4/cnt_3_s0 |
Path Statistics:
| Clock Skew | 0.000 |
| Hold Relationship | 0.000 |
| Logic Level | 2 |
| Arrival Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
| Arrival Data Path Delay | cell: 0.276, 52.217%; route: 0.005, 0.994%; tC2Q: 0.247, 46.789% |
| Required Clock Path Delay | cell: 1.392, 91.053%; route: 0.137, 8.947% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_1/count_18_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_18_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_18_s0/CLK |
MPW2
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_1/count_16_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_16_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_16_s0/CLK |
MPW3
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_1/count_12_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_12_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_12_s0/CLK |
MPW4
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_1/count_4_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_1/count_4_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_1/count_4_s0/CLK |
MPW5
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_2/count_5_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_2/count_5_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_2/count_5_s0/CLK |
MPW6
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | cntr4max_1/cnt_1_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | cntr4max_1/cnt_1_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | cntr4max_1/cnt_1_s0/CLK |
MPW7
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | cntr4max_1/cnt_2_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | cntr4max_1/cnt_2_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | cntr4max_1/cnt_2_s0/CLK |
MPW8
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | clkdiv_2/count_6_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | clkdiv_2/count_6_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | clkdiv_2/count_6_s0/CLK |
MPW9
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | cntr4maxe_1/cnt_0_s1 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | cntr4maxe_1/cnt_0_s1/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | cntr4maxe_1/cnt_0_s1/CLK |
MPW10
MPW Summary:
| Slack: | 16.613 |
| Actual Width: | 17.539 |
| Required Width: | 0.926 |
| Type: | Low Pulse Width |
| Clock: | clk27mhz |
| Objects: | cntr4maxe_1/cnt_3_s0 |
Late clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 18.518 | 0.000 | active clock edge time | ||
| 18.518 | 0.000 | clk27mhz | ||
| 18.518 | 0.000 | tCL | FF | clk_ibuf/I |
| 20.832 | 2.314 | tINS | FF | clk_ibuf/O |
| 21.026 | 0.195 | tNET | FF | cntr4maxe_1/cnt_3_s0/CLK |
Early clock Path:
| AT | DELAY | TYPE | RF | NODE |
|---|---|---|---|---|
| 37.037 | 0.000 | active clock edge time | ||
| 37.037 | 0.000 | clk27mhz | ||
| 37.037 | 0.000 | tCL | RR | clk_ibuf/I |
| 38.429 | 1.392 | tINS | RR | clk_ibuf/O |
| 38.566 | 0.137 | tNET | RR | cntr4maxe_1/cnt_3_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
| FANOUT | NET NAME | WORST SLACK | MAX DELAY |
|---|---|---|---|
| 77 | clk_d | 30.030 | 0.195 |
| 41 | active_15 | 30.030 | 1.369 |
| 22 | clk400hz | 2499995.250 | 1.052 |
| 21 | col[0] | 6249990.000 | 0.874 |
| 19 | cnt10hz[0] | 31.215 | 1.480 |
| 18 | cnt100hz[0] | 31.313 | 1.582 |
| 18 | cnt10s[0] | 32.423 | 1.225 |
| 18 | cnt10hz[1] | 31.128 | 1.578 |
| 18 | cnt1s[0] | 32.212 | 1.111 |
| 17 | cnt100hz[1] | 30.707 | 1.698 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
| GRID LOC | ROUTE CONGESTIONS |
|---|---|
| R11C13 | 68.06% |
| R8C7 | 66.67% |
| R7C9 | 65.28% |
| R9C14 | 65.28% |
| R7C6 | 63.89% |
| R8C12 | 62.50% |
| R12C14 | 61.11% |
| R7C11 | 59.72% |
| R9C9 | 59.72% |
| R7C7 | 59.72% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
| SDC Command Type | State | Detail Command |
|---|---|---|
| TC_CLOCK | Actived | create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk160hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 168750 [get_nets {clk160hz}] |
| TC_GENERATED_CLOCK | Actived | create_generated_clock -name clk400hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 67500 [get_nets {clk400hz}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk27mhz}] -group [get_clocks {clk400hz}] |
| TC_CLOCK_GROUP | Actived | set_clock_groups -asynchronous -group [get_clocks {clk27mhz}] -group [get_clocks {clk160hz}] |