Timing Messages

Report Title Timing Analysis Report
Design File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\add4bit\impl\gwsynthesis\add4bit.vg
Physical Constraints File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\add4bit\src\add4bit.cst
Timing Constraint File C:\Gowin\GW1N\KiwiNano1K\SV_241128_kiwi_nano_1K\add4bit\src\add4bit.sdc
Tool Version V1.9.10.03 (64-bit)
Part Number GW1N-UV1P5QN48XFC7/I6
Device GW1N-1P5
Device Version C
Created Time Mon Dec 16 16:47:27 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.

Timing Summaries

STA Tool Run Summary:

Setup Delay Model Slow 1.71V 85C C7/I6
Hold Delay Model Fast 3.6V 0C C7/I6
Numbers of Paths Analyzed 140
Numbers of Endpoints Analyzed 56
Numbers of Falling Endpoints 0
Numbers of Setup Violated Endpoints 0
Numbers of Hold Violated Endpoints 0

Clock Summary:

NO. Clock Name Type Period Frequency(MHz) Rise Fall Source Master Objects
1 clk27mhz Base 37.037 27.000 0.000 18.518 clk
2 clk160hz Generated 6249993.500 0.000 0.000 3124996.750 clk clk27mhz clk_160hz

Max Frequency Summary:

NO. Clock Name Constraint Actual Fmax Logic Level Entity
1 clk27mhz 27.000(MHz) 142.570(MHz) 7 TOP
2 clk160hz 0.000(MHz) 222.222(MHz) 3 TOP

Total Negative Slack Summary:

Clock Name Analysis Type Endpoints TNS Number of Endpoints
clk27mhz Setup 0.000 0
clk27mhz Hold 0.000 0
clk160hz Setup 0.000 0
clk160hz Hold 0.000 0

Timing Details

Path Slacks Table:

Setup Paths Table

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 30.023 clkdiv_1/count_7_s0/Q clkdiv_1/count_9_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.718
2 30.218 clkdiv_1/count_7_s0/Q clkdiv_1/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.523
3 30.218 clkdiv_1/count_7_s0/Q clkdiv_1/count_15_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.523
4 30.218 clkdiv_1/count_7_s0/Q clkdiv_1/count_17_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.523
5 30.240 clkdiv_1/count_7_s0/Q clkdiv_1/count_6_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.501
6 30.385 clkdiv_1/count_7_s0/Q clkdiv_1/count_7_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.355
7 30.385 clkdiv_1/count_7_s0/Q clkdiv_1/count_8_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.355
8 30.459 clkdiv_1/count_7_s0/Q clkdiv_1/count_4_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.281
9 30.459 clkdiv_1/count_7_s0/Q clkdiv_1/count_5_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.281
10 30.459 clkdiv_1/count_7_s0/Q clkdiv_1/count_14_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.281
11 30.605 clkdiv_1/count_7_s0/Q clkdiv_1/count_25_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.136
12 30.605 clkdiv_1/count_7_s0/Q clkdiv_1/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.136
13 30.605 clkdiv_1/count_7_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.136
14 30.605 clkdiv_1/count_7_s0/Q clkdiv_1/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.136
15 30.606 clkdiv_1/count_7_s0/Q clkdiv_1/count_22_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.135
16 30.606 clkdiv_1/count_7_s0/Q clkdiv_1/count_24_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.135
17 30.705 clkdiv_1/count_3_s0/Q clkdiv_1/clk_out_s1/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.035
18 30.729 clkdiv_1/count_7_s0/Q clkdiv_1/count_18_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.012
19 30.729 clkdiv_1/count_7_s0/Q clkdiv_1/count_19_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.012
20 30.729 clkdiv_1/count_7_s0/Q clkdiv_1/count_20_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.012
21 30.729 clkdiv_1/count_7_s0/Q clkdiv_1/count_21_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.012
22 30.729 clkdiv_1/count_7_s0/Q clkdiv_1/count_23_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.012
23 30.732 clkdiv_1/count_7_s0/Q clkdiv_1/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.008
24 30.732 clkdiv_1/count_7_s0/Q clkdiv_1/count_11_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.008
25 30.732 clkdiv_1/count_7_s0/Q clkdiv_1/count_12_s0/D clk27mhz:[R] clk27mhz:[R] 37.037 0.000 6.008

Hold Paths Table

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path Number Path Slack From Node To Node From Clock To Clock Relation Clock Skew Data Delay
1 0.530 mux7seg_1/col_0_s0/Q mux7seg_1/col_0_s0/D clk160hz:[R] clk160hz:[R] 0.000 0.000 0.530
2 0.786 clkdiv_1/count_0_s0/Q clkdiv_1/count_0_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.786
3 0.827 mux7seg_1/col_0_s0/Q mux7seg_1/dig_0_s1/SET clk160hz:[R] clk160hz:[R] 0.000 0.000 0.836
4 0.833 mux7seg_1/col_1_s0/Q mux7seg_1/dig_0_s1/D clk160hz:[R] clk160hz:[R] 0.000 0.000 0.833
5 0.899 mux7seg_1/col_1_s0/Q mux7seg_1/dig_1_s1/D clk160hz:[R] clk160hz:[R] 0.000 0.000 0.899
6 0.946 clkdiv_1/count_25_s0/Q clkdiv_1/clk_out_s1/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 0.946
7 1.022 mux7seg_1/col_0_s0/Q mux7seg_1/dig_1_s1/SET clk160hz:[R] clk160hz:[R] 0.000 0.000 1.032
8 1.024 mux7seg_1/col_0_s0/Q mux7seg_1/dig_2_s1/SET clk160hz:[R] clk160hz:[R] 0.000 0.000 1.033
9 1.024 mux7seg_1/col_0_s0/Q mux7seg_1/dig_3_s1/SET clk160hz:[R] clk160hz:[R] 0.000 0.000 1.033
10 1.161 clkdiv_1/count_22_s0/Q clkdiv_1/count_22_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 1.161
11 1.250 mux7seg_1/col_1_s0/Q mux7seg_1/col_1_s0/D clk160hz:[R] clk160hz:[R] 0.000 0.000 1.250
12 1.339 mux7seg_1/col_0_s0/Q mux7seg_1/seg_4_s0/D clk160hz:[R] clk160hz:[R] 0.000 0.000 1.339
13 1.495 mux7seg_1/col_0_s0/Q mux7seg_1/seg_1_s0/D clk160hz:[R] clk160hz:[R] 0.000 0.000 1.495
14 1.528 clkdiv_1/count_16_s0/Q clkdiv_1/count_13_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 1.528
15 1.528 clkdiv_1/count_16_s0/Q clkdiv_1/count_16_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 1.528
16 1.580 mux7seg_1/col_0_s0/Q mux7seg_1/seg_6_s0/D clk160hz:[R] clk160hz:[R] 0.000 0.000 1.580
17 1.603 mux7seg_1/col_1_s0/Q mux7seg_1/dig_2_s1/D clk160hz:[R] clk160hz:[R] 0.000 0.000 1.603
18 1.603 mux7seg_1/col_1_s0/Q mux7seg_1/dig_3_s1/D clk160hz:[R] clk160hz:[R] 0.000 0.000 1.603
19 1.620 clkdiv_1/count_24_s0/Q clkdiv_1/count_24_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 1.620
20 1.672 mux7seg_1/col_1_s0/Q mux7seg_1/seg_2_s0/D clk160hz:[R] clk160hz:[R] 0.000 0.000 1.672
21 1.673 clkdiv_1/count_16_s0/Q clkdiv_1/count_25_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 1.673
22 1.673 clkdiv_1/count_16_s0/Q clkdiv_1/count_1_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 1.673
23 1.673 clkdiv_1/count_16_s0/Q clkdiv_1/count_2_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 1.673
24 1.673 clkdiv_1/count_16_s0/Q clkdiv_1/count_3_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 1.673
25 1.697 clkdiv_1/count_16_s0/Q clkdiv_1/count_10_s0/D clk27mhz:[R] clk27mhz:[R] 0.000 0.000 1.697

Recovery Paths Table

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

Nothing to report!

Removal Paths Table

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

Nothing to report!

Minimum Pulse Width Table:

Report Command:report_min_pulse_width -nworst 10 -detail

Number Slack Actual Width Required Width Type Clock Objects
1 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_24_s0
2 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_22_s0
3 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_18_s0
4 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_10_s0
5 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_11_s0
6 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_19_s0
7 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_12_s0
8 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/clk_out_s1
9 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_25_s0
10 16.613 17.539 0.926 Low Pulse Width clk27mhz clkdiv_1/count_13_s0

Timing Report By Analysis Type:

Setup Analysis Report

Report Command:report_timing -setup -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 30.023
Data Arrival Time 8.986
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_9_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
8.172 0.998 tNET FF 1 R11C9[1][B] clkdiv_1/gw_add_dLut_count_9_s0/I1
8.986 0.814 tINS FF 1 R11C9[1][B] clkdiv_1/gw_add_dLut_count_9_s0/F
8.986 0.000 tNET FF 1 R11C9[1][B] clkdiv_1/count_9_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C9[1][B] clkdiv_1/count_9_s0/CLK
39.009 -0.296 tSu 1 R11C9[1][B] clkdiv_1/count_9_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.085, 60.812%; route: 2.293, 34.133%; tC2Q: 0.340, 5.056%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path2

Path Summary:

Slack 30.218
Data Arrival Time 8.791
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
8.182 1.008 tNET FF 1 R11C8[0][B] clkdiv_1/gw_add_dLut_count_0_s0/I1
8.791 0.609 tINS FF 1 R11C8[0][B] clkdiv_1/gw_add_dLut_count_0_s0/F
8.791 0.000 tNET FF 1 R11C8[0][B] clkdiv_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C8[0][B] clkdiv_1/count_0_s0/CLK
39.009 -0.296 tSu 1 R11C8[0][B] clkdiv_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.880, 59.484%; route: 2.303, 35.309%; tC2Q: 0.340, 5.207%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path3

Path Summary:

Slack 30.218
Data Arrival Time 8.791
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_15_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
8.182 1.008 tNET FF 1 R11C8[1][A] clkdiv_1/gw_add_dLut_count_15_s0/I1
8.791 0.609 tINS FF 1 R11C8[1][A] clkdiv_1/gw_add_dLut_count_15_s0/F
8.791 0.000 tNET FF 1 R11C8[1][A] clkdiv_1/count_15_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C8[1][A] clkdiv_1/count_15_s0/CLK
39.009 -0.296 tSu 1 R11C8[1][A] clkdiv_1/count_15_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.880, 59.484%; route: 2.303, 35.309%; tC2Q: 0.340, 5.207%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path4

Path Summary:

Slack 30.218
Data Arrival Time 8.791
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_17_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
8.182 1.008 tNET FF 1 R11C8[0][A] clkdiv_1/gw_add_dLut_count_17_s0/I1
8.791 0.609 tINS FF 1 R11C8[0][A] clkdiv_1/gw_add_dLut_count_17_s0/F
8.791 0.000 tNET FF 1 R11C8[0][A] clkdiv_1/count_17_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C8[0][A] clkdiv_1/count_17_s0/CLK
39.009 -0.296 tSu 1 R11C8[0][A] clkdiv_1/count_17_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.880, 59.484%; route: 2.303, 35.309%; tC2Q: 0.340, 5.207%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path5

Path Summary:

Slack 30.240
Data Arrival Time 8.769
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_6_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
8.160 0.986 tNET FF 1 R11C10[1][B] clkdiv_1/gw_add_dLut_count_6_s0/I1
8.769 0.609 tINS FF 1 R11C10[1][B] clkdiv_1/gw_add_dLut_count_6_s0/F
8.769 0.000 tNET FF 1 R11C10[1][B] clkdiv_1/count_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C10[1][B] clkdiv_1/count_6_s0/CLK
39.009 -0.296 tSu 1 R11C10[1][B] clkdiv_1/count_6_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.880, 59.684%; route: 2.281, 35.091%; tC2Q: 0.340, 5.224%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path6

Path Summary:

Slack 30.385
Data Arrival Time 8.624
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_7_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
8.160 0.986 tNET FF 1 R11C10[3][A] clkdiv_1/gw_add_dLut_count_7_s0/I1
8.624 0.464 tINS FF 1 R11C10[3][A] clkdiv_1/gw_add_dLut_count_7_s0/F
8.624 0.000 tNET FF 1 R11C10[3][A] clkdiv_1/count_7_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
39.009 -0.296 tSu 1 R11C10[3][A] clkdiv_1/count_7_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 58.763%; route: 2.281, 35.893%; tC2Q: 0.340, 5.344%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path7

Path Summary:

Slack 30.385
Data Arrival Time 8.624
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_8_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
8.160 0.986 tNET FF 1 R11C10[2][A] clkdiv_1/gw_add_dLut_count_8_s0/I1
8.624 0.464 tINS FF 1 R11C10[2][A] clkdiv_1/gw_add_dLut_count_8_s0/F
8.624 0.000 tNET FF 1 R11C10[2][A] clkdiv_1/count_8_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C10[2][A] clkdiv_1/count_8_s0/CLK
39.009 -0.296 tSu 1 R11C10[2][A] clkdiv_1/count_8_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 58.763%; route: 2.281, 35.893%; tC2Q: 0.340, 5.344%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path8

Path Summary:

Slack 30.459
Data Arrival Time 8.550
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_4_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.941 0.767 tNET FF 1 R12C9[2][A] clkdiv_1/gw_add_dLut_count_4_s0/I1
8.550 0.609 tINS FF 1 R12C9[2][A] clkdiv_1/gw_add_dLut_count_4_s0/F
8.550 0.000 tNET FF 1 R12C9[2][A] clkdiv_1/count_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C9[2][A] clkdiv_1/count_4_s0/CLK
39.009 -0.296 tSu 1 R12C9[2][A] clkdiv_1/count_4_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.880, 61.769%; route: 2.062, 32.824%; tC2Q: 0.340, 5.407%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path9

Path Summary:

Slack 30.459
Data Arrival Time 8.550
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_5_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.941 0.767 tNET FF 1 R12C9[2][B] clkdiv_1/gw_add_dLut_count_5_s0/I1
8.550 0.609 tINS FF 1 R12C9[2][B] clkdiv_1/gw_add_dLut_count_5_s0/F
8.550 0.000 tNET FF 1 R12C9[2][B] clkdiv_1/count_5_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C9[2][B] clkdiv_1/count_5_s0/CLK
39.009 -0.296 tSu 1 R12C9[2][B] clkdiv_1/count_5_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.880, 61.769%; route: 2.062, 32.824%; tC2Q: 0.340, 5.407%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path10

Path Summary:

Slack 30.459
Data Arrival Time 8.550
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_14_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.941 0.767 tNET FF 1 R12C9[3][A] clkdiv_1/gw_add_dLut_count_14_s0/I1
8.550 0.609 tINS FF 1 R12C9[3][A] clkdiv_1/gw_add_dLut_count_14_s0/F
8.550 0.000 tNET FF 1 R12C9[3][A] clkdiv_1/count_14_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C9[3][A] clkdiv_1/count_14_s0/CLK
39.009 -0.296 tSu 1 R12C9[3][A] clkdiv_1/count_14_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.880, 61.769%; route: 2.062, 32.824%; tC2Q: 0.340, 5.407%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path11

Path Summary:

Slack 30.605
Data Arrival Time 8.405
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_25_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.941 0.767 tNET FF 1 R12C9[0][A] clkdiv_1/gw_add_dLut_count_25_s0/I1
8.405 0.464 tINS FF 1 R12C9[0][A] clkdiv_1/gw_add_dLut_count_25_s0/F
8.405 0.000 tNET FF 1 R12C9[0][A] clkdiv_1/count_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C9[0][A] clkdiv_1/count_25_s0/CLK
39.009 -0.296 tSu 1 R12C9[0][A] clkdiv_1/count_25_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 60.864%; route: 2.062, 33.601%; tC2Q: 0.340, 5.535%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path12

Path Summary:

Slack 30.605
Data Arrival Time 8.405
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.941 0.767 tNET FF 1 R12C9[0][B] clkdiv_1/gw_add_dLut_count_1_s0/I1
8.405 0.464 tINS FF 1 R12C9[0][B] clkdiv_1/gw_add_dLut_count_1_s0/F
8.405 0.000 tNET FF 1 R12C9[0][B] clkdiv_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C9[0][B] clkdiv_1/count_1_s0/CLK
39.009 -0.296 tSu 1 R12C9[0][B] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 60.864%; route: 2.062, 33.601%; tC2Q: 0.340, 5.535%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path13

Path Summary:

Slack 30.605
Data Arrival Time 8.405
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.941 0.767 tNET FF 1 R12C9[1][A] clkdiv_1/gw_add_dLut_count_2_s0/I1
8.405 0.464 tINS FF 1 R12C9[1][A] clkdiv_1/gw_add_dLut_count_2_s0/F
8.405 0.000 tNET FF 1 R12C9[1][A] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C9[1][A] clkdiv_1/count_2_s0/CLK
39.009 -0.296 tSu 1 R12C9[1][A] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 60.864%; route: 2.062, 33.601%; tC2Q: 0.340, 5.535%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path14

Path Summary:

Slack 30.605
Data Arrival Time 8.405
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.941 0.767 tNET FF 1 R12C9[1][B] clkdiv_1/gw_add_dLut_count_3_s0/I1
8.405 0.464 tINS FF 1 R12C9[1][B] clkdiv_1/gw_add_dLut_count_3_s0/F
8.405 0.000 tNET FF 1 R12C9[1][B] clkdiv_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R12C9[1][B] clkdiv_1/count_3_s0/CLK
39.009 -0.296 tSu 1 R12C9[1][B] clkdiv_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 60.864%; route: 2.062, 33.601%; tC2Q: 0.340, 5.535%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path15

Path Summary:

Slack 30.606
Data Arrival Time 8.404
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_22_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.795 0.620 tNET FF 1 R9C8[2][B] clkdiv_1/gw_add_dLut_count_22_s0/I1
8.404 0.609 tINS FF 1 R9C8[2][B] clkdiv_1/gw_add_dLut_count_22_s0/F
8.404 0.000 tNET FF 1 R9C8[2][B] clkdiv_1/count_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C8[2][B] clkdiv_1/count_22_s0/CLK
39.009 -0.296 tSu 1 R9C8[2][B] clkdiv_1/count_22_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.880, 63.243%; route: 1.915, 31.221%; tC2Q: 0.340, 5.536%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path16

Path Summary:

Slack 30.606
Data Arrival Time 8.404
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_24_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.795 0.620 tNET FF 1 R8C7[3][A] clkdiv_1/gw_add_dLut_count_24_s0/I1
8.404 0.609 tINS FF 1 R8C7[3][A] clkdiv_1/gw_add_dLut_count_24_s0/F
8.404 0.000 tNET FF 1 R8C7[3][A] clkdiv_1/count_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R8C7[3][A] clkdiv_1/count_24_s0/CLK
39.009 -0.296 tSu 1 R8C7[3][A] clkdiv_1/count_24_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.880, 63.243%; route: 1.915, 31.221%; tC2Q: 0.340, 5.536%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path17

Path Summary:

Slack 30.705
Data Arrival Time 8.304
Data Required Time 39.009
From clkdiv_1/count_3_s0
To clkdiv_1/clk_out_s1
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R12C9[1][B] clkdiv_1/count_3_s0/CLK
2.608 0.340 tC2Q RF 3 R12C9[1][B] clkdiv_1/count_3_s0/Q
3.219 0.610 tNET FF 1 R11C9[3][B] clkdiv_1/clk_out_s8/I2
4.033 0.814 tINS FF 1 R11C9[3][B] clkdiv_1/clk_out_s8/F
4.037 0.004 tNET FF 1 R11C9[1][A] clkdiv_1/clk_out_s7/I2
4.802 0.765 tINS FF 1 R11C9[1][A] clkdiv_1/clk_out_s7/F
4.806 0.004 tNET FF 1 R11C9[0][A] clkdiv_1/clk_out_s6/I2
5.270 0.464 tINS FF 1 R11C9[0][A] clkdiv_1/clk_out_s6/F
5.866 0.596 tNET FF 1 R9C8[2][A] clkdiv_1/clk_out_s4/I2
6.630 0.765 tINS FF 1 R9C8[2][A] clkdiv_1/clk_out_s4/F
6.635 0.004 tNET FF 1 R9C8[1][B] clkdiv_1/clk_out_s3/I1
7.229 0.594 tINS FR 1 R9C8[1][B] clkdiv_1/clk_out_s3/F
7.539 0.310 tNET RR 1 R9C9[0][B] clkdiv_1/gw_add_dLut_clk_out_s1/I1
8.304 0.765 tINS RF 1 R9C9[0][B] clkdiv_1/gw_add_dLut_clk_out_s1/F
8.304 0.000 tNET FF 1 R9C9[0][B] clkdiv_1/clk_out_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C9[0][B] clkdiv_1/clk_out_s1/CLK
39.009 -0.296 tSu 1 R9C9[0][B] clkdiv_1/clk_out_s1

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 4.167, 69.040%; route: 1.529, 25.333%; tC2Q: 0.340, 5.627%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path18

Path Summary:

Slack 30.729
Data Arrival Time 8.280
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_18_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.816 0.642 tNET FF 1 R9C7[0][A] clkdiv_1/gw_add_dLut_count_18_s0/I1
8.280 0.464 tINS FF 1 R9C7[0][A] clkdiv_1/gw_add_dLut_count_18_s0/F
8.280 0.000 tNET FF 1 R9C7[0][A] clkdiv_1/count_18_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C7[0][A] clkdiv_1/count_18_s0/CLK
39.009 -0.296 tSu 1 R9C7[0][A] clkdiv_1/count_18_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 62.125%; route: 1.937, 32.226%; tC2Q: 0.340, 5.650%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path19

Path Summary:

Slack 30.729
Data Arrival Time 8.280
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_19_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.816 0.642 tNET FF 1 R9C7[0][B] clkdiv_1/gw_add_dLut_count_19_s0/I1
8.280 0.464 tINS FF 1 R9C7[0][B] clkdiv_1/gw_add_dLut_count_19_s0/F
8.280 0.000 tNET FF 1 R9C7[0][B] clkdiv_1/count_19_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C7[0][B] clkdiv_1/count_19_s0/CLK
39.009 -0.296 tSu 1 R9C7[0][B] clkdiv_1/count_19_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 62.125%; route: 1.937, 32.226%; tC2Q: 0.340, 5.650%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path20

Path Summary:

Slack 30.729
Data Arrival Time 8.280
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_20_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.816 0.642 tNET FF 1 R9C7[1][A] clkdiv_1/gw_add_dLut_count_20_s0/I1
8.280 0.464 tINS FF 1 R9C7[1][A] clkdiv_1/gw_add_dLut_count_20_s0/F
8.280 0.000 tNET FF 1 R9C7[1][A] clkdiv_1/count_20_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C7[1][A] clkdiv_1/count_20_s0/CLK
39.009 -0.296 tSu 1 R9C7[1][A] clkdiv_1/count_20_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 62.125%; route: 1.937, 32.226%; tC2Q: 0.340, 5.650%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path21

Path Summary:

Slack 30.729
Data Arrival Time 8.280
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_21_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.816 0.642 tNET FF 1 R9C7[1][B] clkdiv_1/gw_add_dLut_count_21_s0/I1
8.280 0.464 tINS FF 1 R9C7[1][B] clkdiv_1/gw_add_dLut_count_21_s0/F
8.280 0.000 tNET FF 1 R9C7[1][B] clkdiv_1/count_21_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C7[1][B] clkdiv_1/count_21_s0/CLK
39.009 -0.296 tSu 1 R9C7[1][B] clkdiv_1/count_21_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 62.125%; route: 1.937, 32.226%; tC2Q: 0.340, 5.650%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path22

Path Summary:

Slack 30.729
Data Arrival Time 8.280
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_23_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.816 0.642 tNET FF 1 R9C7[2][A] clkdiv_1/gw_add_dLut_count_23_s0/I1
8.280 0.464 tINS FF 1 R9C7[2][A] clkdiv_1/gw_add_dLut_count_23_s0/F
8.280 0.000 tNET FF 1 R9C7[2][A] clkdiv_1/count_23_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R9C7[2][A] clkdiv_1/count_23_s0/CLK
39.009 -0.296 tSu 1 R9C7[2][A] clkdiv_1/count_23_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 62.125%; route: 1.937, 32.226%; tC2Q: 0.340, 5.650%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path23

Path Summary:

Slack 30.732
Data Arrival Time 8.277
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.813 0.639 tNET FF 1 R11C9[2][A] clkdiv_1/gw_add_dLut_count_10_s0/I1
8.277 0.464 tINS FF 1 R11C9[2][A] clkdiv_1/gw_add_dLut_count_10_s0/F
8.277 0.000 tNET FF 1 R11C9[2][A] clkdiv_1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C9[2][A] clkdiv_1/count_10_s0/CLK
39.009 -0.296 tSu 1 R11C9[2][A] clkdiv_1/count_10_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 62.160%; route: 1.934, 32.187%; tC2Q: 0.340, 5.653%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path24

Path Summary:

Slack 30.732
Data Arrival Time 8.277
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_11_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.813 0.639 tNET FF 1 R11C9[2][B] clkdiv_1/gw_add_dLut_count_11_s0/I1
8.277 0.464 tINS FF 1 R11C9[2][B] clkdiv_1/gw_add_dLut_count_11_s0/F
8.277 0.000 tNET FF 1 R11C9[2][B] clkdiv_1/count_11_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C9[2][B] clkdiv_1/count_11_s0/CLK
39.009 -0.296 tSu 1 R11C9[2][B] clkdiv_1/count_11_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 62.160%; route: 1.934, 32.187%; tC2Q: 0.340, 5.653%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Path25

Path Summary:

Slack 30.732
Data Arrival Time 8.277
Data Required Time 39.009
From clkdiv_1/count_7_s0
To clkdiv_1/count_12_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
2.088 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
2.269 0.181 tNET RR 1 R11C10[3][A] clkdiv_1/count_7_s0/CLK
2.608 0.340 tC2Q RF 3 R11C10[3][A] clkdiv_1/count_7_s0/Q
3.581 0.972 tNET FF 1 R9C9[2][B] clkdiv_1/tc_s88/I1
4.395 0.814 tINS FF 1 R9C9[2][B] clkdiv_1/tc_s88/F
4.399 0.004 tNET FF 1 R9C9[3][B] clkdiv_1/tc_s84/I3
5.164 0.765 tINS FF 1 R9C9[3][B] clkdiv_1/tc_s84/F
5.168 0.004 tNET FF 1 R9C9[0][A] clkdiv_1/tc_s81/I0
5.933 0.765 tINS FF 1 R9C9[0][A] clkdiv_1/tc_s81/F
5.937 0.004 tNET FF 1 R9C9[1][B] clkdiv_1/tc_s79/I0
6.400 0.463 tINS FR 1 R9C9[1][B] clkdiv_1/tc_s79/F
6.710 0.310 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I1
7.174 0.464 tINS RF 26 R8C9[2][B] clkdiv_1/tc_s78/F
7.813 0.639 tNET FF 1 R11C9[3][A] clkdiv_1/gw_add_dLut_count_12_s0/I1
8.277 0.464 tINS FF 1 R11C9[3][A] clkdiv_1/gw_add_dLut_count_12_s0/F
8.277 0.000 tNET FF 1 R11C9[3][A] clkdiv_1/count_12_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
37.037 37.037 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
39.125 2.088 tINS RR 27 IOL6[A] clk_ibuf/O
39.306 0.181 tNET RR 1 R11C9[3][A] clkdiv_1/count_12_s0/CLK
39.009 -0.296 tSu 1 R11C9[3][A] clkdiv_1/count_12_s0

Path Statistics:

Clock Skew 0.000
Setup Relationship 37.037
Logic Level 7
Arrival Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%
Arrival Data Path Delay cell: 3.735, 62.160%; route: 1.934, 32.187%; tC2Q: 0.340, 5.653%
Required Clock Path Delay cell: 2.088, 92.033%; route: 0.181, 7.967%

Hold Analysis Report

Report Command:report_timing -hold -max_paths 25 -max_common_paths 1

Path1

Path Summary:

Slack 0.530
Data Arrival Time 1.088
Data Required Time 0.558
From mux7seg_1/col_0_s0
To mux7seg_1/col_0_s0
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][A] mux7seg_1/col_0_s0/CLK
0.805 0.247 tC2Q RR 19 R11C13[0][A] mux7seg_1/col_0_s0/Q
0.812 0.007 tNET RR 1 R11C13[0][A] mux7seg_1/gw_add_dLut_col_0_s0/I0
1.088 0.276 tINS RF 1 R11C13[0][A] mux7seg_1/gw_add_dLut_col_0_s0/F
1.088 0.000 tNET FF 1 R11C13[0][A] mux7seg_1/col_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][A] mux7seg_1/col_0_s0/CLK
0.558 0.000 tHld 1 R11C13[0][A] mux7seg_1/col_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.276, 52.044%; route: 0.007, 1.321%; tC2Q: 0.247, 46.635%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path2

Path Summary:

Slack 0.786
Data Arrival Time 2.315
Data Required Time 1.529
From clkdiv_1/count_0_s0
To clkdiv_1/count_0_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C8[0][B] clkdiv_1/count_0_s0/CLK
1.776 0.247 tC2Q RR 3 R11C8[0][B] clkdiv_1/count_0_s0/Q
1.778 0.003 tNET RR 1 R11C8[0][B] clkdiv_1/gw_add_dLut_count_0_s0/I0
2.315 0.536 tINS RR 1 R11C8[0][B] clkdiv_1/gw_add_dLut_count_0_s0/F
2.315 0.000 tNET RR 1 R11C8[0][B] clkdiv_1/count_0_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C8[0][B] clkdiv_1/count_0_s0/CLK
1.529 0.000 tHld 1 R11C8[0][B] clkdiv_1/count_0_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.536, 68.246%; route: 0.003, 0.334%; tC2Q: 0.247, 31.421%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path3

Path Summary:

Slack 0.827
Data Arrival Time 1.394
Data Required Time 0.568
From mux7seg_1/col_0_s0
To mux7seg_1/dig_0_s1
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][A] mux7seg_1/col_0_s0/CLK
0.805 0.247 tC2Q RR 19 R11C13[0][A] mux7seg_1/col_0_s0/Q
1.394 0.589 tNET RR 1 IOR13[B] mux7seg_1/dig_0_s1/SET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOR13[B] mux7seg_1/dig_0_s1/CLK
0.568 0.009 tHld 1 IOR13[B] mux7seg_1/dig_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.589, 70.457%; tC2Q: 0.247, 29.543%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path4

Path Summary:

Slack 0.833
Data Arrival Time 1.392
Data Required Time 0.558
From mux7seg_1/col_1_s0
To mux7seg_1/dig_0_s1
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][B] mux7seg_1/col_1_s0/CLK
0.805 0.247 tC2Q RR 16 R11C13[0][B] mux7seg_1/col_1_s0/Q
1.392 0.586 tNET RR 1 IOR13[B] mux7seg_1/dig_0_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOR13[B] mux7seg_1/dig_0_s1/CLK
0.558 0.000 tHld 1 IOR13[B] mux7seg_1/dig_0_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.586, 70.359%; tC2Q: 0.247, 29.641%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path5

Path Summary:

Slack 0.899
Data Arrival Time 1.458
Data Required Time 0.558
From mux7seg_1/col_1_s0
To mux7seg_1/dig_1_s1
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][B] mux7seg_1/col_1_s0/CLK
0.805 0.247 tC2Q RR 16 R11C13[0][B] mux7seg_1/col_1_s0/Q
1.458 0.652 tNET RR 1 IOR15[A] mux7seg_1/dig_1_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOR15[A] mux7seg_1/dig_1_s1/CLK
0.558 0.000 tHld 1 IOR15[A] mux7seg_1/dig_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.652, 72.540%; tC2Q: 0.247, 27.460%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path6

Path Summary:

Slack 0.946
Data Arrival Time 2.475
Data Required Time 1.529
From clkdiv_1/count_25_s0
To clkdiv_1/clk_out_s1
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C9[0][A] clkdiv_1/count_25_s0/CLK
1.776 0.247 tC2Q RR 3 R12C9[0][A] clkdiv_1/count_25_s0/Q
2.199 0.424 tNET RR 1 R9C9[0][B] clkdiv_1/gw_add_dLut_clk_out_s1/I0
2.475 0.276 tINS RF 1 R9C9[0][B] clkdiv_1/gw_add_dLut_clk_out_s1/F
2.475 0.000 tNET FF 1 R9C9[0][B] clkdiv_1/clk_out_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C9[0][B] clkdiv_1/clk_out_s1/CLK
1.529 0.000 tHld 1 R9C9[0][B] clkdiv_1/clk_out_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.276, 29.133%; route: 0.424, 44.762%; tC2Q: 0.247, 26.105%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path7

Path Summary:

Slack 1.022
Data Arrival Time 1.590
Data Required Time 0.568
From mux7seg_1/col_0_s0
To mux7seg_1/dig_1_s1
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][A] mux7seg_1/col_0_s0/CLK
0.805 0.247 tC2Q RR 19 R11C13[0][A] mux7seg_1/col_0_s0/Q
1.590 0.785 tNET RR 1 IOR15[A] mux7seg_1/dig_1_s1/SET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOR15[A] mux7seg_1/dig_1_s1/CLK
0.568 0.009 tHld 1 IOR15[A] mux7seg_1/dig_1_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.785, 76.055%; tC2Q: 0.247, 23.945%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path8

Path Summary:

Slack 1.024
Data Arrival Time 1.592
Data Required Time 0.568
From mux7seg_1/col_0_s0
To mux7seg_1/dig_2_s1
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][A] mux7seg_1/col_0_s0/CLK
0.805 0.247 tC2Q RR 19 R11C13[0][A] mux7seg_1/col_0_s0/Q
1.592 0.786 tNET RR 1 IOT15[B] mux7seg_1/dig_2_s1/SET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOT15[B] mux7seg_1/dig_2_s1/CLK
0.568 0.009 tHld 1 IOT15[B] mux7seg_1/dig_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.786, 76.097%; tC2Q: 0.247, 23.903%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path9

Path Summary:

Slack 1.024
Data Arrival Time 1.592
Data Required Time 0.568
From mux7seg_1/col_0_s0
To mux7seg_1/dig_3_s1
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][A] mux7seg_1/col_0_s0/CLK
0.805 0.247 tC2Q RR 19 R11C13[0][A] mux7seg_1/col_0_s0/Q
1.592 0.786 tNET RR 1 IOT15[A] mux7seg_1/dig_3_s1/SET

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOT15[A] mux7seg_1/dig_3_s1/CLK
0.568 0.009 tHld 1 IOT15[A] mux7seg_1/dig_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 1
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.000, 0.000%; route: 0.786, 76.097%; tC2Q: 0.247, 23.903%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path10

Path Summary:

Slack 1.161
Data Arrival Time 2.689
Data Required Time 1.529
From clkdiv_1/count_22_s0
To clkdiv_1/count_22_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C8[2][B] clkdiv_1/count_22_s0/CLK
1.776 0.247 tC2Q RF 3 R9C8[2][B] clkdiv_1/count_22_s0/Q
1.950 0.174 tNET FF 2 R8C8[2][A] clkdiv_1/n14_s/I1
2.241 0.292 tINS FF 1 R8C8[2][A] clkdiv_1/n14_s/SUM
2.414 0.172 tNET FF 1 R9C8[2][B] clkdiv_1/gw_add_dLut_count_22_s0/I0
2.689 0.276 tINS FF 1 R9C8[2][B] clkdiv_1/gw_add_dLut_count_22_s0/F
2.689 0.000 tNET FF 1 R9C8[2][B] clkdiv_1/count_22_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R9C8[2][B] clkdiv_1/count_22_s0/CLK
1.529 0.000 tHld 1 R9C8[2][B] clkdiv_1/count_22_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.568, 48.908%; route: 0.346, 29.810%; tC2Q: 0.247, 21.283%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path11

Path Summary:

Slack 1.250
Data Arrival Time 1.809
Data Required Time 0.558
From mux7seg_1/col_1_s0
To mux7seg_1/col_1_s0
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][B] mux7seg_1/col_1_s0/CLK
0.805 0.247 tC2Q RF 16 R11C13[0][B] mux7seg_1/col_1_s0/Q
0.993 0.188 tNET FF 1 R11C13[1][B] mux7seg_1/n9_s3/I1
1.269 0.276 tINS FF 1 R11C13[1][B] mux7seg_1/n9_s3/F
1.272 0.003 tNET FF 1 R11C13[0][B] mux7seg_1/gw_add_dLut_col_1_s0/I0
1.809 0.536 tINS FR 1 R11C13[0][B] mux7seg_1/gw_add_dLut_col_1_s0/F
1.809 0.000 tNET RR 1 R11C13[0][B] mux7seg_1/col_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][B] mux7seg_1/col_1_s0/CLK
0.558 0.000 tHld 1 R11C13[0][B] mux7seg_1/col_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.812, 64.945%; route: 0.191, 15.302%; tC2Q: 0.247, 19.752%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path12

Path Summary:

Slack 1.339
Data Arrival Time 1.897
Data Required Time 0.558
From mux7seg_1/col_0_s0
To mux7seg_1/seg_4_s0
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][A] mux7seg_1/col_0_s0/CLK
0.805 0.247 tC2Q RR 19 R11C13[0][A] mux7seg_1/col_0_s0/Q
1.010 0.205 tNET RR 1 R11C11[3][B] mux7seg_1/n16_s4/I2
1.296 0.285 tINS RR 1 R11C11[3][B] mux7seg_1/n16_s4/F
1.897 0.602 tNET RR 1 IOB7[A] mux7seg_1/seg_4_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOB7[A] mux7seg_1/seg_4_s0/CLK
0.558 0.000 tHld 1 IOB7[A] mux7seg_1/seg_4_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.285, 21.304%; route: 0.807, 60.251%; tC2Q: 0.247, 18.445%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path13

Path Summary:

Slack 1.495
Data Arrival Time 2.054
Data Required Time 0.558
From mux7seg_1/col_0_s0
To mux7seg_1/seg_1_s0
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][A] mux7seg_1/col_0_s0/CLK
0.805 0.247 tC2Q RF 19 R11C13[0][A] mux7seg_1/col_0_s0/Q
1.009 0.204 tNET FF 1 R11C12[2][A] mux7seg_1/n19_s5/I0
1.421 0.412 tINS FR 1 R11C12[2][A] mux7seg_1/n19_s5/F
2.054 0.633 tNET RR 1 IOB9[B] mux7seg_1/seg_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOB9[B] mux7seg_1/seg_1_s0/CLK
0.558 0.000 tHld 1 IOB9[B] mux7seg_1/seg_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.412, 27.554%; route: 0.836, 55.927%; tC2Q: 0.247, 16.519%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path14

Path Summary:

Slack 1.528
Data Arrival Time 3.057
Data Required Time 1.529
From clkdiv_1/count_16_s0
To clkdiv_1/count_13_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C9[2][A] clkdiv_1/count_16_s0/CLK
1.776 0.247 tC2Q RR 3 R8C9[2][A] clkdiv_1/count_16_s0/Q
1.974 0.198 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I0
2.510 0.536 tINS RR 26 R8C9[2][B] clkdiv_1/tc_s78/F
2.519 0.008 tNET RR 1 R8C9[1][B] clkdiv_1/gw_add_dLut_count_13_s0/I1
3.057 0.538 tINS RR 1 R8C9[1][B] clkdiv_1/gw_add_dLut_count_13_s0/F
3.057 0.000 tNET RR 1 R8C9[1][B] clkdiv_1/count_13_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C9[1][B] clkdiv_1/count_13_s0/CLK
1.529 0.000 tHld 1 R8C9[1][B] clkdiv_1/count_13_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 1.074, 70.329%; route: 0.206, 13.503%; tC2Q: 0.247, 16.168%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path15

Path Summary:

Slack 1.528
Data Arrival Time 3.057
Data Required Time 1.529
From clkdiv_1/count_16_s0
To clkdiv_1/count_16_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C9[2][A] clkdiv_1/count_16_s0/CLK
1.776 0.247 tC2Q RR 3 R8C9[2][A] clkdiv_1/count_16_s0/Q
1.974 0.198 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I0
2.510 0.536 tINS RR 26 R8C9[2][B] clkdiv_1/tc_s78/F
2.519 0.008 tNET RR 1 R8C9[2][A] clkdiv_1/gw_add_dLut_count_16_s0/I1
3.057 0.538 tINS RR 1 R8C9[2][A] clkdiv_1/gw_add_dLut_count_16_s0/F
3.057 0.000 tNET RR 1 R8C9[2][A] clkdiv_1/count_16_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C9[2][A] clkdiv_1/count_16_s0/CLK
1.529 0.000 tHld 1 R8C9[2][A] clkdiv_1/count_16_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 1.074, 70.329%; route: 0.206, 13.503%; tC2Q: 0.247, 16.168%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path16

Path Summary:

Slack 1.580
Data Arrival Time 2.138
Data Required Time 0.558
From mux7seg_1/col_0_s0
To mux7seg_1/seg_6_s0
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][A] mux7seg_1/col_0_s0/CLK
0.805 0.247 tC2Q RR 19 R11C13[0][A] mux7seg_1/col_0_s0/Q
1.237 0.432 tNET RR 1 R12C12[3][A] mux7seg_1/n14_s4/I2
1.523 0.285 tINS RR 1 R12C12[3][A] mux7seg_1/n14_s4/F
2.138 0.616 tNET RR 1 IOB2[A] mux7seg_1/seg_6_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOB2[A] mux7seg_1/seg_6_s0/CLK
0.558 0.000 tHld 1 IOB2[A] mux7seg_1/seg_6_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.285, 18.055%; route: 1.048, 66.312%; tC2Q: 0.247, 15.632%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path17

Path Summary:

Slack 1.603
Data Arrival Time 2.161
Data Required Time 0.558
From mux7seg_1/col_1_s0
To mux7seg_1/dig_2_s1
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][B] mux7seg_1/col_1_s0/CLK
0.805 0.247 tC2Q RR 16 R11C13[0][B] mux7seg_1/col_1_s0/Q
1.444 0.638 tNET RR 1 R2C15[0][A] mux7seg_1/n21_s11/I0
1.986 0.542 tINS RF 2 R2C15[0][A] mux7seg_1/n21_s11/F
2.161 0.175 tNET FF 1 IOT15[B] mux7seg_1/dig_2_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOT15[B] mux7seg_1/dig_2_s1/CLK
0.558 0.000 tHld 1 IOT15[B] mux7seg_1/dig_2_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.542, 33.833%; route: 0.814, 50.761%; tC2Q: 0.247, 15.406%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path18

Path Summary:

Slack 1.603
Data Arrival Time 2.161
Data Required Time 0.558
From mux7seg_1/col_1_s0
To mux7seg_1/dig_3_s1
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][B] mux7seg_1/col_1_s0/CLK
0.805 0.247 tC2Q RR 16 R11C13[0][B] mux7seg_1/col_1_s0/Q
1.444 0.638 tNET RR 1 R2C15[0][A] mux7seg_1/n21_s11/I0
1.986 0.542 tINS RF 2 R2C15[0][A] mux7seg_1/n21_s11/F
2.161 0.175 tNET FF 1 IOT15[A] mux7seg_1/dig_3_s1/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOT15[A] mux7seg_1/dig_3_s1/CLK
0.558 0.000 tHld 1 IOT15[A] mux7seg_1/dig_3_s1

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.542, 33.833%; route: 0.814, 50.761%; tC2Q: 0.247, 15.406%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path19

Path Summary:

Slack 1.620
Data Arrival Time 3.149
Data Required Time 1.529
From clkdiv_1/count_24_s0
To clkdiv_1/count_24_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C7[3][A] clkdiv_1/count_24_s0/CLK
1.776 0.247 tC2Q RR 2 R8C7[3][A] clkdiv_1/count_24_s0/Q
2.146 0.371 tNET RR 2 R8C9[0][A] clkdiv_1/n12_s/I1
2.438 0.292 tINS RF 1 R8C9[0][A] clkdiv_1/n12_s/SUM
2.873 0.435 tNET FF 1 R8C7[3][A] clkdiv_1/gw_add_dLut_count_24_s0/I0
3.149 0.276 tINS FF 1 R8C7[3][A] clkdiv_1/gw_add_dLut_count_24_s0/F
3.149 0.000 tNET FF 1 R8C7[3][A] clkdiv_1/count_24_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C7[3][A] clkdiv_1/count_24_s0/CLK
1.529 0.000 tHld 1 R8C7[3][A] clkdiv_1/count_24_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.568, 35.032%; route: 0.806, 49.724%; tC2Q: 0.247, 15.245%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path20

Path Summary:

Slack 1.672
Data Arrival Time 2.230
Data Required Time 0.558
From mux7seg_1/col_1_s0
To mux7seg_1/seg_2_s0
Launch Clk clk160hz:[R]
Latch Clk clk160hz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 R11C13[0][B] mux7seg_1/col_1_s0/CLK
0.805 0.247 tC2Q RR 16 R11C13[0][B] mux7seg_1/col_1_s0/Q
1.238 0.433 tNET RR 1 R12C11[1][A] mux7seg_1/n18_s4/I2
1.650 0.412 tINS RR 1 R12C11[1][A] mux7seg_1/n18_s4/F
2.230 0.580 tNET RR 1 IOB9[A] mux7seg_1/seg_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk160hz
0.000 0.000 tCL RR 13 R9C9[0][B] clkdiv_1/clk_out_s1/Q
0.558 0.558 tNET RR 1 IOB9[A] mux7seg_1/seg_2_s0/CLK
0.558 0.000 tHld 1 IOB9[A] mux7seg_1/seg_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 2
Arrival Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%
Arrival Data Path Delay cell: 0.412, 24.639%; route: 1.013, 60.589%; tC2Q: 0.247, 14.772%
Required Clock Path Delay cell: 0.000, 0.000%; route: 0.558, 100.000%

Path21

Path Summary:

Slack 1.673
Data Arrival Time 3.202
Data Required Time 1.529
From clkdiv_1/count_16_s0
To clkdiv_1/count_25_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C9[2][A] clkdiv_1/count_16_s0/CLK
1.776 0.247 tC2Q RR 3 R8C9[2][A] clkdiv_1/count_16_s0/Q
1.974 0.198 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I0
2.510 0.536 tINS RR 26 R8C9[2][B] clkdiv_1/tc_s78/F
2.926 0.416 tNET RR 1 R12C9[0][A] clkdiv_1/gw_add_dLut_count_25_s0/I1
3.202 0.276 tINS RF 1 R12C9[0][A] clkdiv_1/gw_add_dLut_count_25_s0/F
3.202 0.000 tNET FF 1 R12C9[0][A] clkdiv_1/count_25_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C9[0][A] clkdiv_1/count_25_s0/CLK
1.529 0.000 tHld 1 R12C9[0][A] clkdiv_1/count_25_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.812, 48.544%; route: 0.614, 36.691%; tC2Q: 0.247, 14.764%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path22

Path Summary:

Slack 1.673
Data Arrival Time 3.202
Data Required Time 1.529
From clkdiv_1/count_16_s0
To clkdiv_1/count_1_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C9[2][A] clkdiv_1/count_16_s0/CLK
1.776 0.247 tC2Q RR 3 R8C9[2][A] clkdiv_1/count_16_s0/Q
1.974 0.198 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I0
2.510 0.536 tINS RR 26 R8C9[2][B] clkdiv_1/tc_s78/F
2.926 0.416 tNET RR 1 R12C9[0][B] clkdiv_1/gw_add_dLut_count_1_s0/I1
3.202 0.276 tINS RF 1 R12C9[0][B] clkdiv_1/gw_add_dLut_count_1_s0/F
3.202 0.000 tNET FF 1 R12C9[0][B] clkdiv_1/count_1_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C9[0][B] clkdiv_1/count_1_s0/CLK
1.529 0.000 tHld 1 R12C9[0][B] clkdiv_1/count_1_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.812, 48.544%; route: 0.614, 36.691%; tC2Q: 0.247, 14.764%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path23

Path Summary:

Slack 1.673
Data Arrival Time 3.202
Data Required Time 1.529
From clkdiv_1/count_16_s0
To clkdiv_1/count_2_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C9[2][A] clkdiv_1/count_16_s0/CLK
1.776 0.247 tC2Q RR 3 R8C9[2][A] clkdiv_1/count_16_s0/Q
1.974 0.198 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I0
2.510 0.536 tINS RR 26 R8C9[2][B] clkdiv_1/tc_s78/F
2.926 0.416 tNET RR 1 R12C9[1][A] clkdiv_1/gw_add_dLut_count_2_s0/I1
3.202 0.276 tINS RF 1 R12C9[1][A] clkdiv_1/gw_add_dLut_count_2_s0/F
3.202 0.000 tNET FF 1 R12C9[1][A] clkdiv_1/count_2_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C9[1][A] clkdiv_1/count_2_s0/CLK
1.529 0.000 tHld 1 R12C9[1][A] clkdiv_1/count_2_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.812, 48.544%; route: 0.614, 36.691%; tC2Q: 0.247, 14.764%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path24

Path Summary:

Slack 1.673
Data Arrival Time 3.202
Data Required Time 1.529
From clkdiv_1/count_16_s0
To clkdiv_1/count_3_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C9[2][A] clkdiv_1/count_16_s0/CLK
1.776 0.247 tC2Q RR 3 R8C9[2][A] clkdiv_1/count_16_s0/Q
1.974 0.198 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I0
2.510 0.536 tINS RR 26 R8C9[2][B] clkdiv_1/tc_s78/F
2.926 0.416 tNET RR 1 R12C9[1][B] clkdiv_1/gw_add_dLut_count_3_s0/I1
3.202 0.276 tINS RF 1 R12C9[1][B] clkdiv_1/gw_add_dLut_count_3_s0/F
3.202 0.000 tNET FF 1 R12C9[1][B] clkdiv_1/count_3_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R12C9[1][B] clkdiv_1/count_3_s0/CLK
1.529 0.000 tHld 1 R12C9[1][B] clkdiv_1/count_3_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.812, 48.544%; route: 0.614, 36.691%; tC2Q: 0.247, 14.764%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Path25

Path Summary:

Slack 1.697
Data Arrival Time 3.225
Data Required Time 1.529
From clkdiv_1/count_16_s0
To clkdiv_1/count_10_s0
Launch Clk clk27mhz:[R]
Latch Clk clk27mhz:[R]

Data Arrival Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R8C9[2][A] clkdiv_1/count_16_s0/CLK
1.776 0.247 tC2Q RR 3 R8C9[2][A] clkdiv_1/count_16_s0/Q
1.974 0.198 tNET RR 1 R8C9[2][B] clkdiv_1/tc_s78/I0
2.510 0.536 tINS RR 26 R8C9[2][B] clkdiv_1/tc_s78/F
2.950 0.439 tNET RR 1 R11C9[2][A] clkdiv_1/gw_add_dLut_count_10_s0/I1
3.225 0.276 tINS RF 1 R11C9[2][A] clkdiv_1/gw_add_dLut_count_10_s0/F
3.225 0.000 tNET FF 1 R11C9[2][A] clkdiv_1/count_10_s0/D

Data Required Path:

AT DELAY TYPE RF FANOUT LOC NODE
0.000 0.000 active clock edge time
0.000 0.000 clk27mhz
0.000 0.000 tCL RR 1 IOL6[A] clk_ibuf/I
1.392 1.392 tINS RR 27 IOL6[A] clk_ibuf/O
1.529 0.137 tNET RR 1 R11C9[2][A] clkdiv_1/count_10_s0/CLK
1.529 0.000 tHld 1 R11C9[2][A] clkdiv_1/count_10_s0

Path Statistics:

Clock Skew 0.000
Hold Relationship 0.000
Logic Level 3
Arrival Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%
Arrival Data Path Delay cell: 0.812, 47.868%; route: 0.637, 37.574%; tC2Q: 0.247, 14.558%
Required Clock Path Delay cell: 1.392, 91.053%; route: 0.137, 8.947%

Recovery Analysis Report

Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1

No recovery paths to report!

Removal Analysis Report

Report Command:report_timing -removal -max_paths 25 -max_common_paths 1

No removal paths to report!

Minimum Pulse Width Report:

Report Command:report_min_pulse_width -nworst 10 -detail

MPW1

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_24_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_24_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_24_s0/CLK

MPW2

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_22_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_22_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_22_s0/CLK

MPW3

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_18_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_18_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_18_s0/CLK

MPW4

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_10_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_10_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_10_s0/CLK

MPW5

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_11_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_11_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_11_s0/CLK

MPW6

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_19_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_19_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_19_s0/CLK

MPW7

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_12_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_12_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_12_s0/CLK

MPW8

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/clk_out_s1

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/clk_out_s1/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/clk_out_s1/CLK

MPW9

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_25_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_25_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_25_s0/CLK

MPW10

MPW Summary:

Slack: 16.613
Actual Width: 17.539
Required Width: 0.926
Type: Low Pulse Width
Clock: clk27mhz
Objects: clkdiv_1/count_13_s0

Late clock Path:

AT DELAY TYPE RF NODE
18.518 0.000 active clock edge time
18.518 0.000 clk27mhz
18.518 0.000 tCL FF clk_ibuf/I
20.832 2.314 tINS FF clk_ibuf/O
21.026 0.195 tNET FF clkdiv_1/count_13_s0/CLK

Early clock Path:

AT DELAY TYPE RF NODE
37.037 0.000 active clock edge time
37.037 0.000 clk27mhz
37.037 0.000 tCL RR clk_ibuf/I
38.429 1.392 tINS RR clk_ibuf/O
38.566 0.137 tNET RR clkdiv_1/count_13_s0/CLK

High Fanout Nets Report:

Report Command:report_high_fanout_nets -max_nets 10

FANOUT NET NAME WORST SLACK MAX DELAY
27 clk_d 30.023 0.195
26 tc 30.023 1.008
19 col[0] 6249989.000 1.476
16 col[1] 6249989.000 1.219
13 clk_160hz 6249988.500 0.785
3 count[11] 31.746 1.319
3 count[12] 31.973 1.560
3 count[9] 32.082 1.325
3 count[10] 31.902 1.319
3 count[5] 31.037 1.208

Route Congestions Report:

Report Command:report_route_congestion -max_grids 10

GRID LOC ROUTE CONGESTIONS
R12C9 83.33%
R9C7 65.28%
R11C9 61.11%
R11C13 58.33%
R11C8 51.39%
R8C9 44.44%
R11C10 38.89%
R8C7 33.33%
R9C8 31.94%
R9C9 31.94%

Timing Exceptions Report:

Setup Analysis Report

Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Hold Analysis Report

Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Recovery Analysis Report

Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Removal Analysis Report

Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1

No timing exceptions to report!

Timing Constraints Report:

SDC Command Type State Detail Command
TC_CLOCK Actived create_clock -name clk27mhz -period 37.037 -waveform {0 18.518} [get_ports {clk}]
TC_GENERATED_CLOCK Actived create_generated_clock -name clk160hz -source [get_ports {clk}] -master_clock clk27mhz -divide_by 168750 [get_nets {clk_160hz}]